1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MipsMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14 
15 #include "MipsMCCodeEmitter.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCExpr.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCFixup.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/raw_ostream.h"
29 
30 #define DEBUG_TYPE "mccodeemitter"
31 
32 #define GET_INSTRMAP_INFO
33 #include "MipsGenInstrInfo.inc"
34 #undef GET_INSTRMAP_INFO
35 
36 namespace llvm {
37 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
38                                          const MCRegisterInfo &MRI,
39                                          MCContext &Ctx) {
40   return new MipsMCCodeEmitter(MCII, Ctx, false);
41 }
42 
43 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
44                                          const MCRegisterInfo &MRI,
45                                          MCContext &Ctx) {
46   return new MipsMCCodeEmitter(MCII, Ctx, true);
47 }
48 } // End of namespace llvm.
49 
50 // If the D<shift> instruction has a shift amount that is greater
51 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
52 static void LowerLargeShift(MCInst& Inst) {
53 
54   assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
55   assert(Inst.getOperand(2).isImm());
56 
57   int64_t Shift = Inst.getOperand(2).getImm();
58   if (Shift <= 31)
59     return; // Do nothing
60   Shift -= 32;
61 
62   // saminus32
63   Inst.getOperand(2).setImm(Shift);
64 
65   switch (Inst.getOpcode()) {
66   default:
67     // Calling function is not synchronized
68     llvm_unreachable("Unexpected shift instruction");
69   case Mips::DSLL:
70     Inst.setOpcode(Mips::DSLL32);
71     return;
72   case Mips::DSRL:
73     Inst.setOpcode(Mips::DSRL32);
74     return;
75   case Mips::DSRA:
76     Inst.setOpcode(Mips::DSRA32);
77     return;
78   case Mips::DROTR:
79     Inst.setOpcode(Mips::DROTR32);
80     return;
81   }
82 }
83 
84 // Pick a DINS instruction variant based on the pos and size operands
85 static void LowerDins(MCInst& InstIn) {
86   assert(InstIn.getNumOperands() == 5 &&
87          "Invalid no. of machine operands for DINS!");
88 
89   assert(InstIn.getOperand(2).isImm());
90   int64_t pos = InstIn.getOperand(2).getImm();
91   assert(InstIn.getOperand(3).isImm());
92   int64_t size = InstIn.getOperand(3).getImm();
93 
94   if (size <= 32) {
95     if (pos < 32)  // DINS, do nothing
96       return;
97     // DINSU
98     InstIn.getOperand(2).setImm(pos - 32);
99     InstIn.setOpcode(Mips::DINSU);
100     return;
101   }
102   // DINSM
103   assert(pos < 32 && "DINS cannot have both size and pos > 32");
104   InstIn.getOperand(3).setImm(size - 32);
105   InstIn.setOpcode(Mips::DINSM);
106   return;
107 }
108 
109 // Fix a bad compact branch encoding for beqc/bnec.
110 void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
111 
112   // Encoding may be illegal !(rs < rt), but this situation is
113   // easily fixed.
114   unsigned RegOp0 = Inst.getOperand(0).getReg();
115   unsigned RegOp1 = Inst.getOperand(1).getReg();
116 
117   unsigned Reg0 =  Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
118   unsigned Reg1 =  Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
119 
120   if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC) {
121     assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!");
122     if (Reg0 < Reg1)
123       return;
124   } else if (Inst.getOpcode() == Mips::BNVC || Inst.getOpcode() == Mips::BOVC) {
125     if (Reg0 >= Reg1)
126       return;
127   } else if (Inst.getOpcode() == Mips::BNVC_MMR6 ||
128              Inst.getOpcode() == Mips::BOVC_MMR6) {
129     if (Reg1 >= Reg0)
130       return;
131   } else
132    llvm_unreachable("Cannot rewrite unknown branch!");
133 
134   Inst.getOperand(0).setReg(RegOp1);
135   Inst.getOperand(1).setReg(RegOp0);
136 
137 }
138 
139 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
140   return STI.getFeatureBits()[Mips::FeatureMicroMips];
141 }
142 
143 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
144   return STI.getFeatureBits()[Mips::FeatureMips32r6];
145 }
146 
147 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
148   OS << (char)C;
149 }
150 
151 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
152                                         const MCSubtargetInfo &STI,
153                                         raw_ostream &OS) const {
154   // Output the instruction encoding in little endian byte order.
155   // Little-endian byte ordering:
156   //   mips32r2:   4 | 3 | 2 | 1
157   //   microMIPS:  2 | 1 | 4 | 3
158   if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
159     EmitInstruction(Val >> 16, 2, STI, OS);
160     EmitInstruction(Val, 2, STI, OS);
161   } else {
162     for (unsigned i = 0; i < Size; ++i) {
163       unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
164       EmitByte((Val >> Shift) & 0xff, OS);
165     }
166   }
167 }
168 
169 /// encodeInstruction - Emit the instruction.
170 /// Size the instruction with Desc.getSize().
171 void MipsMCCodeEmitter::
172 encodeInstruction(const MCInst &MI, raw_ostream &OS,
173                   SmallVectorImpl<MCFixup> &Fixups,
174                   const MCSubtargetInfo &STI) const
175 {
176 
177   // Non-pseudo instructions that get changed for direct object
178   // only based on operand values.
179   // If this list of instructions get much longer we will move
180   // the check to a function call. Until then, this is more efficient.
181   MCInst TmpInst = MI;
182   switch (MI.getOpcode()) {
183   // If shift amount is >= 32 it the inst needs to be lowered further
184   case Mips::DSLL:
185   case Mips::DSRL:
186   case Mips::DSRA:
187   case Mips::DROTR:
188     LowerLargeShift(TmpInst);
189     break;
190     // Double extract instruction is chosen by pos and size operands
191   case Mips::DINS:
192     LowerDins(TmpInst);
193     break;
194   // Compact branches, enforce encoding restrictions.
195   case Mips::BEQC:
196   case Mips::BNEC:
197   case Mips::BOVC:
198   case Mips::BOVC_MMR6:
199   case Mips::BNVC:
200   case Mips::BNVC_MMR6:
201     LowerCompactBranch(TmpInst);
202   }
203 
204   unsigned long N = Fixups.size();
205   uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
206 
207   // Check for unimplemented opcodes.
208   // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
209   // so we have to special check for them.
210   unsigned Opcode = TmpInst.getOpcode();
211   if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
212       (Opcode != Mips::SLL_MM) && !Binary)
213     llvm_unreachable("unimplemented opcode in encodeInstruction()");
214 
215   int NewOpcode = -1;
216   if (isMicroMips(STI)) {
217     if (isMips32r6(STI)) {
218       NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
219       if (NewOpcode == -1)
220         NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
221     }
222     else
223       NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
224 
225     // Check whether it is Dsp instruction.
226     if (NewOpcode == -1)
227       NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
228 
229     if (NewOpcode != -1) {
230       if (Fixups.size() > N)
231         Fixups.pop_back();
232 
233       Opcode = NewOpcode;
234       TmpInst.setOpcode (NewOpcode);
235       Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
236     }
237   }
238 
239   const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
240 
241   // Get byte count of instruction
242   unsigned Size = Desc.getSize();
243   if (!Size)
244     llvm_unreachable("Desc.getSize() returns 0");
245 
246   EmitInstruction(Binary, Size, STI, OS);
247 }
248 
249 /// getBranchTargetOpValue - Return binary encoding of the branch
250 /// target operand. If the machine operand requires relocation,
251 /// record the relocation and return zero.
252 unsigned MipsMCCodeEmitter::
253 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
254                        SmallVectorImpl<MCFixup> &Fixups,
255                        const MCSubtargetInfo &STI) const {
256 
257   const MCOperand &MO = MI.getOperand(OpNo);
258 
259   // If the destination is an immediate, divide by 4.
260   if (MO.isImm()) return MO.getImm() >> 2;
261 
262   assert(MO.isExpr() &&
263          "getBranchTargetOpValue expects only expressions or immediates");
264 
265   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
266       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
267   Fixups.push_back(MCFixup::create(0, FixupExpression,
268                                    MCFixupKind(Mips::fixup_Mips_PC16)));
269   return 0;
270 }
271 
272 /// getBranchTargetOpValue1SImm16 - Return binary encoding of the branch
273 /// target operand. If the machine operand requires relocation,
274 /// record the relocation and return zero.
275 unsigned MipsMCCodeEmitter::
276 getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
277                               SmallVectorImpl<MCFixup> &Fixups,
278                               const MCSubtargetInfo &STI) const {
279 
280   const MCOperand &MO = MI.getOperand(OpNo);
281 
282   // If the destination is an immediate, divide by 2.
283   if (MO.isImm()) return MO.getImm() >> 1;
284 
285   assert(MO.isExpr() &&
286          "getBranchTargetOpValue expects only expressions or immediates");
287 
288   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
289       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
290   Fixups.push_back(MCFixup::create(0, FixupExpression,
291                                    MCFixupKind(Mips::fixup_Mips_PC16)));
292   return 0;
293 }
294 
295 /// getBranchTargetOpValueMMR6 - Return binary encoding of the branch
296 /// target operand. If the machine operand requires relocation,
297 /// record the relocation and return zero.
298 unsigned MipsMCCodeEmitter::
299 getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
300                            SmallVectorImpl<MCFixup> &Fixups,
301                            const MCSubtargetInfo &STI) const {
302 
303   const MCOperand &MO = MI.getOperand(OpNo);
304 
305   // If the destination is an immediate, divide by 2.
306   if (MO.isImm())
307     return MO.getImm() >> 1;
308 
309   assert(MO.isExpr() &&
310          "getBranchTargetOpValueMMR6 expects only expressions or immediates");
311 
312   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
313       MO.getExpr(), MCConstantExpr::create(-2, Ctx), Ctx);
314   Fixups.push_back(MCFixup::create(0, FixupExpression,
315                                    MCFixupKind(Mips::fixup_Mips_PC16)));
316   return 0;
317 }
318 
319 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
320 /// target operand. If the machine operand requires relocation,
321 /// record the relocation and return zero.
322 unsigned MipsMCCodeEmitter::
323 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
324                           SmallVectorImpl<MCFixup> &Fixups,
325                           const MCSubtargetInfo &STI) const {
326 
327   const MCOperand &MO = MI.getOperand(OpNo);
328 
329   // If the destination is an immediate, divide by 2.
330   if (MO.isImm()) return MO.getImm() >> 1;
331 
332   assert(MO.isExpr() &&
333          "getBranchTargetOpValueMM expects only expressions or immediates");
334 
335   const MCExpr *Expr = MO.getExpr();
336   Fixups.push_back(MCFixup::create(0, Expr,
337                                    MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
338   return 0;
339 }
340 
341 /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
342 /// 10-bit branch target operand. If the machine operand requires relocation,
343 /// record the relocation and return zero.
344 unsigned MipsMCCodeEmitter::
345 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
346                              SmallVectorImpl<MCFixup> &Fixups,
347                              const MCSubtargetInfo &STI) const {
348 
349   const MCOperand &MO = MI.getOperand(OpNo);
350 
351   // If the destination is an immediate, divide by 2.
352   if (MO.isImm()) return MO.getImm() >> 1;
353 
354   assert(MO.isExpr() &&
355          "getBranchTargetOpValuePC10 expects only expressions or immediates");
356 
357   const MCExpr *Expr = MO.getExpr();
358   Fixups.push_back(MCFixup::create(0, Expr,
359                    MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
360   return 0;
361 }
362 
363 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
364 /// target operand. If the machine operand requires relocation,
365 /// record the relocation and return zero.
366 unsigned MipsMCCodeEmitter::
367 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
368                          SmallVectorImpl<MCFixup> &Fixups,
369                          const MCSubtargetInfo &STI) const {
370 
371   const MCOperand &MO = MI.getOperand(OpNo);
372 
373   // If the destination is an immediate, divide by 2.
374   if (MO.isImm()) return MO.getImm() >> 1;
375 
376   assert(MO.isExpr() &&
377          "getBranchTargetOpValueMM expects only expressions or immediates");
378 
379   const MCExpr *Expr = MO.getExpr();
380   Fixups.push_back(MCFixup::create(0, Expr,
381                    MCFixupKind(Mips::
382                                fixup_MICROMIPS_PC16_S1)));
383   return 0;
384 }
385 
386 /// getBranchTarget21OpValue - Return binary encoding of the branch
387 /// target operand. If the machine operand requires relocation,
388 /// record the relocation and return zero.
389 unsigned MipsMCCodeEmitter::
390 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
391                          SmallVectorImpl<MCFixup> &Fixups,
392                          const MCSubtargetInfo &STI) const {
393 
394   const MCOperand &MO = MI.getOperand(OpNo);
395 
396   // If the destination is an immediate, divide by 4.
397   if (MO.isImm()) return MO.getImm() >> 2;
398 
399   assert(MO.isExpr() &&
400          "getBranchTarget21OpValue expects only expressions or immediates");
401 
402   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
403       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
404   Fixups.push_back(MCFixup::create(0, FixupExpression,
405                                    MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
406   return 0;
407 }
408 
409 /// getBranchTarget21OpValueMM - Return binary encoding of the branch
410 /// target operand for microMIPS. If the machine operand requires
411 /// relocation, record the relocation and return zero.
412 unsigned MipsMCCodeEmitter::
413 getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
414                            SmallVectorImpl<MCFixup> &Fixups,
415                            const MCSubtargetInfo &STI) const {
416 
417   const MCOperand &MO = MI.getOperand(OpNo);
418 
419   // If the destination is an immediate, divide by 2.
420   if (MO.isImm()) return MO.getImm() >> 1;
421 
422   assert(MO.isExpr() &&
423     "getBranchTarget21OpValueMM expects only expressions or immediates");
424 
425   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
426       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
427   Fixups.push_back(MCFixup::create(0, FixupExpression,
428                                    MCFixupKind(Mips::fixup_MICROMIPS_PC21_S1)));
429   return 0;
430 }
431 
432 /// getBranchTarget26OpValue - Return binary encoding of the branch
433 /// target operand. If the machine operand requires relocation,
434 /// record the relocation and return zero.
435 unsigned MipsMCCodeEmitter::
436 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
437                          SmallVectorImpl<MCFixup> &Fixups,
438                          const MCSubtargetInfo &STI) const {
439 
440   const MCOperand &MO = MI.getOperand(OpNo);
441 
442   // If the destination is an immediate, divide by 4.
443   if (MO.isImm()) return MO.getImm() >> 2;
444 
445   assert(MO.isExpr() &&
446          "getBranchTarget26OpValue expects only expressions or immediates");
447 
448   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
449       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
450   Fixups.push_back(MCFixup::create(0, FixupExpression,
451                                    MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
452   return 0;
453 }
454 
455 /// getBranchTarget26OpValueMM - Return binary encoding of the branch
456 /// target operand. If the machine operand requires relocation,
457 /// record the relocation and return zero.
458 unsigned MipsMCCodeEmitter::getBranchTarget26OpValueMM(
459     const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
460     const MCSubtargetInfo &STI) const {
461 
462   const MCOperand &MO = MI.getOperand(OpNo);
463 
464   // If the destination is an immediate, divide by 2.
465   if (MO.isImm())
466     return MO.getImm() >> 1;
467 
468   assert(MO.isExpr() &&
469          "getBranchTarget26OpValueMM expects only expressions or immediates");
470 
471   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
472       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
473   Fixups.push_back(MCFixup::create(0, FixupExpression,
474                                    MCFixupKind(Mips::fixup_MICROMIPS_PC26_S1)));
475   return 0;
476 }
477 
478 /// getJumpOffset16OpValue - Return binary encoding of the jump
479 /// target operand. If the machine operand requires relocation,
480 /// record the relocation and return zero.
481 unsigned MipsMCCodeEmitter::
482 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
483                        SmallVectorImpl<MCFixup> &Fixups,
484                        const MCSubtargetInfo &STI) const {
485 
486   const MCOperand &MO = MI.getOperand(OpNo);
487 
488   if (MO.isImm()) return MO.getImm();
489 
490   assert(MO.isExpr() &&
491          "getJumpOffset16OpValue expects only expressions or an immediate");
492 
493    // TODO: Push fixup.
494    return 0;
495 }
496 
497 /// getJumpTargetOpValue - Return binary encoding of the jump
498 /// target operand. If the machine operand requires relocation,
499 /// record the relocation and return zero.
500 unsigned MipsMCCodeEmitter::
501 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
502                      SmallVectorImpl<MCFixup> &Fixups,
503                      const MCSubtargetInfo &STI) const {
504 
505   const MCOperand &MO = MI.getOperand(OpNo);
506   // If the destination is an immediate, divide by 4.
507   if (MO.isImm()) return MO.getImm()>>2;
508 
509   assert(MO.isExpr() &&
510          "getJumpTargetOpValue expects only expressions or an immediate");
511 
512   const MCExpr *Expr = MO.getExpr();
513   Fixups.push_back(MCFixup::create(0, Expr,
514                                    MCFixupKind(Mips::fixup_Mips_26)));
515   return 0;
516 }
517 
518 unsigned MipsMCCodeEmitter::
519 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
520                        SmallVectorImpl<MCFixup> &Fixups,
521                        const MCSubtargetInfo &STI) const {
522 
523   const MCOperand &MO = MI.getOperand(OpNo);
524   // If the destination is an immediate, divide by 2.
525   if (MO.isImm()) return MO.getImm() >> 1;
526 
527   assert(MO.isExpr() &&
528          "getJumpTargetOpValueMM expects only expressions or an immediate");
529 
530   const MCExpr *Expr = MO.getExpr();
531   Fixups.push_back(MCFixup::create(0, Expr,
532                                    MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
533   return 0;
534 }
535 
536 unsigned MipsMCCodeEmitter::
537 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
538                      SmallVectorImpl<MCFixup> &Fixups,
539                      const MCSubtargetInfo &STI) const {
540 
541   const MCOperand &MO = MI.getOperand(OpNo);
542   if (MO.isImm()) {
543     // The immediate is encoded as 'immediate << 2'.
544     unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
545     assert((Res & 3) == 0);
546     return Res >> 2;
547   }
548 
549   assert(MO.isExpr() &&
550          "getUImm5Lsl2Encoding expects only expressions or an immediate");
551 
552   return 0;
553 }
554 
555 unsigned MipsMCCodeEmitter::
556 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
557                   SmallVectorImpl<MCFixup> &Fixups,
558                   const MCSubtargetInfo &STI) const {
559 
560   const MCOperand &MO = MI.getOperand(OpNo);
561   if (MO.isImm()) {
562     int Value = MO.getImm();
563     return Value >> 2;
564   }
565 
566   return 0;
567 }
568 
569 unsigned MipsMCCodeEmitter::
570 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
571                      SmallVectorImpl<MCFixup> &Fixups,
572                      const MCSubtargetInfo &STI) const {
573 
574   const MCOperand &MO = MI.getOperand(OpNo);
575   if (MO.isImm()) {
576     unsigned Value = MO.getImm();
577     return Value >> 2;
578   }
579 
580   return 0;
581 }
582 
583 unsigned MipsMCCodeEmitter::
584 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
585                      SmallVectorImpl<MCFixup> &Fixups,
586                      const MCSubtargetInfo &STI) const {
587 
588   const MCOperand &MO = MI.getOperand(OpNo);
589   if (MO.isImm()) {
590     unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
591     return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
592   }
593 
594   return 0;
595 }
596 
597 unsigned MipsMCCodeEmitter::
598 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
599                const MCSubtargetInfo &STI) const {
600   int64_t Res;
601 
602   if (Expr->evaluateAsAbsolute(Res))
603     return Res;
604 
605   MCExpr::ExprKind Kind = Expr->getKind();
606   if (Kind == MCExpr::Constant) {
607     return cast<MCConstantExpr>(Expr)->getValue();
608   }
609 
610   if (Kind == MCExpr::Binary) {
611     unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
612     Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
613     return Res;
614   }
615 
616   if (Kind == MCExpr::Target) {
617     const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
618 
619     Mips::Fixups FixupKind = Mips::Fixups(0);
620     switch (MipsExpr->getKind()) {
621     case MipsMCExpr::MEK_NEG:
622     case MipsMCExpr::MEK_None:
623     case MipsMCExpr::MEK_Special:
624       llvm_unreachable("Unhandled fixup kind!");
625       break;
626     case MipsMCExpr::MEK_CALL_HI16:
627       FixupKind = Mips::fixup_Mips_CALL_HI16;
628       break;
629     case MipsMCExpr::MEK_CALL_LO16:
630       FixupKind = Mips::fixup_Mips_CALL_LO16;
631       break;
632     case MipsMCExpr::MEK_DTPREL_HI:
633       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
634                                    : Mips::fixup_Mips_DTPREL_HI;
635       break;
636     case MipsMCExpr::MEK_DTPREL_LO:
637       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
638                                    : Mips::fixup_Mips_DTPREL_LO;
639       break;
640     case MipsMCExpr::MEK_GOTTPREL:
641       FixupKind = Mips::fixup_Mips_GOTTPREL;
642       break;
643     case MipsMCExpr::MEK_GOT:
644       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
645                                    : Mips::fixup_Mips_GOT;
646       break;
647     case MipsMCExpr::MEK_GOT_CALL:
648       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
649                                    : Mips::fixup_Mips_CALL16;
650       break;
651     case MipsMCExpr::MEK_GOT_DISP:
652       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
653                                    : Mips::fixup_Mips_GOT_DISP;
654       break;
655     case MipsMCExpr::MEK_GOT_HI16:
656       FixupKind = Mips::fixup_Mips_GOT_HI16;
657       break;
658     case MipsMCExpr::MEK_GOT_LO16:
659       FixupKind = Mips::fixup_Mips_GOT_LO16;
660       break;
661     case MipsMCExpr::MEK_GOT_PAGE:
662       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
663                                    : Mips::fixup_Mips_GOT_PAGE;
664       break;
665     case MipsMCExpr::MEK_GOT_OFST:
666       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
667                                    : Mips::fixup_Mips_GOT_OFST;
668       break;
669     case MipsMCExpr::MEK_GPREL:
670       FixupKind = Mips::fixup_Mips_GPREL16;
671       break;
672     case MipsMCExpr::MEK_LO: {
673       // Check for %lo(%neg(%gp_rel(X)))
674       if (MipsExpr->isGpOff()) {
675         FixupKind = Mips::fixup_Mips_GPOFF_LO;
676         break;
677       }
678       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
679                                    : Mips::fixup_Mips_LO16;
680       break;
681     }
682     case MipsMCExpr::MEK_HIGHEST:
683       FixupKind = Mips::fixup_Mips_HIGHEST;
684       break;
685     case MipsMCExpr::MEK_HIGHER:
686       FixupKind = Mips::fixup_Mips_HIGHER;
687       break;
688     case MipsMCExpr::MEK_HI:
689       // Check for %hi(%neg(%gp_rel(X)))
690       if (MipsExpr->isGpOff()) {
691         FixupKind = Mips::fixup_Mips_GPOFF_HI;
692         break;
693       }
694       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
695                                    : Mips::fixup_Mips_HI16;
696       break;
697     case MipsMCExpr::MEK_PCREL_HI16:
698       FixupKind = Mips::fixup_MIPS_PCHI16;
699       break;
700     case MipsMCExpr::MEK_PCREL_LO16:
701       FixupKind = Mips::fixup_MIPS_PCLO16;
702       break;
703     case MipsMCExpr::MEK_TLSGD:
704       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
705                                    : Mips::fixup_Mips_TLSGD;
706       break;
707     case MipsMCExpr::MEK_TLSLDM:
708       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
709                                    : Mips::fixup_Mips_TLSLDM;
710       break;
711     case MipsMCExpr::MEK_TPREL_HI:
712       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
713                                    : Mips::fixup_Mips_TPREL_HI;
714       break;
715     case MipsMCExpr::MEK_TPREL_LO:
716       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
717                                    : Mips::fixup_Mips_TPREL_LO;
718       break;
719     }
720     Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
721     return 0;
722   }
723 
724   if (Kind == MCExpr::SymbolRef) {
725     Mips::Fixups FixupKind = Mips::Fixups(0);
726 
727     switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
728     default: llvm_unreachable("Unknown fixup kind!");
729       break;
730     case MCSymbolRefExpr::VK_None:
731       FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
732       break;
733     } // switch
734 
735     Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
736     return 0;
737   }
738   return 0;
739 }
740 
741 /// getMachineOpValue - Return binary encoding of operand. If the machine
742 /// operand requires relocation, record the relocation and return zero.
743 unsigned MipsMCCodeEmitter::
744 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
745                   SmallVectorImpl<MCFixup> &Fixups,
746                   const MCSubtargetInfo &STI) const {
747   if (MO.isReg()) {
748     unsigned Reg = MO.getReg();
749     unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
750     return RegNo;
751   } else if (MO.isImm()) {
752     return static_cast<unsigned>(MO.getImm());
753   } else if (MO.isFPImm()) {
754     return static_cast<unsigned>(APFloat(MO.getFPImm())
755         .bitcastToAPInt().getHiBits(32).getLimitedValue());
756   }
757   // MO must be an Expr.
758   assert(MO.isExpr());
759   return getExprOpValue(MO.getExpr(),Fixups, STI);
760 }
761 
762 /// Return binary encoding of memory related operand.
763 /// If the offset operand requires relocation, record the relocation.
764 template <unsigned ShiftAmount>
765 unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
766                                            SmallVectorImpl<MCFixup> &Fixups,
767                                            const MCSubtargetInfo &STI) const {
768   // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
769   assert(MI.getOperand(OpNo).isReg());
770   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
771   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
772 
773   // Apply the scale factor if there is one.
774   OffBits >>= ShiftAmount;
775 
776   return (OffBits & 0xFFFF) | RegBits;
777 }
778 
779 unsigned MipsMCCodeEmitter::
780 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
781                      SmallVectorImpl<MCFixup> &Fixups,
782                      const MCSubtargetInfo &STI) const {
783   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
784   assert(MI.getOperand(OpNo).isReg());
785   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
786                                        Fixups, STI) << 4;
787   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
788                                        Fixups, STI);
789 
790   return (OffBits & 0xF) | RegBits;
791 }
792 
793 unsigned MipsMCCodeEmitter::
794 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
795                          SmallVectorImpl<MCFixup> &Fixups,
796                          const MCSubtargetInfo &STI) const {
797   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
798   assert(MI.getOperand(OpNo).isReg());
799   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
800                                        Fixups, STI) << 4;
801   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
802                                        Fixups, STI) >> 1;
803 
804   return (OffBits & 0xF) | RegBits;
805 }
806 
807 unsigned MipsMCCodeEmitter::
808 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
809                          SmallVectorImpl<MCFixup> &Fixups,
810                          const MCSubtargetInfo &STI) const {
811   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
812   assert(MI.getOperand(OpNo).isReg());
813   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
814                                        Fixups, STI) << 4;
815   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
816                                        Fixups, STI) >> 2;
817 
818   return (OffBits & 0xF) | RegBits;
819 }
820 
821 unsigned MipsMCCodeEmitter::
822 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
823                            SmallVectorImpl<MCFixup> &Fixups,
824                            const MCSubtargetInfo &STI) const {
825   // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
826   assert(MI.getOperand(OpNo).isReg() &&
827          (MI.getOperand(OpNo).getReg() == Mips::SP ||
828          MI.getOperand(OpNo).getReg() == Mips::SP_64) &&
829          "Unexpected base register!");
830   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
831                                        Fixups, STI) >> 2;
832 
833   return OffBits & 0x1F;
834 }
835 
836 unsigned MipsMCCodeEmitter::
837 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
838                            SmallVectorImpl<MCFixup> &Fixups,
839                            const MCSubtargetInfo &STI) const {
840   // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
841   assert(MI.getOperand(OpNo).isReg() &&
842          MI.getOperand(OpNo).getReg() == Mips::GP &&
843          "Unexpected base register!");
844 
845   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
846                                        Fixups, STI) >> 2;
847 
848   return OffBits & 0x7F;
849 }
850 
851 unsigned MipsMCCodeEmitter::
852 getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
853                      SmallVectorImpl<MCFixup> &Fixups,
854                      const MCSubtargetInfo &STI) const {
855   // Base register is encoded in bits 20-16, offset is encoded in bits 8-0.
856   assert(MI.getOperand(OpNo).isReg());
857   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
858                                        STI) << 16;
859   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
860 
861   return (OffBits & 0x1FF) | RegBits;
862 }
863 
864 unsigned MipsMCCodeEmitter::
865 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
866                       SmallVectorImpl<MCFixup> &Fixups,
867                       const MCSubtargetInfo &STI) const {
868   // opNum can be invalid if instruction had reglist as operand.
869   // MemOperand is always last operand of instruction (base + offset).
870   switch (MI.getOpcode()) {
871   default:
872     break;
873   case Mips::SWM32_MM:
874   case Mips::LWM32_MM:
875     OpNo = MI.getNumOperands() - 2;
876     break;
877   }
878 
879   // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
880   assert(MI.getOperand(OpNo).isReg());
881   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
882   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
883 
884   return (OffBits & 0x0FFF) | RegBits;
885 }
886 
887 unsigned MipsMCCodeEmitter::
888 getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
889                       SmallVectorImpl<MCFixup> &Fixups,
890                       const MCSubtargetInfo &STI) const {
891   // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
892   assert(MI.getOperand(OpNo).isReg());
893   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
894                                        STI) << 16;
895   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
896 
897   return (OffBits & 0xFFFF) | RegBits;
898 }
899 
900 unsigned MipsMCCodeEmitter::
901 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
902                        SmallVectorImpl<MCFixup> &Fixups,
903                        const MCSubtargetInfo &STI) const {
904   // opNum can be invalid if instruction had reglist as operand
905   // MemOperand is always last operand of instruction (base + offset)
906   switch (MI.getOpcode()) {
907   default:
908     break;
909   case Mips::SWM16_MM:
910   case Mips::SWM16_MMR6:
911   case Mips::LWM16_MM:
912   case Mips::LWM16_MMR6:
913     OpNo = MI.getNumOperands() - 2;
914     break;
915   }
916 
917   // Offset is encoded in bits 4-0.
918   assert(MI.getOperand(OpNo).isReg());
919   // Base register is always SP - thus it is not encoded.
920   assert(MI.getOperand(OpNo+1).isImm());
921   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
922 
923   return ((OffBits >> 2) & 0x0F);
924 }
925 
926 // FIXME: should be called getMSBEncoding
927 //
928 unsigned
929 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
930                                       SmallVectorImpl<MCFixup> &Fixups,
931                                       const MCSubtargetInfo &STI) const {
932   assert(MI.getOperand(OpNo-1).isImm());
933   assert(MI.getOperand(OpNo).isImm());
934   unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
935   unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
936 
937   return Position + Size - 1;
938 }
939 
940 template <unsigned Bits, int Offset>
941 unsigned
942 MipsMCCodeEmitter::getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo,
943                                              SmallVectorImpl<MCFixup> &Fixups,
944                                              const MCSubtargetInfo &STI) const {
945   assert(MI.getOperand(OpNo).isImm());
946   unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
947   Value -= Offset;
948   return Value;
949 }
950 
951 unsigned
952 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
953                                          SmallVectorImpl<MCFixup> &Fixups,
954                                          const MCSubtargetInfo &STI) const {
955   const MCOperand &MO = MI.getOperand(OpNo);
956   if (MO.isImm()) {
957     // The immediate is encoded as 'immediate << 2'.
958     unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
959     assert((Res & 3) == 0);
960     return Res >> 2;
961   }
962 
963   assert(MO.isExpr() &&
964          "getSimm19Lsl2Encoding expects only expressions or an immediate");
965 
966   const MCExpr *Expr = MO.getExpr();
967   Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC19_S2
968                                             : Mips::fixup_MIPS_PC19_S2;
969   Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
970   return 0;
971 }
972 
973 unsigned
974 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
975                                          SmallVectorImpl<MCFixup> &Fixups,
976                                          const MCSubtargetInfo &STI) const {
977   const MCOperand &MO = MI.getOperand(OpNo);
978   if (MO.isImm()) {
979     // The immediate is encoded as 'immediate << 3'.
980     unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
981     assert((Res & 7) == 0);
982     return Res >> 3;
983   }
984 
985   assert(MO.isExpr() &&
986          "getSimm18Lsl2Encoding expects only expressions or an immediate");
987 
988   const MCExpr *Expr = MO.getExpr();
989   Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3
990                                             : Mips::fixup_MIPS_PC18_S3;
991   Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
992   return 0;
993 }
994 
995 unsigned
996 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
997                                         SmallVectorImpl<MCFixup> &Fixups,
998                                         const MCSubtargetInfo &STI) const {
999   assert(MI.getOperand(OpNo).isImm());
1000   const MCOperand &MO = MI.getOperand(OpNo);
1001   return MO.getImm() % 8;
1002 }
1003 
1004 unsigned
1005 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
1006                                     SmallVectorImpl<MCFixup> &Fixups,
1007                                     const MCSubtargetInfo &STI) const {
1008   assert(MI.getOperand(OpNo).isImm());
1009   const MCOperand &MO = MI.getOperand(OpNo);
1010   unsigned Value = MO.getImm();
1011   switch (Value) {
1012     case 128:   return 0x0;
1013     case 1:     return 0x1;
1014     case 2:     return 0x2;
1015     case 3:     return 0x3;
1016     case 4:     return 0x4;
1017     case 7:     return 0x5;
1018     case 8:     return 0x6;
1019     case 15:    return 0x7;
1020     case 16:    return 0x8;
1021     case 31:    return 0x9;
1022     case 32:    return 0xa;
1023     case 63:    return 0xb;
1024     case 64:    return 0xc;
1025     case 255:   return 0xd;
1026     case 32768: return 0xe;
1027     case 65535: return 0xf;
1028   }
1029   llvm_unreachable("Unexpected value");
1030 }
1031 
1032 unsigned
1033 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
1034                                           SmallVectorImpl<MCFixup> &Fixups,
1035                                           const MCSubtargetInfo &STI) const {
1036   unsigned res = 0;
1037 
1038   // Register list operand is always first operand of instruction and it is
1039   // placed before memory operand (register + imm).
1040 
1041   for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
1042     unsigned Reg = MI.getOperand(I).getReg();
1043     unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
1044     if (RegNo != 31)
1045       res++;
1046     else
1047       res |= 0x10;
1048   }
1049   return res;
1050 }
1051 
1052 unsigned
1053 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
1054                                             SmallVectorImpl<MCFixup> &Fixups,
1055                                             const MCSubtargetInfo &STI) const {
1056   return (MI.getNumOperands() - 4);
1057 }
1058 
1059 unsigned
1060 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
1061                                           SmallVectorImpl<MCFixup> &Fixups,
1062                                           const MCSubtargetInfo &STI) const {
1063   return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
1064 }
1065 
1066 unsigned
1067 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
1068                                           SmallVectorImpl<MCFixup> &Fixups,
1069                                           const MCSubtargetInfo &STI) const {
1070   unsigned res = 0;
1071 
1072   if (MI.getOperand(0).getReg() == Mips::A1 &&
1073       MI.getOperand(1).getReg() == Mips::A2)
1074     res = 0;
1075   else if (MI.getOperand(0).getReg() == Mips::A1 &&
1076            MI.getOperand(1).getReg() == Mips::A3)
1077     res = 1;
1078   else if (MI.getOperand(0).getReg() == Mips::A2 &&
1079            MI.getOperand(1).getReg() == Mips::A3)
1080     res = 2;
1081   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1082            MI.getOperand(1).getReg() == Mips::S5)
1083     res = 3;
1084   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1085            MI.getOperand(1).getReg() == Mips::S6)
1086     res = 4;
1087   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1088            MI.getOperand(1).getReg() == Mips::A1)
1089     res = 5;
1090   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1091            MI.getOperand(1).getReg() == Mips::A2)
1092     res = 6;
1093   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1094            MI.getOperand(1).getReg() == Mips::A3)
1095     res = 7;
1096 
1097   return res;
1098 }
1099 
1100 unsigned
1101 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
1102                                          SmallVectorImpl<MCFixup> &Fixups,
1103                                          const MCSubtargetInfo &STI) const {
1104   const MCOperand &MO = MI.getOperand(OpNo);
1105   assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
1106   // The immediate is encoded as 'immediate >> 2'.
1107   unsigned Res = static_cast<unsigned>(MO.getImm());
1108   assert((Res & 3) == 0);
1109   return Res >> 2;
1110 }
1111 
1112 #include "MipsGenMCCodeEmitter.inc"
1113