1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MipsMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14 
15 #include "MipsMCCodeEmitter.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCExpr.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCFixup.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
28 
29 #define DEBUG_TYPE "mccodeemitter"
30 
31 #define GET_INSTRMAP_INFO
32 #include "MipsGenInstrInfo.inc"
33 #undef GET_INSTRMAP_INFO
34 
35 namespace llvm {
36 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37                                          const MCRegisterInfo &MRI,
38                                          const MCSubtargetInfo &STI,
39                                          MCContext &Ctx) {
40   return new MipsMCCodeEmitter(MCII, Ctx, false);
41 }
42 
43 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
44                                          const MCRegisterInfo &MRI,
45                                          const MCSubtargetInfo &STI,
46                                          MCContext &Ctx) {
47   return new MipsMCCodeEmitter(MCII, Ctx, true);
48 }
49 } // End of namespace llvm.
50 
51 // If the D<shift> instruction has a shift amount that is greater
52 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
53 static void LowerLargeShift(MCInst& Inst) {
54 
55   assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
56   assert(Inst.getOperand(2).isImm());
57 
58   int64_t Shift = Inst.getOperand(2).getImm();
59   if (Shift <= 31)
60     return; // Do nothing
61   Shift -= 32;
62 
63   // saminus32
64   Inst.getOperand(2).setImm(Shift);
65 
66   switch (Inst.getOpcode()) {
67   default:
68     // Calling function is not synchronized
69     llvm_unreachable("Unexpected shift instruction");
70   case Mips::DSLL:
71     Inst.setOpcode(Mips::DSLL32);
72     return;
73   case Mips::DSRL:
74     Inst.setOpcode(Mips::DSRL32);
75     return;
76   case Mips::DSRA:
77     Inst.setOpcode(Mips::DSRA32);
78     return;
79   case Mips::DROTR:
80     Inst.setOpcode(Mips::DROTR32);
81     return;
82   }
83 }
84 
85 // Pick a DEXT or DINS instruction variant based on the pos and size operands
86 static void LowerDextDins(MCInst& InstIn) {
87   int Opcode = InstIn.getOpcode();
88 
89   if (Opcode == Mips::DEXT)
90     assert(InstIn.getNumOperands() == 4 &&
91            "Invalid no. of machine operands for DEXT!");
92   else // Only DEXT and DINS are possible
93     assert(InstIn.getNumOperands() == 5 &&
94            "Invalid no. of machine operands for DINS!");
95 
96   assert(InstIn.getOperand(2).isImm());
97   int64_t pos = InstIn.getOperand(2).getImm();
98   assert(InstIn.getOperand(3).isImm());
99   int64_t size = InstIn.getOperand(3).getImm();
100 
101   if (size <= 32) {
102     if (pos < 32)  // DEXT/DINS, do nothing
103       return;
104     // DEXTU/DINSU
105     InstIn.getOperand(2).setImm(pos - 32);
106     InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
107     return;
108   }
109   // DEXTM/DINSM
110   assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
111   InstIn.getOperand(3).setImm(size - 32);
112   InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
113   return;
114 }
115 
116 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
117   return STI.getFeatureBits() & Mips::FeatureMicroMips;
118 }
119 
120 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
121   OS << (char)C;
122 }
123 
124 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
125                                         const MCSubtargetInfo &STI,
126                                         raw_ostream &OS) const {
127   // Output the instruction encoding in little endian byte order.
128   // Little-endian byte ordering:
129   //   mips32r2:   4 | 3 | 2 | 1
130   //   microMIPS:  2 | 1 | 4 | 3
131   if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
132     EmitInstruction(Val >> 16, 2, STI, OS);
133     EmitInstruction(Val, 2, STI, OS);
134   } else {
135     for (unsigned i = 0; i < Size; ++i) {
136       unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
137       EmitByte((Val >> Shift) & 0xff, OS);
138     }
139   }
140 }
141 
142 /// EncodeInstruction - Emit the instruction.
143 /// Size the instruction with Desc.getSize().
144 void MipsMCCodeEmitter::
145 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
146                   SmallVectorImpl<MCFixup> &Fixups,
147                   const MCSubtargetInfo &STI) const
148 {
149 
150   // Non-pseudo instructions that get changed for direct object
151   // only based on operand values.
152   // If this list of instructions get much longer we will move
153   // the check to a function call. Until then, this is more efficient.
154   MCInst TmpInst = MI;
155   switch (MI.getOpcode()) {
156   // If shift amount is >= 32 it the inst needs to be lowered further
157   case Mips::DSLL:
158   case Mips::DSRL:
159   case Mips::DSRA:
160   case Mips::DROTR:
161     LowerLargeShift(TmpInst);
162     break;
163     // Double extract instruction is chosen by pos and size operands
164   case Mips::DEXT:
165   case Mips::DINS:
166     LowerDextDins(TmpInst);
167   }
168 
169   unsigned long N = Fixups.size();
170   uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
171 
172   // Check for unimplemented opcodes.
173   // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
174   // so we have to special check for them.
175   unsigned Opcode = TmpInst.getOpcode();
176   if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
177       (Opcode != Mips::SLL_MM) && !Binary)
178     llvm_unreachable("unimplemented opcode in EncodeInstruction()");
179 
180   if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
181     int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
182     if (NewOpcode != -1) {
183       if (Fixups.size() > N)
184         Fixups.pop_back();
185       Opcode = NewOpcode;
186       TmpInst.setOpcode (NewOpcode);
187       Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
188     }
189   }
190 
191   const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
192 
193   // Get byte count of instruction
194   unsigned Size = Desc.getSize();
195   if (!Size)
196     llvm_unreachable("Desc.getSize() returns 0");
197 
198   EmitInstruction(Binary, Size, STI, OS);
199 }
200 
201 /// getBranchTargetOpValue - Return binary encoding of the branch
202 /// target operand. If the machine operand requires relocation,
203 /// record the relocation and return zero.
204 unsigned MipsMCCodeEmitter::
205 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
206                        SmallVectorImpl<MCFixup> &Fixups,
207                        const MCSubtargetInfo &STI) const {
208 
209   const MCOperand &MO = MI.getOperand(OpNo);
210 
211   // If the destination is an immediate, divide by 4.
212   if (MO.isImm()) return MO.getImm() >> 2;
213 
214   assert(MO.isExpr() &&
215          "getBranchTargetOpValue expects only expressions or immediates");
216 
217   const MCExpr *Expr = MO.getExpr();
218   Fixups.push_back(MCFixup::Create(0, Expr,
219                                    MCFixupKind(Mips::fixup_Mips_PC16)));
220   return 0;
221 }
222 
223 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
224 /// target operand. If the machine operand requires relocation,
225 /// record the relocation and return zero.
226 unsigned MipsMCCodeEmitter::
227 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
228                           SmallVectorImpl<MCFixup> &Fixups,
229                           const MCSubtargetInfo &STI) const {
230 
231   const MCOperand &MO = MI.getOperand(OpNo);
232 
233   // If the destination is an immediate, divide by 2.
234   if (MO.isImm()) return MO.getImm() >> 1;
235 
236   assert(MO.isExpr() &&
237          "getBranchTargetOpValueMM expects only expressions or immediates");
238 
239   const MCExpr *Expr = MO.getExpr();
240   Fixups.push_back(MCFixup::Create(0, Expr,
241                                    MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
242   return 0;
243 }
244 
245 /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
246 /// 10-bit branch target operand. If the machine operand requires relocation,
247 /// record the relocation and return zero.
248 unsigned MipsMCCodeEmitter::
249 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
250                              SmallVectorImpl<MCFixup> &Fixups,
251                              const MCSubtargetInfo &STI) const {
252 
253   const MCOperand &MO = MI.getOperand(OpNo);
254 
255   // If the destination is an immediate, divide by 2.
256   if (MO.isImm()) return MO.getImm() >> 1;
257 
258   assert(MO.isExpr() &&
259          "getBranchTargetOpValuePC10 expects only expressions or immediates");
260 
261   const MCExpr *Expr = MO.getExpr();
262   Fixups.push_back(MCFixup::Create(0, Expr,
263                    MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
264   return 0;
265 }
266 
267 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
268 /// target operand. If the machine operand requires relocation,
269 /// record the relocation and return zero.
270 unsigned MipsMCCodeEmitter::
271 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
272                          SmallVectorImpl<MCFixup> &Fixups,
273                          const MCSubtargetInfo &STI) const {
274 
275   const MCOperand &MO = MI.getOperand(OpNo);
276 
277   // If the destination is an immediate, divide by 2.
278   if (MO.isImm()) return MO.getImm() >> 1;
279 
280   assert(MO.isExpr() &&
281          "getBranchTargetOpValueMM expects only expressions or immediates");
282 
283   const MCExpr *Expr = MO.getExpr();
284   Fixups.push_back(MCFixup::Create(0, Expr,
285                    MCFixupKind(Mips::
286                                fixup_MICROMIPS_PC16_S1)));
287   return 0;
288 }
289 
290 /// getBranchTarget21OpValue - Return binary encoding of the branch
291 /// target operand. If the machine operand requires relocation,
292 /// record the relocation and return zero.
293 unsigned MipsMCCodeEmitter::
294 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
295                          SmallVectorImpl<MCFixup> &Fixups,
296                          const MCSubtargetInfo &STI) const {
297 
298   const MCOperand &MO = MI.getOperand(OpNo);
299 
300   // If the destination is an immediate, divide by 4.
301   if (MO.isImm()) return MO.getImm() >> 2;
302 
303   assert(MO.isExpr() &&
304          "getBranchTarget21OpValue expects only expressions or immediates");
305 
306   const MCExpr *Expr = MO.getExpr();
307   Fixups.push_back(MCFixup::Create(0, Expr,
308                                    MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
309   return 0;
310 }
311 
312 /// getBranchTarget26OpValue - Return binary encoding of the branch
313 /// target operand. If the machine operand requires relocation,
314 /// record the relocation and return zero.
315 unsigned MipsMCCodeEmitter::
316 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
317                          SmallVectorImpl<MCFixup> &Fixups,
318                          const MCSubtargetInfo &STI) const {
319 
320   const MCOperand &MO = MI.getOperand(OpNo);
321 
322   // If the destination is an immediate, divide by 4.
323   if (MO.isImm()) return MO.getImm() >> 2;
324 
325   assert(MO.isExpr() &&
326          "getBranchTarget26OpValue expects only expressions or immediates");
327 
328   const MCExpr *Expr = MO.getExpr();
329   Fixups.push_back(MCFixup::Create(0, Expr,
330                                    MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
331   return 0;
332 }
333 
334 /// getJumpOffset16OpValue - Return binary encoding of the jump
335 /// target operand. If the machine operand requires relocation,
336 /// record the relocation and return zero.
337 unsigned MipsMCCodeEmitter::
338 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
339                        SmallVectorImpl<MCFixup> &Fixups,
340                        const MCSubtargetInfo &STI) const {
341 
342   const MCOperand &MO = MI.getOperand(OpNo);
343 
344   if (MO.isImm()) return MO.getImm();
345 
346   assert(MO.isExpr() &&
347          "getJumpOffset16OpValue expects only expressions or an immediate");
348 
349    // TODO: Push fixup.
350    return 0;
351 }
352 
353 /// getJumpTargetOpValue - Return binary encoding of the jump
354 /// target operand. If the machine operand requires relocation,
355 /// record the relocation and return zero.
356 unsigned MipsMCCodeEmitter::
357 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
358                      SmallVectorImpl<MCFixup> &Fixups,
359                      const MCSubtargetInfo &STI) const {
360 
361   const MCOperand &MO = MI.getOperand(OpNo);
362   // If the destination is an immediate, divide by 4.
363   if (MO.isImm()) return MO.getImm()>>2;
364 
365   assert(MO.isExpr() &&
366          "getJumpTargetOpValue expects only expressions or an immediate");
367 
368   const MCExpr *Expr = MO.getExpr();
369   Fixups.push_back(MCFixup::Create(0, Expr,
370                                    MCFixupKind(Mips::fixup_Mips_26)));
371   return 0;
372 }
373 
374 unsigned MipsMCCodeEmitter::
375 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
376                        SmallVectorImpl<MCFixup> &Fixups,
377                        const MCSubtargetInfo &STI) const {
378 
379   const MCOperand &MO = MI.getOperand(OpNo);
380   // If the destination is an immediate, divide by 2.
381   if (MO.isImm()) return MO.getImm() >> 1;
382 
383   assert(MO.isExpr() &&
384          "getJumpTargetOpValueMM expects only expressions or an immediate");
385 
386   const MCExpr *Expr = MO.getExpr();
387   Fixups.push_back(MCFixup::Create(0, Expr,
388                                    MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
389   return 0;
390 }
391 
392 unsigned MipsMCCodeEmitter::
393 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
394                      SmallVectorImpl<MCFixup> &Fixups,
395                      const MCSubtargetInfo &STI) const {
396 
397   const MCOperand &MO = MI.getOperand(OpNo);
398   if (MO.isImm()) {
399     // The immediate is encoded as 'immediate << 2'.
400     unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
401     assert((Res & 3) == 0);
402     return Res >> 2;
403   }
404 
405   assert(MO.isExpr() &&
406          "getUImm5Lsl2Encoding expects only expressions or an immediate");
407 
408   return 0;
409 }
410 
411 unsigned MipsMCCodeEmitter::
412 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
413                   SmallVectorImpl<MCFixup> &Fixups,
414                   const MCSubtargetInfo &STI) const {
415 
416   const MCOperand &MO = MI.getOperand(OpNo);
417   if (MO.isImm()) {
418     int Value = MO.getImm();
419     return Value >> 2;
420   }
421 
422   return 0;
423 }
424 
425 unsigned MipsMCCodeEmitter::
426 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
427                      SmallVectorImpl<MCFixup> &Fixups,
428                      const MCSubtargetInfo &STI) const {
429 
430   const MCOperand &MO = MI.getOperand(OpNo);
431   if (MO.isImm()) {
432     unsigned Value = MO.getImm();
433     return Value >> 2;
434   }
435 
436   return 0;
437 }
438 
439 unsigned MipsMCCodeEmitter::
440 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
441                      SmallVectorImpl<MCFixup> &Fixups,
442                      const MCSubtargetInfo &STI) const {
443 
444   const MCOperand &MO = MI.getOperand(OpNo);
445   if (MO.isImm()) {
446     unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
447     return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
448   }
449 
450   return 0;
451 }
452 
453 unsigned MipsMCCodeEmitter::
454 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
455                const MCSubtargetInfo &STI) const {
456   int64_t Res;
457 
458   if (Expr->EvaluateAsAbsolute(Res))
459     return Res;
460 
461   MCExpr::ExprKind Kind = Expr->getKind();
462   if (Kind == MCExpr::Constant) {
463     return cast<MCConstantExpr>(Expr)->getValue();
464   }
465 
466   if (Kind == MCExpr::Binary) {
467     unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
468     Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
469     return Res;
470   }
471 
472   if (Kind == MCExpr::Target) {
473     const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
474 
475     Mips::Fixups FixupKind = Mips::Fixups(0);
476     switch (MipsExpr->getKind()) {
477     default: llvm_unreachable("Unsupported fixup kind for target expression!");
478     case MipsMCExpr::VK_Mips_HIGHEST:
479       FixupKind = Mips::fixup_Mips_HIGHEST;
480       break;
481     case MipsMCExpr::VK_Mips_HIGHER:
482       FixupKind = Mips::fixup_Mips_HIGHER;
483       break;
484     case MipsMCExpr::VK_Mips_HI:
485       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
486                                    : Mips::fixup_Mips_HI16;
487       break;
488     case MipsMCExpr::VK_Mips_LO:
489       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
490                                    : Mips::fixup_Mips_LO16;
491       break;
492     }
493     Fixups.push_back(MCFixup::Create(0, MipsExpr, MCFixupKind(FixupKind)));
494     return 0;
495   }
496 
497   if (Kind == MCExpr::SymbolRef) {
498     Mips::Fixups FixupKind = Mips::Fixups(0);
499 
500     switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
501     default: llvm_unreachable("Unknown fixup kind!");
502       break;
503     case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
504       FixupKind = Mips::fixup_Mips_GPOFF_HI;
505       break;
506     case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
507       FixupKind = Mips::fixup_Mips_GPOFF_LO;
508       break;
509     case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
510       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
511                               : Mips::fixup_Mips_GOT_PAGE;
512       break;
513     case MCSymbolRefExpr::VK_Mips_GOT_OFST :
514       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
515                               : Mips::fixup_Mips_GOT_OFST;
516       break;
517     case MCSymbolRefExpr::VK_Mips_GOT_DISP :
518       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
519                               : Mips::fixup_Mips_GOT_DISP;
520       break;
521     case MCSymbolRefExpr::VK_Mips_GPREL:
522       FixupKind = Mips::fixup_Mips_GPREL16;
523       break;
524     case MCSymbolRefExpr::VK_Mips_GOT_CALL:
525       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
526                               : Mips::fixup_Mips_CALL16;
527       break;
528     case MCSymbolRefExpr::VK_Mips_GOT16:
529       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
530                               : Mips::fixup_Mips_GOT_Global;
531       break;
532     case MCSymbolRefExpr::VK_Mips_GOT:
533       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
534                               : Mips::fixup_Mips_GOT_Local;
535       break;
536     case MCSymbolRefExpr::VK_Mips_ABS_HI:
537       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
538                               : Mips::fixup_Mips_HI16;
539       break;
540     case MCSymbolRefExpr::VK_Mips_ABS_LO:
541       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
542                               : Mips::fixup_Mips_LO16;
543       break;
544     case MCSymbolRefExpr::VK_Mips_TLSGD:
545       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
546                               : Mips::fixup_Mips_TLSGD;
547       break;
548     case MCSymbolRefExpr::VK_Mips_TLSLDM:
549       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
550                               : Mips::fixup_Mips_TLSLDM;
551       break;
552     case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
553       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
554                               : Mips::fixup_Mips_DTPREL_HI;
555       break;
556     case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
557       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
558                               : Mips::fixup_Mips_DTPREL_LO;
559       break;
560     case MCSymbolRefExpr::VK_Mips_GOTTPREL:
561       FixupKind = Mips::fixup_Mips_GOTTPREL;
562       break;
563     case MCSymbolRefExpr::VK_Mips_TPREL_HI:
564       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
565                               : Mips::fixup_Mips_TPREL_HI;
566       break;
567     case MCSymbolRefExpr::VK_Mips_TPREL_LO:
568       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
569                               : Mips::fixup_Mips_TPREL_LO;
570       break;
571     case MCSymbolRefExpr::VK_Mips_HIGHER:
572       FixupKind = Mips::fixup_Mips_HIGHER;
573       break;
574     case MCSymbolRefExpr::VK_Mips_HIGHEST:
575       FixupKind = Mips::fixup_Mips_HIGHEST;
576       break;
577     case MCSymbolRefExpr::VK_Mips_GOT_HI16:
578       FixupKind = Mips::fixup_Mips_GOT_HI16;
579       break;
580     case MCSymbolRefExpr::VK_Mips_GOT_LO16:
581       FixupKind = Mips::fixup_Mips_GOT_LO16;
582       break;
583     case MCSymbolRefExpr::VK_Mips_CALL_HI16:
584       FixupKind = Mips::fixup_Mips_CALL_HI16;
585       break;
586     case MCSymbolRefExpr::VK_Mips_CALL_LO16:
587       FixupKind = Mips::fixup_Mips_CALL_LO16;
588       break;
589     case MCSymbolRefExpr::VK_Mips_PCREL_HI16:
590       FixupKind = Mips::fixup_MIPS_PCHI16;
591       break;
592     case MCSymbolRefExpr::VK_Mips_PCREL_LO16:
593       FixupKind = Mips::fixup_MIPS_PCLO16;
594       break;
595     } // switch
596 
597     Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
598     return 0;
599   }
600   return 0;
601 }
602 
603 /// getMachineOpValue - Return binary encoding of operand. If the machine
604 /// operand requires relocation, record the relocation and return zero.
605 unsigned MipsMCCodeEmitter::
606 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
607                   SmallVectorImpl<MCFixup> &Fixups,
608                   const MCSubtargetInfo &STI) const {
609   if (MO.isReg()) {
610     unsigned Reg = MO.getReg();
611     unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
612     return RegNo;
613   } else if (MO.isImm()) {
614     return static_cast<unsigned>(MO.getImm());
615   } else if (MO.isFPImm()) {
616     return static_cast<unsigned>(APFloat(MO.getFPImm())
617         .bitcastToAPInt().getHiBits(32).getLimitedValue());
618   }
619   // MO must be an Expr.
620   assert(MO.isExpr());
621   return getExprOpValue(MO.getExpr(),Fixups, STI);
622 }
623 
624 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
625 /// instructions.
626 unsigned
627 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
628                                      SmallVectorImpl<MCFixup> &Fixups,
629                                      const MCSubtargetInfo &STI) const {
630   // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
631   assert(MI.getOperand(OpNo).isReg());
632   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
633   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
634 
635   // The immediate field of an LD/ST instruction is scaled which means it must
636   // be divided (when encoding) by the size (in bytes) of the instructions'
637   // data format.
638   // .b - 1 byte
639   // .h - 2 bytes
640   // .w - 4 bytes
641   // .d - 8 bytes
642   switch(MI.getOpcode())
643   {
644   default:
645     assert (0 && "Unexpected instruction");
646     break;
647   case Mips::LD_B:
648   case Mips::ST_B:
649     // We don't need to scale the offset in this case
650     break;
651   case Mips::LD_H:
652   case Mips::ST_H:
653     OffBits >>= 1;
654     break;
655   case Mips::LD_W:
656   case Mips::ST_W:
657     OffBits >>= 2;
658     break;
659   case Mips::LD_D:
660   case Mips::ST_D:
661     OffBits >>= 3;
662     break;
663   }
664 
665   return (OffBits & 0xFFFF) | RegBits;
666 }
667 
668 /// getMemEncoding - Return binary encoding of memory related operand.
669 /// If the offset operand requires relocation, record the relocation.
670 unsigned
671 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
672                                   SmallVectorImpl<MCFixup> &Fixups,
673                                   const MCSubtargetInfo &STI) const {
674   // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
675   assert(MI.getOperand(OpNo).isReg());
676   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
677   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
678 
679   return (OffBits & 0xFFFF) | RegBits;
680 }
681 
682 unsigned MipsMCCodeEmitter::
683 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
684                      SmallVectorImpl<MCFixup> &Fixups,
685                      const MCSubtargetInfo &STI) const {
686   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
687   assert(MI.getOperand(OpNo).isReg());
688   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
689                                        Fixups, STI) << 4;
690   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
691                                        Fixups, STI);
692 
693   return (OffBits & 0xF) | RegBits;
694 }
695 
696 unsigned MipsMCCodeEmitter::
697 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
698                          SmallVectorImpl<MCFixup> &Fixups,
699                          const MCSubtargetInfo &STI) const {
700   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
701   assert(MI.getOperand(OpNo).isReg());
702   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
703                                        Fixups, STI) << 4;
704   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
705                                        Fixups, STI) >> 1;
706 
707   return (OffBits & 0xF) | RegBits;
708 }
709 
710 unsigned MipsMCCodeEmitter::
711 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
712                          SmallVectorImpl<MCFixup> &Fixups,
713                          const MCSubtargetInfo &STI) const {
714   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
715   assert(MI.getOperand(OpNo).isReg());
716   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
717                                        Fixups, STI) << 4;
718   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
719                                        Fixups, STI) >> 2;
720 
721   return (OffBits & 0xF) | RegBits;
722 }
723 
724 unsigned MipsMCCodeEmitter::
725 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
726                            SmallVectorImpl<MCFixup> &Fixups,
727                            const MCSubtargetInfo &STI) const {
728   // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
729   assert(MI.getOperand(OpNo).isReg() &&
730          MI.getOperand(OpNo).getReg() == Mips::SP &&
731          "Unexpected base register!");
732   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
733                                        Fixups, STI) >> 2;
734 
735   return OffBits & 0x1F;
736 }
737 
738 unsigned MipsMCCodeEmitter::
739 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
740                            SmallVectorImpl<MCFixup> &Fixups,
741                            const MCSubtargetInfo &STI) const {
742   // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
743   assert(MI.getOperand(OpNo).isReg() &&
744          MI.getOperand(OpNo).getReg() == Mips::GP &&
745          "Unexpected base register!");
746 
747   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
748                                        Fixups, STI) >> 2;
749 
750   return OffBits & 0x7F;
751 }
752 
753 unsigned MipsMCCodeEmitter::
754 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
755                       SmallVectorImpl<MCFixup> &Fixups,
756                       const MCSubtargetInfo &STI) const {
757   // opNum can be invalid if instruction had reglist as operand.
758   // MemOperand is always last operand of instruction (base + offset).
759   switch (MI.getOpcode()) {
760   default:
761     break;
762   case Mips::SWM32_MM:
763   case Mips::LWM32_MM:
764     OpNo = MI.getNumOperands() - 2;
765     break;
766   }
767 
768   // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
769   assert(MI.getOperand(OpNo).isReg());
770   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
771   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
772 
773   return (OffBits & 0x0FFF) | RegBits;
774 }
775 
776 unsigned MipsMCCodeEmitter::
777 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
778                        SmallVectorImpl<MCFixup> &Fixups,
779                        const MCSubtargetInfo &STI) const {
780   // opNum can be invalid if instruction had reglist as operand
781   // MemOperand is always last operand of instruction (base + offset)
782   switch (MI.getOpcode()) {
783   default:
784     break;
785   case Mips::SWM16_MM:
786   case Mips::LWM16_MM:
787     OpNo = MI.getNumOperands() - 2;
788     break;
789   }
790 
791   // Offset is encoded in bits 4-0.
792   assert(MI.getOperand(OpNo).isReg());
793   // Base register is always SP - thus it is not encoded.
794   assert(MI.getOperand(OpNo+1).isImm());
795   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
796 
797   return ((OffBits >> 2) & 0x0F);
798 }
799 
800 unsigned
801 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
802                                       SmallVectorImpl<MCFixup> &Fixups,
803                                       const MCSubtargetInfo &STI) const {
804   assert(MI.getOperand(OpNo).isImm());
805   unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
806   return SizeEncoding - 1;
807 }
808 
809 // FIXME: should be called getMSBEncoding
810 //
811 unsigned
812 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
813                                       SmallVectorImpl<MCFixup> &Fixups,
814                                       const MCSubtargetInfo &STI) const {
815   assert(MI.getOperand(OpNo-1).isImm());
816   assert(MI.getOperand(OpNo).isImm());
817   unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
818   unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
819 
820   return Position + Size - 1;
821 }
822 
823 unsigned
824 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
825                                      SmallVectorImpl<MCFixup> &Fixups,
826                                      const MCSubtargetInfo &STI) const {
827   assert(MI.getOperand(OpNo).isImm());
828   // The immediate is encoded as 'immediate - 1'.
829   return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
830 }
831 
832 unsigned
833 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
834                                          SmallVectorImpl<MCFixup> &Fixups,
835                                          const MCSubtargetInfo &STI) const {
836   const MCOperand &MO = MI.getOperand(OpNo);
837   if (MO.isImm()) {
838     // The immediate is encoded as 'immediate << 2'.
839     unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
840     assert((Res & 3) == 0);
841     return Res >> 2;
842   }
843 
844   assert(MO.isExpr() &&
845          "getSimm19Lsl2Encoding expects only expressions or an immediate");
846 
847   const MCExpr *Expr = MO.getExpr();
848   Fixups.push_back(MCFixup::Create(0, Expr,
849                                    MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
850   return 0;
851 }
852 
853 unsigned
854 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
855                                          SmallVectorImpl<MCFixup> &Fixups,
856                                          const MCSubtargetInfo &STI) const {
857   const MCOperand &MO = MI.getOperand(OpNo);
858   if (MO.isImm()) {
859     // The immediate is encoded as 'immediate << 3'.
860     unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
861     assert((Res & 7) == 0);
862     return Res >> 3;
863   }
864 
865   assert(MO.isExpr() &&
866          "getSimm18Lsl2Encoding expects only expressions or an immediate");
867 
868   const MCExpr *Expr = MO.getExpr();
869   Fixups.push_back(MCFixup::Create(0, Expr,
870                                    MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
871   return 0;
872 }
873 
874 unsigned
875 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
876                                         SmallVectorImpl<MCFixup> &Fixups,
877                                         const MCSubtargetInfo &STI) const {
878   assert(MI.getOperand(OpNo).isImm());
879   const MCOperand &MO = MI.getOperand(OpNo);
880   return MO.getImm() % 8;
881 }
882 
883 unsigned
884 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
885                                     SmallVectorImpl<MCFixup> &Fixups,
886                                     const MCSubtargetInfo &STI) const {
887   assert(MI.getOperand(OpNo).isImm());
888   const MCOperand &MO = MI.getOperand(OpNo);
889   unsigned Value = MO.getImm();
890   switch (Value) {
891     case 128:   return 0x0;
892     case 1:     return 0x1;
893     case 2:     return 0x2;
894     case 3:     return 0x3;
895     case 4:     return 0x4;
896     case 7:     return 0x5;
897     case 8:     return 0x6;
898     case 15:    return 0x7;
899     case 16:    return 0x8;
900     case 31:    return 0x9;
901     case 32:    return 0xa;
902     case 63:    return 0xb;
903     case 64:    return 0xc;
904     case 255:   return 0xd;
905     case 32768: return 0xe;
906     case 65535: return 0xf;
907   }
908   llvm_unreachable("Unexpected value");
909 }
910 
911 unsigned
912 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
913                                           SmallVectorImpl<MCFixup> &Fixups,
914                                           const MCSubtargetInfo &STI) const {
915   unsigned res = 0;
916 
917   // Register list operand is always first operand of instruction and it is
918   // placed before memory operand (register + imm).
919 
920   for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
921     unsigned Reg = MI.getOperand(I).getReg();
922     unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
923     if (RegNo != 31)
924       res++;
925     else
926       res |= 0x10;
927   }
928   return res;
929 }
930 
931 unsigned
932 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
933                                             SmallVectorImpl<MCFixup> &Fixups,
934                                             const MCSubtargetInfo &STI) const {
935   return (MI.getNumOperands() - 4);
936 }
937 
938 unsigned
939 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
940                                           SmallVectorImpl<MCFixup> &Fixups,
941                                           const MCSubtargetInfo &STI) const {
942   return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
943 }
944 
945 unsigned
946 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
947                                           SmallVectorImpl<MCFixup> &Fixups,
948                                           const MCSubtargetInfo &STI) const {
949   unsigned res = 0;
950 
951   if (MI.getOperand(0).getReg() == Mips::A1 &&
952       MI.getOperand(1).getReg() == Mips::A2)
953     res = 0;
954   else if (MI.getOperand(0).getReg() == Mips::A1 &&
955            MI.getOperand(1).getReg() == Mips::A3)
956     res = 1;
957   else if (MI.getOperand(0).getReg() == Mips::A2 &&
958            MI.getOperand(1).getReg() == Mips::A3)
959     res = 2;
960   else if (MI.getOperand(0).getReg() == Mips::A0 &&
961            MI.getOperand(1).getReg() == Mips::S5)
962     res = 3;
963   else if (MI.getOperand(0).getReg() == Mips::A0 &&
964            MI.getOperand(1).getReg() == Mips::S6)
965     res = 4;
966   else if (MI.getOperand(0).getReg() == Mips::A0 &&
967            MI.getOperand(1).getReg() == Mips::A1)
968     res = 5;
969   else if (MI.getOperand(0).getReg() == Mips::A0 &&
970            MI.getOperand(1).getReg() == Mips::A2)
971     res = 6;
972   else if (MI.getOperand(0).getReg() == Mips::A0 &&
973            MI.getOperand(1).getReg() == Mips::A3)
974     res = 7;
975 
976   return res;
977 }
978 
979 unsigned
980 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
981                                          SmallVectorImpl<MCFixup> &Fixups,
982                                          const MCSubtargetInfo &STI) const {
983   const MCOperand &MO = MI.getOperand(OpNo);
984   assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
985   // The immediate is encoded as 'immediate >> 2'.
986   unsigned Res = static_cast<unsigned>(MO.getImm());
987   assert((Res & 3) == 0);
988   return Res >> 2;
989 }
990 
991 #include "MipsGenMCCodeEmitter.inc"
992