1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MipsMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14 
15 #include "MipsMCCodeEmitter.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCExpr.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCFixup.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
28 
29 #define DEBUG_TYPE "mccodeemitter"
30 
31 #define GET_INSTRMAP_INFO
32 #include "MipsGenInstrInfo.inc"
33 #undef GET_INSTRMAP_INFO
34 
35 namespace llvm {
36 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37                                          const MCRegisterInfo &MRI,
38                                          MCContext &Ctx) {
39   return new MipsMCCodeEmitter(MCII, Ctx, false);
40 }
41 
42 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
43                                          const MCRegisterInfo &MRI,
44                                          MCContext &Ctx) {
45   return new MipsMCCodeEmitter(MCII, Ctx, true);
46 }
47 } // End of namespace llvm.
48 
49 // If the D<shift> instruction has a shift amount that is greater
50 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
51 static void LowerLargeShift(MCInst& Inst) {
52 
53   assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
54   assert(Inst.getOperand(2).isImm());
55 
56   int64_t Shift = Inst.getOperand(2).getImm();
57   if (Shift <= 31)
58     return; // Do nothing
59   Shift -= 32;
60 
61   // saminus32
62   Inst.getOperand(2).setImm(Shift);
63 
64   switch (Inst.getOpcode()) {
65   default:
66     // Calling function is not synchronized
67     llvm_unreachable("Unexpected shift instruction");
68   case Mips::DSLL:
69     Inst.setOpcode(Mips::DSLL32);
70     return;
71   case Mips::DSRL:
72     Inst.setOpcode(Mips::DSRL32);
73     return;
74   case Mips::DSRA:
75     Inst.setOpcode(Mips::DSRA32);
76     return;
77   case Mips::DROTR:
78     Inst.setOpcode(Mips::DROTR32);
79     return;
80   }
81 }
82 
83 // Pick a DEXT or DINS instruction variant based on the pos and size operands
84 static void LowerDextDins(MCInst& InstIn) {
85   int Opcode = InstIn.getOpcode();
86 
87   if (Opcode == Mips::DEXT)
88     assert(InstIn.getNumOperands() == 4 &&
89            "Invalid no. of machine operands for DEXT!");
90   else // Only DEXT and DINS are possible
91     assert(InstIn.getNumOperands() == 5 &&
92            "Invalid no. of machine operands for DINS!");
93 
94   assert(InstIn.getOperand(2).isImm());
95   int64_t pos = InstIn.getOperand(2).getImm();
96   assert(InstIn.getOperand(3).isImm());
97   int64_t size = InstIn.getOperand(3).getImm();
98 
99   if (size <= 32) {
100     if (pos < 32)  // DEXT/DINS, do nothing
101       return;
102     // DEXTU/DINSU
103     InstIn.getOperand(2).setImm(pos - 32);
104     InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
105     return;
106   }
107   // DEXTM/DINSM
108   assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
109   InstIn.getOperand(3).setImm(size - 32);
110   InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
111   return;
112 }
113 
114 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
115   return STI.getFeatureBits() & Mips::FeatureMicroMips;
116 }
117 
118 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
119   return STI.getFeatureBits() & Mips::FeatureMips32r6;
120 }
121 
122 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
123   OS << (char)C;
124 }
125 
126 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
127                                         const MCSubtargetInfo &STI,
128                                         raw_ostream &OS) const {
129   // Output the instruction encoding in little endian byte order.
130   // Little-endian byte ordering:
131   //   mips32r2:   4 | 3 | 2 | 1
132   //   microMIPS:  2 | 1 | 4 | 3
133   if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
134     EmitInstruction(Val >> 16, 2, STI, OS);
135     EmitInstruction(Val, 2, STI, OS);
136   } else {
137     for (unsigned i = 0; i < Size; ++i) {
138       unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
139       EmitByte((Val >> Shift) & 0xff, OS);
140     }
141   }
142 }
143 
144 /// EncodeInstruction - Emit the instruction.
145 /// Size the instruction with Desc.getSize().
146 void MipsMCCodeEmitter::
147 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
148                   SmallVectorImpl<MCFixup> &Fixups,
149                   const MCSubtargetInfo &STI) const
150 {
151 
152   // Non-pseudo instructions that get changed for direct object
153   // only based on operand values.
154   // If this list of instructions get much longer we will move
155   // the check to a function call. Until then, this is more efficient.
156   MCInst TmpInst = MI;
157   switch (MI.getOpcode()) {
158   // If shift amount is >= 32 it the inst needs to be lowered further
159   case Mips::DSLL:
160   case Mips::DSRL:
161   case Mips::DSRA:
162   case Mips::DROTR:
163     LowerLargeShift(TmpInst);
164     break;
165     // Double extract instruction is chosen by pos and size operands
166   case Mips::DEXT:
167   case Mips::DINS:
168     LowerDextDins(TmpInst);
169   }
170 
171   unsigned long N = Fixups.size();
172   uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
173 
174   // Check for unimplemented opcodes.
175   // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
176   // so we have to special check for them.
177   unsigned Opcode = TmpInst.getOpcode();
178   if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
179       (Opcode != Mips::SLL_MM) && !Binary)
180     llvm_unreachable("unimplemented opcode in EncodeInstruction()");
181 
182   if (isMicroMips(STI)) {
183     int NewOpcode = isMips32r6(STI) ?
184                     Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6) :
185                     Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
186     if (NewOpcode != -1) {
187       if (Fixups.size() > N)
188         Fixups.pop_back();
189       Opcode = NewOpcode;
190       TmpInst.setOpcode (NewOpcode);
191       Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
192     }
193   }
194 
195   const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
196 
197   // Get byte count of instruction
198   unsigned Size = Desc.getSize();
199   if (!Size)
200     llvm_unreachable("Desc.getSize() returns 0");
201 
202   EmitInstruction(Binary, Size, STI, OS);
203 }
204 
205 /// getBranchTargetOpValue - Return binary encoding of the branch
206 /// target operand. If the machine operand requires relocation,
207 /// record the relocation and return zero.
208 unsigned MipsMCCodeEmitter::
209 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
210                        SmallVectorImpl<MCFixup> &Fixups,
211                        const MCSubtargetInfo &STI) const {
212 
213   const MCOperand &MO = MI.getOperand(OpNo);
214 
215   // If the destination is an immediate, divide by 4.
216   if (MO.isImm()) return MO.getImm() >> 2;
217 
218   assert(MO.isExpr() &&
219          "getBranchTargetOpValue expects only expressions or immediates");
220 
221   const MCExpr *Expr = MO.getExpr();
222   Fixups.push_back(MCFixup::Create(0, Expr,
223                                    MCFixupKind(Mips::fixup_Mips_PC16)));
224   return 0;
225 }
226 
227 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
228 /// target operand. If the machine operand requires relocation,
229 /// record the relocation and return zero.
230 unsigned MipsMCCodeEmitter::
231 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
232                           SmallVectorImpl<MCFixup> &Fixups,
233                           const MCSubtargetInfo &STI) const {
234 
235   const MCOperand &MO = MI.getOperand(OpNo);
236 
237   // If the destination is an immediate, divide by 2.
238   if (MO.isImm()) return MO.getImm() >> 1;
239 
240   assert(MO.isExpr() &&
241          "getBranchTargetOpValueMM expects only expressions or immediates");
242 
243   const MCExpr *Expr = MO.getExpr();
244   Fixups.push_back(MCFixup::Create(0, Expr,
245                                    MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
246   return 0;
247 }
248 
249 /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
250 /// 10-bit branch target operand. If the machine operand requires relocation,
251 /// record the relocation and return zero.
252 unsigned MipsMCCodeEmitter::
253 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
254                              SmallVectorImpl<MCFixup> &Fixups,
255                              const MCSubtargetInfo &STI) const {
256 
257   const MCOperand &MO = MI.getOperand(OpNo);
258 
259   // If the destination is an immediate, divide by 2.
260   if (MO.isImm()) return MO.getImm() >> 1;
261 
262   assert(MO.isExpr() &&
263          "getBranchTargetOpValuePC10 expects only expressions or immediates");
264 
265   const MCExpr *Expr = MO.getExpr();
266   Fixups.push_back(MCFixup::Create(0, Expr,
267                    MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
268   return 0;
269 }
270 
271 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
272 /// target operand. If the machine operand requires relocation,
273 /// record the relocation and return zero.
274 unsigned MipsMCCodeEmitter::
275 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
276                          SmallVectorImpl<MCFixup> &Fixups,
277                          const MCSubtargetInfo &STI) const {
278 
279   const MCOperand &MO = MI.getOperand(OpNo);
280 
281   // If the destination is an immediate, divide by 2.
282   if (MO.isImm()) return MO.getImm() >> 1;
283 
284   assert(MO.isExpr() &&
285          "getBranchTargetOpValueMM expects only expressions or immediates");
286 
287   const MCExpr *Expr = MO.getExpr();
288   Fixups.push_back(MCFixup::Create(0, Expr,
289                    MCFixupKind(Mips::
290                                fixup_MICROMIPS_PC16_S1)));
291   return 0;
292 }
293 
294 /// getBranchTarget21OpValue - Return binary encoding of the branch
295 /// target operand. If the machine operand requires relocation,
296 /// record the relocation and return zero.
297 unsigned MipsMCCodeEmitter::
298 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
299                          SmallVectorImpl<MCFixup> &Fixups,
300                          const MCSubtargetInfo &STI) const {
301 
302   const MCOperand &MO = MI.getOperand(OpNo);
303 
304   // If the destination is an immediate, divide by 4.
305   if (MO.isImm()) return MO.getImm() >> 2;
306 
307   assert(MO.isExpr() &&
308          "getBranchTarget21OpValue expects only expressions or immediates");
309 
310   const MCExpr *Expr = MO.getExpr();
311   Fixups.push_back(MCFixup::Create(0, Expr,
312                                    MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
313   return 0;
314 }
315 
316 /// getBranchTarget26OpValue - Return binary encoding of the branch
317 /// target operand. If the machine operand requires relocation,
318 /// record the relocation and return zero.
319 unsigned MipsMCCodeEmitter::
320 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
321                          SmallVectorImpl<MCFixup> &Fixups,
322                          const MCSubtargetInfo &STI) const {
323 
324   const MCOperand &MO = MI.getOperand(OpNo);
325 
326   // If the destination is an immediate, divide by 4.
327   if (MO.isImm()) return MO.getImm() >> 2;
328 
329   assert(MO.isExpr() &&
330          "getBranchTarget26OpValue expects only expressions or immediates");
331 
332   const MCExpr *Expr = MO.getExpr();
333   Fixups.push_back(MCFixup::Create(0, Expr,
334                                    MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
335   return 0;
336 }
337 
338 /// getJumpOffset16OpValue - Return binary encoding of the jump
339 /// target operand. If the machine operand requires relocation,
340 /// record the relocation and return zero.
341 unsigned MipsMCCodeEmitter::
342 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
343                        SmallVectorImpl<MCFixup> &Fixups,
344                        const MCSubtargetInfo &STI) const {
345 
346   const MCOperand &MO = MI.getOperand(OpNo);
347 
348   if (MO.isImm()) return MO.getImm();
349 
350   assert(MO.isExpr() &&
351          "getJumpOffset16OpValue expects only expressions or an immediate");
352 
353    // TODO: Push fixup.
354    return 0;
355 }
356 
357 /// getJumpTargetOpValue - Return binary encoding of the jump
358 /// target operand. If the machine operand requires relocation,
359 /// record the relocation and return zero.
360 unsigned MipsMCCodeEmitter::
361 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
362                      SmallVectorImpl<MCFixup> &Fixups,
363                      const MCSubtargetInfo &STI) const {
364 
365   const MCOperand &MO = MI.getOperand(OpNo);
366   // If the destination is an immediate, divide by 4.
367   if (MO.isImm()) return MO.getImm()>>2;
368 
369   assert(MO.isExpr() &&
370          "getJumpTargetOpValue expects only expressions or an immediate");
371 
372   const MCExpr *Expr = MO.getExpr();
373   Fixups.push_back(MCFixup::Create(0, Expr,
374                                    MCFixupKind(Mips::fixup_Mips_26)));
375   return 0;
376 }
377 
378 unsigned MipsMCCodeEmitter::
379 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
380                        SmallVectorImpl<MCFixup> &Fixups,
381                        const MCSubtargetInfo &STI) const {
382 
383   const MCOperand &MO = MI.getOperand(OpNo);
384   // If the destination is an immediate, divide by 2.
385   if (MO.isImm()) return MO.getImm() >> 1;
386 
387   assert(MO.isExpr() &&
388          "getJumpTargetOpValueMM expects only expressions or an immediate");
389 
390   const MCExpr *Expr = MO.getExpr();
391   Fixups.push_back(MCFixup::Create(0, Expr,
392                                    MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
393   return 0;
394 }
395 
396 unsigned MipsMCCodeEmitter::
397 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
398                      SmallVectorImpl<MCFixup> &Fixups,
399                      const MCSubtargetInfo &STI) const {
400 
401   const MCOperand &MO = MI.getOperand(OpNo);
402   if (MO.isImm()) {
403     // The immediate is encoded as 'immediate << 2'.
404     unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
405     assert((Res & 3) == 0);
406     return Res >> 2;
407   }
408 
409   assert(MO.isExpr() &&
410          "getUImm5Lsl2Encoding expects only expressions or an immediate");
411 
412   return 0;
413 }
414 
415 unsigned MipsMCCodeEmitter::
416 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
417                   SmallVectorImpl<MCFixup> &Fixups,
418                   const MCSubtargetInfo &STI) const {
419 
420   const MCOperand &MO = MI.getOperand(OpNo);
421   if (MO.isImm()) {
422     int Value = MO.getImm();
423     return Value >> 2;
424   }
425 
426   return 0;
427 }
428 
429 unsigned MipsMCCodeEmitter::
430 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
431                      SmallVectorImpl<MCFixup> &Fixups,
432                      const MCSubtargetInfo &STI) const {
433 
434   const MCOperand &MO = MI.getOperand(OpNo);
435   if (MO.isImm()) {
436     unsigned Value = MO.getImm();
437     return Value >> 2;
438   }
439 
440   return 0;
441 }
442 
443 unsigned MipsMCCodeEmitter::
444 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
445                      SmallVectorImpl<MCFixup> &Fixups,
446                      const MCSubtargetInfo &STI) const {
447 
448   const MCOperand &MO = MI.getOperand(OpNo);
449   if (MO.isImm()) {
450     unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
451     return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
452   }
453 
454   return 0;
455 }
456 
457 unsigned MipsMCCodeEmitter::
458 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
459                const MCSubtargetInfo &STI) const {
460   int64_t Res;
461 
462   if (Expr->EvaluateAsAbsolute(Res))
463     return Res;
464 
465   MCExpr::ExprKind Kind = Expr->getKind();
466   if (Kind == MCExpr::Constant) {
467     return cast<MCConstantExpr>(Expr)->getValue();
468   }
469 
470   if (Kind == MCExpr::Binary) {
471     unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
472     Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
473     return Res;
474   }
475 
476   if (Kind == MCExpr::Target) {
477     const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
478 
479     Mips::Fixups FixupKind = Mips::Fixups(0);
480     switch (MipsExpr->getKind()) {
481     default: llvm_unreachable("Unsupported fixup kind for target expression!");
482     case MipsMCExpr::VK_Mips_HIGHEST:
483       FixupKind = Mips::fixup_Mips_HIGHEST;
484       break;
485     case MipsMCExpr::VK_Mips_HIGHER:
486       FixupKind = Mips::fixup_Mips_HIGHER;
487       break;
488     case MipsMCExpr::VK_Mips_HI:
489       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
490                                    : Mips::fixup_Mips_HI16;
491       break;
492     case MipsMCExpr::VK_Mips_LO:
493       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
494                                    : Mips::fixup_Mips_LO16;
495       break;
496     }
497     Fixups.push_back(MCFixup::Create(0, MipsExpr, MCFixupKind(FixupKind)));
498     return 0;
499   }
500 
501   if (Kind == MCExpr::SymbolRef) {
502     Mips::Fixups FixupKind = Mips::Fixups(0);
503 
504     switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
505     default: llvm_unreachable("Unknown fixup kind!");
506       break;
507     case MCSymbolRefExpr::VK_None:
508       FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
509       break;
510     case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
511       FixupKind = Mips::fixup_Mips_GPOFF_HI;
512       break;
513     case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
514       FixupKind = Mips::fixup_Mips_GPOFF_LO;
515       break;
516     case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
517       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
518                               : Mips::fixup_Mips_GOT_PAGE;
519       break;
520     case MCSymbolRefExpr::VK_Mips_GOT_OFST :
521       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
522                               : Mips::fixup_Mips_GOT_OFST;
523       break;
524     case MCSymbolRefExpr::VK_Mips_GOT_DISP :
525       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
526                               : Mips::fixup_Mips_GOT_DISP;
527       break;
528     case MCSymbolRefExpr::VK_Mips_GPREL:
529       FixupKind = Mips::fixup_Mips_GPREL16;
530       break;
531     case MCSymbolRefExpr::VK_Mips_GOT_CALL:
532       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
533                               : Mips::fixup_Mips_CALL16;
534       break;
535     case MCSymbolRefExpr::VK_Mips_GOT16:
536       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
537                               : Mips::fixup_Mips_GOT_Global;
538       break;
539     case MCSymbolRefExpr::VK_Mips_GOT:
540       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
541                               : Mips::fixup_Mips_GOT_Local;
542       break;
543     case MCSymbolRefExpr::VK_Mips_ABS_HI:
544       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
545                               : Mips::fixup_Mips_HI16;
546       break;
547     case MCSymbolRefExpr::VK_Mips_ABS_LO:
548       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
549                               : Mips::fixup_Mips_LO16;
550       break;
551     case MCSymbolRefExpr::VK_Mips_TLSGD:
552       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
553                               : Mips::fixup_Mips_TLSGD;
554       break;
555     case MCSymbolRefExpr::VK_Mips_TLSLDM:
556       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
557                               : Mips::fixup_Mips_TLSLDM;
558       break;
559     case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
560       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
561                               : Mips::fixup_Mips_DTPREL_HI;
562       break;
563     case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
564       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
565                               : Mips::fixup_Mips_DTPREL_LO;
566       break;
567     case MCSymbolRefExpr::VK_Mips_GOTTPREL:
568       FixupKind = Mips::fixup_Mips_GOTTPREL;
569       break;
570     case MCSymbolRefExpr::VK_Mips_TPREL_HI:
571       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
572                               : Mips::fixup_Mips_TPREL_HI;
573       break;
574     case MCSymbolRefExpr::VK_Mips_TPREL_LO:
575       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
576                               : Mips::fixup_Mips_TPREL_LO;
577       break;
578     case MCSymbolRefExpr::VK_Mips_HIGHER:
579       FixupKind = Mips::fixup_Mips_HIGHER;
580       break;
581     case MCSymbolRefExpr::VK_Mips_HIGHEST:
582       FixupKind = Mips::fixup_Mips_HIGHEST;
583       break;
584     case MCSymbolRefExpr::VK_Mips_GOT_HI16:
585       FixupKind = Mips::fixup_Mips_GOT_HI16;
586       break;
587     case MCSymbolRefExpr::VK_Mips_GOT_LO16:
588       FixupKind = Mips::fixup_Mips_GOT_LO16;
589       break;
590     case MCSymbolRefExpr::VK_Mips_CALL_HI16:
591       FixupKind = Mips::fixup_Mips_CALL_HI16;
592       break;
593     case MCSymbolRefExpr::VK_Mips_CALL_LO16:
594       FixupKind = Mips::fixup_Mips_CALL_LO16;
595       break;
596     case MCSymbolRefExpr::VK_Mips_PCREL_HI16:
597       FixupKind = Mips::fixup_MIPS_PCHI16;
598       break;
599     case MCSymbolRefExpr::VK_Mips_PCREL_LO16:
600       FixupKind = Mips::fixup_MIPS_PCLO16;
601       break;
602     } // switch
603 
604     Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
605     return 0;
606   }
607   return 0;
608 }
609 
610 /// getMachineOpValue - Return binary encoding of operand. If the machine
611 /// operand requires relocation, record the relocation and return zero.
612 unsigned MipsMCCodeEmitter::
613 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
614                   SmallVectorImpl<MCFixup> &Fixups,
615                   const MCSubtargetInfo &STI) const {
616   if (MO.isReg()) {
617     unsigned Reg = MO.getReg();
618     unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
619     return RegNo;
620   } else if (MO.isImm()) {
621     return static_cast<unsigned>(MO.getImm());
622   } else if (MO.isFPImm()) {
623     return static_cast<unsigned>(APFloat(MO.getFPImm())
624         .bitcastToAPInt().getHiBits(32).getLimitedValue());
625   }
626   // MO must be an Expr.
627   assert(MO.isExpr());
628   return getExprOpValue(MO.getExpr(),Fixups, STI);
629 }
630 
631 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
632 /// instructions.
633 unsigned
634 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
635                                      SmallVectorImpl<MCFixup> &Fixups,
636                                      const MCSubtargetInfo &STI) const {
637   // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
638   assert(MI.getOperand(OpNo).isReg());
639   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
640   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
641 
642   // The immediate field of an LD/ST instruction is scaled which means it must
643   // be divided (when encoding) by the size (in bytes) of the instructions'
644   // data format.
645   // .b - 1 byte
646   // .h - 2 bytes
647   // .w - 4 bytes
648   // .d - 8 bytes
649   switch(MI.getOpcode())
650   {
651   default:
652     assert (0 && "Unexpected instruction");
653     break;
654   case Mips::LD_B:
655   case Mips::ST_B:
656     // We don't need to scale the offset in this case
657     break;
658   case Mips::LD_H:
659   case Mips::ST_H:
660     OffBits >>= 1;
661     break;
662   case Mips::LD_W:
663   case Mips::ST_W:
664     OffBits >>= 2;
665     break;
666   case Mips::LD_D:
667   case Mips::ST_D:
668     OffBits >>= 3;
669     break;
670   }
671 
672   return (OffBits & 0xFFFF) | RegBits;
673 }
674 
675 /// getMemEncoding - Return binary encoding of memory related operand.
676 /// If the offset operand requires relocation, record the relocation.
677 unsigned
678 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
679                                   SmallVectorImpl<MCFixup> &Fixups,
680                                   const MCSubtargetInfo &STI) const {
681   // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
682   assert(MI.getOperand(OpNo).isReg());
683   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
684   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
685 
686   return (OffBits & 0xFFFF) | RegBits;
687 }
688 
689 unsigned MipsMCCodeEmitter::
690 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
691                      SmallVectorImpl<MCFixup> &Fixups,
692                      const MCSubtargetInfo &STI) const {
693   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
694   assert(MI.getOperand(OpNo).isReg());
695   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
696                                        Fixups, STI) << 4;
697   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
698                                        Fixups, STI);
699 
700   return (OffBits & 0xF) | RegBits;
701 }
702 
703 unsigned MipsMCCodeEmitter::
704 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
705                          SmallVectorImpl<MCFixup> &Fixups,
706                          const MCSubtargetInfo &STI) const {
707   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
708   assert(MI.getOperand(OpNo).isReg());
709   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
710                                        Fixups, STI) << 4;
711   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
712                                        Fixups, STI) >> 1;
713 
714   return (OffBits & 0xF) | RegBits;
715 }
716 
717 unsigned MipsMCCodeEmitter::
718 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
719                          SmallVectorImpl<MCFixup> &Fixups,
720                          const MCSubtargetInfo &STI) const {
721   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
722   assert(MI.getOperand(OpNo).isReg());
723   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
724                                        Fixups, STI) << 4;
725   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
726                                        Fixups, STI) >> 2;
727 
728   return (OffBits & 0xF) | RegBits;
729 }
730 
731 unsigned MipsMCCodeEmitter::
732 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
733                            SmallVectorImpl<MCFixup> &Fixups,
734                            const MCSubtargetInfo &STI) const {
735   // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
736   assert(MI.getOperand(OpNo).isReg() &&
737          MI.getOperand(OpNo).getReg() == Mips::SP &&
738          "Unexpected base register!");
739   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
740                                        Fixups, STI) >> 2;
741 
742   return OffBits & 0x1F;
743 }
744 
745 unsigned MipsMCCodeEmitter::
746 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
747                            SmallVectorImpl<MCFixup> &Fixups,
748                            const MCSubtargetInfo &STI) const {
749   // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
750   assert(MI.getOperand(OpNo).isReg() &&
751          MI.getOperand(OpNo).getReg() == Mips::GP &&
752          "Unexpected base register!");
753 
754   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
755                                        Fixups, STI) >> 2;
756 
757   return OffBits & 0x7F;
758 }
759 
760 unsigned MipsMCCodeEmitter::
761 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
762                       SmallVectorImpl<MCFixup> &Fixups,
763                       const MCSubtargetInfo &STI) const {
764   // opNum can be invalid if instruction had reglist as operand.
765   // MemOperand is always last operand of instruction (base + offset).
766   switch (MI.getOpcode()) {
767   default:
768     break;
769   case Mips::SWM32_MM:
770   case Mips::LWM32_MM:
771     OpNo = MI.getNumOperands() - 2;
772     break;
773   }
774 
775   // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
776   assert(MI.getOperand(OpNo).isReg());
777   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
778   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
779 
780   return (OffBits & 0x0FFF) | RegBits;
781 }
782 
783 unsigned MipsMCCodeEmitter::
784 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
785                        SmallVectorImpl<MCFixup> &Fixups,
786                        const MCSubtargetInfo &STI) const {
787   // opNum can be invalid if instruction had reglist as operand
788   // MemOperand is always last operand of instruction (base + offset)
789   switch (MI.getOpcode()) {
790   default:
791     break;
792   case Mips::SWM16_MM:
793   case Mips::LWM16_MM:
794     OpNo = MI.getNumOperands() - 2;
795     break;
796   }
797 
798   // Offset is encoded in bits 4-0.
799   assert(MI.getOperand(OpNo).isReg());
800   // Base register is always SP - thus it is not encoded.
801   assert(MI.getOperand(OpNo+1).isImm());
802   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
803 
804   return ((OffBits >> 2) & 0x0F);
805 }
806 
807 unsigned
808 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
809                                       SmallVectorImpl<MCFixup> &Fixups,
810                                       const MCSubtargetInfo &STI) const {
811   assert(MI.getOperand(OpNo).isImm());
812   unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
813   return SizeEncoding - 1;
814 }
815 
816 // FIXME: should be called getMSBEncoding
817 //
818 unsigned
819 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
820                                       SmallVectorImpl<MCFixup> &Fixups,
821                                       const MCSubtargetInfo &STI) const {
822   assert(MI.getOperand(OpNo-1).isImm());
823   assert(MI.getOperand(OpNo).isImm());
824   unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
825   unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
826 
827   return Position + Size - 1;
828 }
829 
830 unsigned
831 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
832                                      SmallVectorImpl<MCFixup> &Fixups,
833                                      const MCSubtargetInfo &STI) const {
834   assert(MI.getOperand(OpNo).isImm());
835   // The immediate is encoded as 'immediate - 1'.
836   return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
837 }
838 
839 unsigned
840 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
841                                          SmallVectorImpl<MCFixup> &Fixups,
842                                          const MCSubtargetInfo &STI) const {
843   const MCOperand &MO = MI.getOperand(OpNo);
844   if (MO.isImm()) {
845     // The immediate is encoded as 'immediate << 2'.
846     unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
847     assert((Res & 3) == 0);
848     return Res >> 2;
849   }
850 
851   assert(MO.isExpr() &&
852          "getSimm19Lsl2Encoding expects only expressions or an immediate");
853 
854   const MCExpr *Expr = MO.getExpr();
855   Fixups.push_back(MCFixup::Create(0, Expr,
856                                    MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
857   return 0;
858 }
859 
860 unsigned
861 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
862                                          SmallVectorImpl<MCFixup> &Fixups,
863                                          const MCSubtargetInfo &STI) const {
864   const MCOperand &MO = MI.getOperand(OpNo);
865   if (MO.isImm()) {
866     // The immediate is encoded as 'immediate << 3'.
867     unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
868     assert((Res & 7) == 0);
869     return Res >> 3;
870   }
871 
872   assert(MO.isExpr() &&
873          "getSimm18Lsl2Encoding expects only expressions or an immediate");
874 
875   const MCExpr *Expr = MO.getExpr();
876   Fixups.push_back(MCFixup::Create(0, Expr,
877                                    MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
878   return 0;
879 }
880 
881 unsigned
882 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
883                                         SmallVectorImpl<MCFixup> &Fixups,
884                                         const MCSubtargetInfo &STI) const {
885   assert(MI.getOperand(OpNo).isImm());
886   const MCOperand &MO = MI.getOperand(OpNo);
887   return MO.getImm() % 8;
888 }
889 
890 unsigned
891 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
892                                     SmallVectorImpl<MCFixup> &Fixups,
893                                     const MCSubtargetInfo &STI) const {
894   assert(MI.getOperand(OpNo).isImm());
895   const MCOperand &MO = MI.getOperand(OpNo);
896   unsigned Value = MO.getImm();
897   switch (Value) {
898     case 128:   return 0x0;
899     case 1:     return 0x1;
900     case 2:     return 0x2;
901     case 3:     return 0x3;
902     case 4:     return 0x4;
903     case 7:     return 0x5;
904     case 8:     return 0x6;
905     case 15:    return 0x7;
906     case 16:    return 0x8;
907     case 31:    return 0x9;
908     case 32:    return 0xa;
909     case 63:    return 0xb;
910     case 64:    return 0xc;
911     case 255:   return 0xd;
912     case 32768: return 0xe;
913     case 65535: return 0xf;
914   }
915   llvm_unreachable("Unexpected value");
916 }
917 
918 unsigned
919 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
920                                           SmallVectorImpl<MCFixup> &Fixups,
921                                           const MCSubtargetInfo &STI) const {
922   unsigned res = 0;
923 
924   // Register list operand is always first operand of instruction and it is
925   // placed before memory operand (register + imm).
926 
927   for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
928     unsigned Reg = MI.getOperand(I).getReg();
929     unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
930     if (RegNo != 31)
931       res++;
932     else
933       res |= 0x10;
934   }
935   return res;
936 }
937 
938 unsigned
939 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
940                                             SmallVectorImpl<MCFixup> &Fixups,
941                                             const MCSubtargetInfo &STI) const {
942   return (MI.getNumOperands() - 4);
943 }
944 
945 unsigned
946 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
947                                           SmallVectorImpl<MCFixup> &Fixups,
948                                           const MCSubtargetInfo &STI) const {
949   return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
950 }
951 
952 unsigned
953 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
954                                           SmallVectorImpl<MCFixup> &Fixups,
955                                           const MCSubtargetInfo &STI) const {
956   unsigned res = 0;
957 
958   if (MI.getOperand(0).getReg() == Mips::A1 &&
959       MI.getOperand(1).getReg() == Mips::A2)
960     res = 0;
961   else if (MI.getOperand(0).getReg() == Mips::A1 &&
962            MI.getOperand(1).getReg() == Mips::A3)
963     res = 1;
964   else if (MI.getOperand(0).getReg() == Mips::A2 &&
965            MI.getOperand(1).getReg() == Mips::A3)
966     res = 2;
967   else if (MI.getOperand(0).getReg() == Mips::A0 &&
968            MI.getOperand(1).getReg() == Mips::S5)
969     res = 3;
970   else if (MI.getOperand(0).getReg() == Mips::A0 &&
971            MI.getOperand(1).getReg() == Mips::S6)
972     res = 4;
973   else if (MI.getOperand(0).getReg() == Mips::A0 &&
974            MI.getOperand(1).getReg() == Mips::A1)
975     res = 5;
976   else if (MI.getOperand(0).getReg() == Mips::A0 &&
977            MI.getOperand(1).getReg() == Mips::A2)
978     res = 6;
979   else if (MI.getOperand(0).getReg() == Mips::A0 &&
980            MI.getOperand(1).getReg() == Mips::A3)
981     res = 7;
982 
983   return res;
984 }
985 
986 unsigned
987 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
988                                          SmallVectorImpl<MCFixup> &Fixups,
989                                          const MCSubtargetInfo &STI) const {
990   const MCOperand &MO = MI.getOperand(OpNo);
991   assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
992   // The immediate is encoded as 'immediate >> 2'.
993   unsigned Res = static_cast<unsigned>(MO.getImm());
994   assert((Res & 3) == 0);
995   return Res >> 2;
996 }
997 
998 #include "MipsGenMCCodeEmitter.inc"
999