1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that BPF uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "BPFISelLowering.h" 16 #include "BPF.h" 17 #include "BPFSubtarget.h" 18 #include "BPFTargetMachine.h" 19 #include "llvm/CodeGen/CallingConvLower.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/SelectionDAGISel.h" 25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/IR/DiagnosticInfo.h" 28 #include "llvm/IR/DiagnosticPrinter.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/raw_ostream.h" 32 using namespace llvm; 33 34 #define DEBUG_TYPE "bpf-lower" 35 36 static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg) { 37 MachineFunction &MF = DAG.getMachineFunction(); 38 DAG.getContext()->diagnose( 39 DiagnosticInfoUnsupported(*MF.getFunction(), Msg, DL.getDebugLoc())); 40 } 41 42 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg, 43 SDValue Val) { 44 MachineFunction &MF = DAG.getMachineFunction(); 45 std::string Str; 46 raw_string_ostream OS(Str); 47 OS << Msg; 48 Val->print(OS); 49 OS.flush(); 50 DAG.getContext()->diagnose( 51 DiagnosticInfoUnsupported(*MF.getFunction(), Str, DL.getDebugLoc())); 52 } 53 54 BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM, 55 const BPFSubtarget &STI) 56 : TargetLowering(TM) { 57 58 // Set up the register classes. 59 addRegisterClass(MVT::i64, &BPF::GPRRegClass); 60 61 // Compute derived properties from the register classes 62 computeRegisterProperties(STI.getRegisterInfo()); 63 64 setStackPointerRegisterToSaveRestore(BPF::R11); 65 66 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 67 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 68 setOperationAction(ISD::BRIND, MVT::Other, Expand); 69 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 70 setOperationAction(ISD::SETCC, MVT::i64, Expand); 71 setOperationAction(ISD::SELECT, MVT::i64, Expand); 72 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 73 74 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 75 76 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 77 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 78 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 79 80 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 81 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 82 setOperationAction(ISD::SREM, MVT::i64, Expand); 83 setOperationAction(ISD::UREM, MVT::i64, Expand); 84 85 setOperationAction(ISD::MULHU, MVT::i64, Expand); 86 setOperationAction(ISD::MULHS, MVT::i64, Expand); 87 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 88 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 89 90 setOperationAction(ISD::ADDC, MVT::i64, Expand); 91 setOperationAction(ISD::ADDE, MVT::i64, Expand); 92 setOperationAction(ISD::SUBC, MVT::i64, Expand); 93 setOperationAction(ISD::SUBE, MVT::i64, Expand); 94 95 setOperationAction(ISD::ROTR, MVT::i64, Expand); 96 setOperationAction(ISD::ROTL, MVT::i64, Expand); 97 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); 98 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); 99 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); 100 101 setOperationAction(ISD::CTTZ, MVT::i64, Custom); 102 setOperationAction(ISD::CTLZ, MVT::i64, Custom); 103 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom); 104 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 105 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 106 107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); 111 112 // Extended load operations for i1 types must be promoted 113 for (MVT VT : MVT::integer_valuetypes()) { 114 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 115 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 116 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 117 118 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 119 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); 120 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); 121 } 122 123 setBooleanContents(ZeroOrOneBooleanContent); 124 125 // Function alignments (log2) 126 setMinFunctionAlignment(3); 127 setPrefFunctionAlignment(3); 128 129 // inline memcpy() for kernel to see explicit copy 130 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 128; 131 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 128; 132 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 128; 133 134 // CPU/Feature control 135 HasJmpExt = STI.getHasJmpExt(); 136 } 137 138 bool BPFTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 139 return false; 140 } 141 142 std::pair<unsigned, const TargetRegisterClass *> 143 BPFTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 144 StringRef Constraint, 145 MVT VT) const { 146 if (Constraint.size() == 1) 147 // GCC Constraint Letters 148 switch (Constraint[0]) { 149 case 'r': // GENERAL_REGS 150 return std::make_pair(0U, &BPF::GPRRegClass); 151 default: 152 break; 153 } 154 155 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 156 } 157 158 SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 159 switch (Op.getOpcode()) { 160 case ISD::BR_CC: 161 return LowerBR_CC(Op, DAG); 162 case ISD::GlobalAddress: 163 return LowerGlobalAddress(Op, DAG); 164 case ISD::SELECT_CC: 165 return LowerSELECT_CC(Op, DAG); 166 default: 167 llvm_unreachable("unimplemented operand"); 168 } 169 } 170 171 // Calling Convention Implementation 172 #include "BPFGenCallingConv.inc" 173 174 SDValue BPFTargetLowering::LowerFormalArguments( 175 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 176 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 177 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 178 switch (CallConv) { 179 default: 180 report_fatal_error("Unsupported calling convention"); 181 case CallingConv::C: 182 case CallingConv::Fast: 183 break; 184 } 185 186 MachineFunction &MF = DAG.getMachineFunction(); 187 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 188 189 // Assign locations to all of the incoming arguments. 190 SmallVector<CCValAssign, 16> ArgLocs; 191 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 192 CCInfo.AnalyzeFormalArguments(Ins, CC_BPF64); 193 194 for (auto &VA : ArgLocs) { 195 if (VA.isRegLoc()) { 196 // Arguments passed in registers 197 EVT RegVT = VA.getLocVT(); 198 switch (RegVT.getSimpleVT().SimpleTy) { 199 default: { 200 errs() << "LowerFormalArguments Unhandled argument type: " 201 << RegVT.getEVTString() << '\n'; 202 llvm_unreachable(0); 203 } 204 case MVT::i64: 205 unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass); 206 RegInfo.addLiveIn(VA.getLocReg(), VReg); 207 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); 208 209 // If this is an 8/16/32-bit value, it is really passed promoted to 64 210 // bits. Insert an assert[sz]ext to capture this, then truncate to the 211 // right size. 212 if (VA.getLocInfo() == CCValAssign::SExt) 213 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, 214 DAG.getValueType(VA.getValVT())); 215 else if (VA.getLocInfo() == CCValAssign::ZExt) 216 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, 217 DAG.getValueType(VA.getValVT())); 218 219 if (VA.getLocInfo() != CCValAssign::Full) 220 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); 221 222 InVals.push_back(ArgValue); 223 } 224 } else { 225 fail(DL, DAG, "defined with too many args"); 226 InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT())); 227 } 228 } 229 230 if (IsVarArg || MF.getFunction()->hasStructRetAttr()) { 231 fail(DL, DAG, "functions with VarArgs or StructRet are not supported"); 232 } 233 234 return Chain; 235 } 236 237 const unsigned BPFTargetLowering::MaxArgs = 5; 238 239 SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 240 SmallVectorImpl<SDValue> &InVals) const { 241 SelectionDAG &DAG = CLI.DAG; 242 auto &Outs = CLI.Outs; 243 auto &OutVals = CLI.OutVals; 244 auto &Ins = CLI.Ins; 245 SDValue Chain = CLI.Chain; 246 SDValue Callee = CLI.Callee; 247 bool &IsTailCall = CLI.IsTailCall; 248 CallingConv::ID CallConv = CLI.CallConv; 249 bool IsVarArg = CLI.IsVarArg; 250 MachineFunction &MF = DAG.getMachineFunction(); 251 252 // BPF target does not support tail call optimization. 253 IsTailCall = false; 254 255 switch (CallConv) { 256 default: 257 report_fatal_error("Unsupported calling convention"); 258 case CallingConv::Fast: 259 case CallingConv::C: 260 break; 261 } 262 263 // Analyze operands of the call, assigning locations to each operand. 264 SmallVector<CCValAssign, 16> ArgLocs; 265 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 266 267 CCInfo.AnalyzeCallOperands(Outs, CC_BPF64); 268 269 unsigned NumBytes = CCInfo.getNextStackOffset(); 270 271 if (Outs.size() > MaxArgs) 272 fail(CLI.DL, DAG, "too many args to ", Callee); 273 274 for (auto &Arg : Outs) { 275 ISD::ArgFlagsTy Flags = Arg.Flags; 276 if (!Flags.isByVal()) 277 continue; 278 279 fail(CLI.DL, DAG, "pass by value not supported ", Callee); 280 } 281 282 auto PtrVT = getPointerTy(MF.getDataLayout()); 283 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL); 284 285 SmallVector<std::pair<unsigned, SDValue>, MaxArgs> RegsToPass; 286 287 // Walk arg assignments 288 for (unsigned i = 0, 289 e = std::min(static_cast<unsigned>(ArgLocs.size()), MaxArgs); 290 i != e; ++i) { 291 CCValAssign &VA = ArgLocs[i]; 292 SDValue Arg = OutVals[i]; 293 294 // Promote the value if needed. 295 switch (VA.getLocInfo()) { 296 default: 297 llvm_unreachable("Unknown loc info"); 298 case CCValAssign::Full: 299 break; 300 case CCValAssign::SExt: 301 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); 302 break; 303 case CCValAssign::ZExt: 304 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); 305 break; 306 case CCValAssign::AExt: 307 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg); 308 break; 309 } 310 311 // Push arguments into RegsToPass vector 312 if (VA.isRegLoc()) 313 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 314 else 315 llvm_unreachable("call arg pass bug"); 316 } 317 318 SDValue InFlag; 319 320 // Build a sequence of copy-to-reg nodes chained together with token chain and 321 // flag operands which copy the outgoing args into registers. The InFlag in 322 // necessary since all emitted instructions must be stuck together. 323 for (auto &Reg : RegsToPass) { 324 Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag); 325 InFlag = Chain.getValue(1); 326 } 327 328 // If the callee is a GlobalAddress node (quite common, every direct call is) 329 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 330 // Likewise ExternalSymbol -> TargetExternalSymbol. 331 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 332 auto GV = G->getGlobal(); 333 fail(CLI.DL, DAG, 334 "A call to global function '" + StringRef(GV->getName()) 335 + "' is not supported. " 336 + (GV->isDeclaration() ? 337 "Only calls to predefined BPF helpers are allowed." : 338 "Please use __attribute__((always_inline) to make sure" 339 " this function is inlined.")); 340 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, PtrVT, 341 G->getOffset(), 0); 342 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) { 343 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0); 344 fail(CLI.DL, DAG, Twine("A call to built-in function '" 345 + StringRef(E->getSymbol()) 346 + "' is not supported.")); 347 } 348 349 // Returns a chain & a flag for retval copy to use. 350 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 351 SmallVector<SDValue, 8> Ops; 352 Ops.push_back(Chain); 353 Ops.push_back(Callee); 354 355 // Add argument registers to the end of the list so that they are 356 // known live into the call. 357 for (auto &Reg : RegsToPass) 358 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); 359 360 if (InFlag.getNode()) 361 Ops.push_back(InFlag); 362 363 Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops); 364 InFlag = Chain.getValue(1); 365 366 // Create the CALLSEQ_END node. 367 Chain = DAG.getCALLSEQ_END( 368 Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), 369 DAG.getConstant(0, CLI.DL, PtrVT, true), InFlag, CLI.DL); 370 InFlag = Chain.getValue(1); 371 372 // Handle result values, copying them out of physregs into vregs that we 373 // return. 374 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG, 375 InVals); 376 } 377 378 SDValue 379 BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 380 bool IsVarArg, 381 const SmallVectorImpl<ISD::OutputArg> &Outs, 382 const SmallVectorImpl<SDValue> &OutVals, 383 const SDLoc &DL, SelectionDAG &DAG) const { 384 unsigned Opc = BPFISD::RET_FLAG; 385 386 // CCValAssign - represent the assignment of the return value to a location 387 SmallVector<CCValAssign, 16> RVLocs; 388 MachineFunction &MF = DAG.getMachineFunction(); 389 390 // CCState - Info about the registers and stack slot. 391 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 392 393 if (MF.getFunction()->getReturnType()->isAggregateType()) { 394 fail(DL, DAG, "only integer returns supported"); 395 return DAG.getNode(Opc, DL, MVT::Other, Chain); 396 } 397 398 // Analize return values. 399 CCInfo.AnalyzeReturn(Outs, RetCC_BPF64); 400 401 SDValue Flag; 402 SmallVector<SDValue, 4> RetOps(1, Chain); 403 404 // Copy the result values into the output registers. 405 for (unsigned i = 0; i != RVLocs.size(); ++i) { 406 CCValAssign &VA = RVLocs[i]; 407 assert(VA.isRegLoc() && "Can only return in registers!"); 408 409 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); 410 411 // Guarantee that all emitted copies are stuck together, 412 // avoiding something bad. 413 Flag = Chain.getValue(1); 414 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 415 } 416 417 RetOps[0] = Chain; // Update chain. 418 419 // Add the flag if we have it. 420 if (Flag.getNode()) 421 RetOps.push_back(Flag); 422 423 return DAG.getNode(Opc, DL, MVT::Other, RetOps); 424 } 425 426 SDValue BPFTargetLowering::LowerCallResult( 427 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 428 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 429 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 430 431 MachineFunction &MF = DAG.getMachineFunction(); 432 // Assign locations to each value returned by this call. 433 SmallVector<CCValAssign, 16> RVLocs; 434 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 435 436 if (Ins.size() >= 2) { 437 fail(DL, DAG, "only small returns supported"); 438 for (unsigned i = 0, e = Ins.size(); i != e; ++i) 439 InVals.push_back(DAG.getConstant(0, DL, Ins[i].VT)); 440 return DAG.getCopyFromReg(Chain, DL, 1, Ins[0].VT, InFlag).getValue(1); 441 } 442 443 CCInfo.AnalyzeCallResult(Ins, RetCC_BPF64); 444 445 // Copy all of the result registers out of their specified physreg. 446 for (auto &Val : RVLocs) { 447 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), 448 Val.getValVT(), InFlag).getValue(1); 449 InFlag = Chain.getValue(2); 450 InVals.push_back(Chain.getValue(0)); 451 } 452 453 return Chain; 454 } 455 456 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { 457 switch (CC) { 458 default: 459 break; 460 case ISD::SETULT: 461 case ISD::SETULE: 462 case ISD::SETLT: 463 case ISD::SETLE: 464 CC = ISD::getSetCCSwappedOperands(CC); 465 std::swap(LHS, RHS); 466 break; 467 } 468 } 469 470 SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 471 SDValue Chain = Op.getOperand(0); 472 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 473 SDValue LHS = Op.getOperand(2); 474 SDValue RHS = Op.getOperand(3); 475 SDValue Dest = Op.getOperand(4); 476 SDLoc DL(Op); 477 478 if (!getHasJmpExt()) 479 NegateCC(LHS, RHS, CC); 480 481 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS, 482 DAG.getConstant(CC, DL, MVT::i64), Dest); 483 } 484 485 SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 486 SDValue LHS = Op.getOperand(0); 487 SDValue RHS = Op.getOperand(1); 488 SDValue TrueV = Op.getOperand(2); 489 SDValue FalseV = Op.getOperand(3); 490 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 491 SDLoc DL(Op); 492 493 if (!getHasJmpExt()) 494 NegateCC(LHS, RHS, CC); 495 496 SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i64); 497 498 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 499 SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV}; 500 501 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops); 502 } 503 504 const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const { 505 switch ((BPFISD::NodeType)Opcode) { 506 case BPFISD::FIRST_NUMBER: 507 break; 508 case BPFISD::RET_FLAG: 509 return "BPFISD::RET_FLAG"; 510 case BPFISD::CALL: 511 return "BPFISD::CALL"; 512 case BPFISD::SELECT_CC: 513 return "BPFISD::SELECT_CC"; 514 case BPFISD::BR_CC: 515 return "BPFISD::BR_CC"; 516 case BPFISD::Wrapper: 517 return "BPFISD::Wrapper"; 518 } 519 return nullptr; 520 } 521 522 SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op, 523 SelectionDAG &DAG) const { 524 auto N = cast<GlobalAddressSDNode>(Op); 525 assert(N->getOffset() == 0 && "Invalid offset for global address"); 526 527 SDLoc DL(Op); 528 const GlobalValue *GV = N->getGlobal(); 529 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64); 530 531 return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA); 532 } 533 534 MachineBasicBlock * 535 BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 536 MachineBasicBlock *BB) const { 537 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); 538 DebugLoc DL = MI.getDebugLoc(); 539 bool isSelectOp = MI.getOpcode() == BPF::Select; 540 541 assert((isSelectOp || MI.getOpcode() == BPF::Select_Ri) && "Unexpected instr type to insert"); 542 543 // To "insert" a SELECT instruction, we actually have to insert the diamond 544 // control-flow pattern. The incoming instruction knows the destination vreg 545 // to set, the condition code register to branch on, the true/false values to 546 // select between, and a branch opcode to use. 547 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 548 MachineFunction::iterator I = ++BB->getIterator(); 549 550 // ThisMBB: 551 // ... 552 // TrueVal = ... 553 // jmp_XX r1, r2 goto Copy1MBB 554 // fallthrough --> Copy0MBB 555 MachineBasicBlock *ThisMBB = BB; 556 MachineFunction *F = BB->getParent(); 557 MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 558 MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 559 560 F->insert(I, Copy0MBB); 561 F->insert(I, Copy1MBB); 562 // Update machine-CFG edges by transferring all successors of the current 563 // block to the new block which will contain the Phi node for the select. 564 Copy1MBB->splice(Copy1MBB->begin(), BB, 565 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 566 Copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 567 // Next, add the true and fallthrough blocks as its successors. 568 BB->addSuccessor(Copy0MBB); 569 BB->addSuccessor(Copy1MBB); 570 571 // Insert Branch if Flag 572 unsigned LHS = MI.getOperand(1).getReg(); 573 int CC = MI.getOperand(3).getImm(); 574 int NewCC; 575 switch (CC) { 576 case ISD::SETGT: 577 NewCC = isSelectOp ? BPF::JSGT_rr : BPF::JSGT_ri; 578 break; 579 case ISD::SETUGT: 580 NewCC = isSelectOp ? BPF::JUGT_rr : BPF::JUGT_ri; 581 break; 582 case ISD::SETGE: 583 NewCC = isSelectOp ? BPF::JSGE_rr : BPF::JSGE_ri; 584 break; 585 case ISD::SETUGE: 586 NewCC = isSelectOp ? BPF::JUGE_rr : BPF::JUGE_ri; 587 break; 588 case ISD::SETEQ: 589 NewCC = isSelectOp ? BPF::JEQ_rr : BPF::JEQ_ri; 590 break; 591 case ISD::SETNE: 592 NewCC = isSelectOp ? BPF::JNE_rr : BPF::JNE_ri; 593 break; 594 case ISD::SETLT: 595 NewCC = isSelectOp ? BPF::JSLT_rr : BPF::JSLT_ri; 596 break; 597 case ISD::SETULT: 598 NewCC = isSelectOp ? BPF::JULT_rr : BPF::JULT_ri; 599 break; 600 case ISD::SETLE: 601 NewCC = isSelectOp ? BPF::JSLE_rr : BPF::JSLE_ri; 602 break; 603 case ISD::SETULE: 604 NewCC = isSelectOp ? BPF::JULE_rr : BPF::JULE_ri; 605 break; 606 default: 607 report_fatal_error("unimplemented select CondCode " + Twine(CC)); 608 } 609 if (isSelectOp) 610 BuildMI(BB, DL, TII.get(NewCC)) 611 .addReg(LHS) 612 .addReg(MI.getOperand(2).getReg()) 613 .addMBB(Copy1MBB); 614 else { 615 int64_t imm32 = MI.getOperand(2).getImm(); 616 // sanity check before we build J*_ri instruction. 617 assert (isInt<32>(imm32)); 618 BuildMI(BB, DL, TII.get(NewCC)) 619 .addReg(LHS) 620 .addImm(imm32) 621 .addMBB(Copy1MBB); 622 } 623 624 // Copy0MBB: 625 // %FalseValue = ... 626 // # fallthrough to Copy1MBB 627 BB = Copy0MBB; 628 629 // Update machine-CFG edges 630 BB->addSuccessor(Copy1MBB); 631 632 // Copy1MBB: 633 // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ] 634 // ... 635 BB = Copy1MBB; 636 BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg()) 637 .addReg(MI.getOperand(5).getReg()) 638 .addMBB(Copy0MBB) 639 .addReg(MI.getOperand(4).getReg()) 640 .addMBB(ThisMBB); 641 642 MI.eraseFromParent(); // The pseudo instruction is gone now. 643 return BB; 644 } 645