1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that BPF uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "BPFISelLowering.h" 16 #include "BPF.h" 17 #include "BPFSubtarget.h" 18 #include "BPFTargetMachine.h" 19 #include "llvm/CodeGen/CallingConvLower.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/SelectionDAGISel.h" 25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/IR/DiagnosticInfo.h" 28 #include "llvm/IR/DiagnosticPrinter.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/raw_ostream.h" 32 using namespace llvm; 33 34 #define DEBUG_TYPE "bpf-lower" 35 36 static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg) { 37 MachineFunction &MF = DAG.getMachineFunction(); 38 DAG.getContext()->diagnose( 39 DiagnosticInfoUnsupported(*MF.getFunction(), Msg, DL.getDebugLoc())); 40 } 41 42 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg, 43 SDValue Val) { 44 MachineFunction &MF = DAG.getMachineFunction(); 45 std::string Str; 46 raw_string_ostream OS(Str); 47 OS << Msg; 48 Val->print(OS); 49 OS.flush(); 50 DAG.getContext()->diagnose( 51 DiagnosticInfoUnsupported(*MF.getFunction(), Str, DL.getDebugLoc())); 52 } 53 54 BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM, 55 const BPFSubtarget &STI) 56 : TargetLowering(TM) { 57 58 // Set up the register classes. 59 addRegisterClass(MVT::i64, &BPF::GPRRegClass); 60 61 // Compute derived properties from the register classes 62 computeRegisterProperties(STI.getRegisterInfo()); 63 64 setStackPointerRegisterToSaveRestore(BPF::R11); 65 66 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 67 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 68 setOperationAction(ISD::BRIND, MVT::Other, Expand); 69 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 70 setOperationAction(ISD::SETCC, MVT::i64, Expand); 71 setOperationAction(ISD::SELECT, MVT::i64, Expand); 72 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 73 74 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 75 76 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 77 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 78 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 79 80 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 81 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 82 setOperationAction(ISD::SREM, MVT::i64, Expand); 83 setOperationAction(ISD::UREM, MVT::i64, Expand); 84 85 setOperationAction(ISD::MULHU, MVT::i64, Expand); 86 setOperationAction(ISD::MULHS, MVT::i64, Expand); 87 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 88 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 89 90 setOperationAction(ISD::ADDC, MVT::i64, Expand); 91 setOperationAction(ISD::ADDE, MVT::i64, Expand); 92 setOperationAction(ISD::SUBC, MVT::i64, Expand); 93 setOperationAction(ISD::SUBE, MVT::i64, Expand); 94 95 setOperationAction(ISD::ROTR, MVT::i64, Expand); 96 setOperationAction(ISD::ROTL, MVT::i64, Expand); 97 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); 98 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); 99 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); 100 101 setOperationAction(ISD::CTTZ, MVT::i64, Custom); 102 setOperationAction(ISD::CTLZ, MVT::i64, Custom); 103 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom); 104 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 105 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 106 107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); 111 112 // Extended load operations for i1 types must be promoted 113 for (MVT VT : MVT::integer_valuetypes()) { 114 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 115 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 116 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 117 118 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 119 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); 120 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); 121 } 122 123 setBooleanContents(ZeroOrOneBooleanContent); 124 125 // Function alignments (log2) 126 setMinFunctionAlignment(3); 127 setPrefFunctionAlignment(3); 128 129 // inline memcpy() for kernel to see explicit copy 130 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 128; 131 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 128; 132 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 128; 133 } 134 135 bool BPFTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 136 return false; 137 } 138 139 SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 140 switch (Op.getOpcode()) { 141 case ISD::BR_CC: 142 return LowerBR_CC(Op, DAG); 143 case ISD::GlobalAddress: 144 return LowerGlobalAddress(Op, DAG); 145 case ISD::SELECT_CC: 146 return LowerSELECT_CC(Op, DAG); 147 default: 148 llvm_unreachable("unimplemented operand"); 149 } 150 } 151 152 // Calling Convention Implementation 153 #include "BPFGenCallingConv.inc" 154 155 SDValue BPFTargetLowering::LowerFormalArguments( 156 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 157 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 158 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 159 switch (CallConv) { 160 default: 161 llvm_unreachable("Unsupported calling convention"); 162 case CallingConv::C: 163 case CallingConv::Fast: 164 break; 165 } 166 167 MachineFunction &MF = DAG.getMachineFunction(); 168 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 169 170 // Assign locations to all of the incoming arguments. 171 SmallVector<CCValAssign, 16> ArgLocs; 172 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 173 CCInfo.AnalyzeFormalArguments(Ins, CC_BPF64); 174 175 for (auto &VA : ArgLocs) { 176 if (VA.isRegLoc()) { 177 // Arguments passed in registers 178 EVT RegVT = VA.getLocVT(); 179 switch (RegVT.getSimpleVT().SimpleTy) { 180 default: { 181 errs() << "LowerFormalArguments Unhandled argument type: " 182 << RegVT.getEVTString() << '\n'; 183 llvm_unreachable(0); 184 } 185 case MVT::i64: 186 unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass); 187 RegInfo.addLiveIn(VA.getLocReg(), VReg); 188 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); 189 190 // If this is an 8/16/32-bit value, it is really passed promoted to 64 191 // bits. Insert an assert[sz]ext to capture this, then truncate to the 192 // right size. 193 if (VA.getLocInfo() == CCValAssign::SExt) 194 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, 195 DAG.getValueType(VA.getValVT())); 196 else if (VA.getLocInfo() == CCValAssign::ZExt) 197 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, 198 DAG.getValueType(VA.getValVT())); 199 200 if (VA.getLocInfo() != CCValAssign::Full) 201 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); 202 203 InVals.push_back(ArgValue); 204 } 205 } else { 206 fail(DL, DAG, "defined with too many args"); 207 InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT())); 208 } 209 } 210 211 if (IsVarArg || MF.getFunction()->hasStructRetAttr()) { 212 fail(DL, DAG, "functions with VarArgs or StructRet are not supported"); 213 } 214 215 return Chain; 216 } 217 218 const unsigned BPFTargetLowering::MaxArgs = 5; 219 220 SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 221 SmallVectorImpl<SDValue> &InVals) const { 222 SelectionDAG &DAG = CLI.DAG; 223 auto &Outs = CLI.Outs; 224 auto &OutVals = CLI.OutVals; 225 auto &Ins = CLI.Ins; 226 SDValue Chain = CLI.Chain; 227 SDValue Callee = CLI.Callee; 228 bool &IsTailCall = CLI.IsTailCall; 229 CallingConv::ID CallConv = CLI.CallConv; 230 bool IsVarArg = CLI.IsVarArg; 231 MachineFunction &MF = DAG.getMachineFunction(); 232 233 // BPF target does not support tail call optimization. 234 IsTailCall = false; 235 236 switch (CallConv) { 237 default: 238 report_fatal_error("Unsupported calling convention"); 239 case CallingConv::Fast: 240 case CallingConv::C: 241 break; 242 } 243 244 // Analyze operands of the call, assigning locations to each operand. 245 SmallVector<CCValAssign, 16> ArgLocs; 246 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 247 248 CCInfo.AnalyzeCallOperands(Outs, CC_BPF64); 249 250 unsigned NumBytes = CCInfo.getNextStackOffset(); 251 252 if (Outs.size() > MaxArgs) 253 fail(CLI.DL, DAG, "too many args to ", Callee); 254 255 for (auto &Arg : Outs) { 256 ISD::ArgFlagsTy Flags = Arg.Flags; 257 if (!Flags.isByVal()) 258 continue; 259 260 fail(CLI.DL, DAG, "pass by value not supported ", Callee); 261 } 262 263 auto PtrVT = getPointerTy(MF.getDataLayout()); 264 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL); 265 266 SmallVector<std::pair<unsigned, SDValue>, MaxArgs> RegsToPass; 267 268 // Walk arg assignments 269 for (unsigned i = 0, 270 e = std::min(static_cast<unsigned>(ArgLocs.size()), MaxArgs); 271 i != e; ++i) { 272 CCValAssign &VA = ArgLocs[i]; 273 SDValue Arg = OutVals[i]; 274 275 // Promote the value if needed. 276 switch (VA.getLocInfo()) { 277 default: 278 llvm_unreachable("Unknown loc info"); 279 case CCValAssign::Full: 280 break; 281 case CCValAssign::SExt: 282 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); 283 break; 284 case CCValAssign::ZExt: 285 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); 286 break; 287 case CCValAssign::AExt: 288 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg); 289 break; 290 } 291 292 // Push arguments into RegsToPass vector 293 if (VA.isRegLoc()) 294 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 295 else 296 llvm_unreachable("call arg pass bug"); 297 } 298 299 SDValue InFlag; 300 301 // Build a sequence of copy-to-reg nodes chained together with token chain and 302 // flag operands which copy the outgoing args into registers. The InFlag in 303 // necessary since all emitted instructions must be stuck together. 304 for (auto &Reg : RegsToPass) { 305 Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag); 306 InFlag = Chain.getValue(1); 307 } 308 309 // If the callee is a GlobalAddress node (quite common, every direct call is) 310 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 311 // Likewise ExternalSymbol -> TargetExternalSymbol. 312 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 313 auto GV = G->getGlobal(); 314 fail(CLI.DL, DAG, 315 "A call to global function '" + StringRef(GV->getName()) 316 + "' is not supported. " 317 + (GV->isDeclaration() ? 318 "Only calls to predefined BPF helpers are allowed." : 319 "Please use __attribute__((always_inline) to make sure" 320 " this function is inlined.")); 321 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, PtrVT, 322 G->getOffset(), 0); 323 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) { 324 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0); 325 fail(CLI.DL, DAG, Twine("A call to built-in function '" 326 + StringRef(E->getSymbol()) 327 + "' is not supported.")); 328 } 329 330 // Returns a chain & a flag for retval copy to use. 331 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 332 SmallVector<SDValue, 8> Ops; 333 Ops.push_back(Chain); 334 Ops.push_back(Callee); 335 336 // Add argument registers to the end of the list so that they are 337 // known live into the call. 338 for (auto &Reg : RegsToPass) 339 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); 340 341 if (InFlag.getNode()) 342 Ops.push_back(InFlag); 343 344 Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops); 345 InFlag = Chain.getValue(1); 346 347 // Create the CALLSEQ_END node. 348 Chain = DAG.getCALLSEQ_END( 349 Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), 350 DAG.getConstant(0, CLI.DL, PtrVT, true), InFlag, CLI.DL); 351 InFlag = Chain.getValue(1); 352 353 // Handle result values, copying them out of physregs into vregs that we 354 // return. 355 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG, 356 InVals); 357 } 358 359 SDValue 360 BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 361 bool IsVarArg, 362 const SmallVectorImpl<ISD::OutputArg> &Outs, 363 const SmallVectorImpl<SDValue> &OutVals, 364 const SDLoc &DL, SelectionDAG &DAG) const { 365 unsigned Opc = BPFISD::RET_FLAG; 366 367 // CCValAssign - represent the assignment of the return value to a location 368 SmallVector<CCValAssign, 16> RVLocs; 369 MachineFunction &MF = DAG.getMachineFunction(); 370 371 // CCState - Info about the registers and stack slot. 372 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 373 374 if (MF.getFunction()->getReturnType()->isAggregateType()) { 375 fail(DL, DAG, "only integer returns supported"); 376 return DAG.getNode(Opc, DL, MVT::Other, Chain); 377 } 378 379 // Analize return values. 380 CCInfo.AnalyzeReturn(Outs, RetCC_BPF64); 381 382 SDValue Flag; 383 SmallVector<SDValue, 4> RetOps(1, Chain); 384 385 // Copy the result values into the output registers. 386 for (unsigned i = 0; i != RVLocs.size(); ++i) { 387 CCValAssign &VA = RVLocs[i]; 388 assert(VA.isRegLoc() && "Can only return in registers!"); 389 390 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); 391 392 // Guarantee that all emitted copies are stuck together, 393 // avoiding something bad. 394 Flag = Chain.getValue(1); 395 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 396 } 397 398 RetOps[0] = Chain; // Update chain. 399 400 // Add the flag if we have it. 401 if (Flag.getNode()) 402 RetOps.push_back(Flag); 403 404 return DAG.getNode(Opc, DL, MVT::Other, RetOps); 405 } 406 407 SDValue BPFTargetLowering::LowerCallResult( 408 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 409 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 410 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 411 412 MachineFunction &MF = DAG.getMachineFunction(); 413 // Assign locations to each value returned by this call. 414 SmallVector<CCValAssign, 16> RVLocs; 415 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 416 417 if (Ins.size() >= 2) { 418 fail(DL, DAG, "only small returns supported"); 419 for (unsigned i = 0, e = Ins.size(); i != e; ++i) 420 InVals.push_back(DAG.getConstant(0, DL, Ins[i].VT)); 421 return DAG.getCopyFromReg(Chain, DL, 1, Ins[0].VT, InFlag).getValue(1); 422 } 423 424 CCInfo.AnalyzeCallResult(Ins, RetCC_BPF64); 425 426 // Copy all of the result registers out of their specified physreg. 427 for (auto &Val : RVLocs) { 428 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), 429 Val.getValVT(), InFlag).getValue(1); 430 InFlag = Chain.getValue(2); 431 InVals.push_back(Chain.getValue(0)); 432 } 433 434 return Chain; 435 } 436 437 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { 438 switch (CC) { 439 default: 440 break; 441 case ISD::SETULT: 442 case ISD::SETULE: 443 case ISD::SETLT: 444 case ISD::SETLE: 445 CC = ISD::getSetCCSwappedOperands(CC); 446 std::swap(LHS, RHS); 447 break; 448 } 449 } 450 451 SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 452 SDValue Chain = Op.getOperand(0); 453 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 454 SDValue LHS = Op.getOperand(2); 455 SDValue RHS = Op.getOperand(3); 456 SDValue Dest = Op.getOperand(4); 457 SDLoc DL(Op); 458 459 NegateCC(LHS, RHS, CC); 460 461 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS, 462 DAG.getConstant(CC, DL, MVT::i64), Dest); 463 } 464 465 SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 466 SDValue LHS = Op.getOperand(0); 467 SDValue RHS = Op.getOperand(1); 468 SDValue TrueV = Op.getOperand(2); 469 SDValue FalseV = Op.getOperand(3); 470 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 471 SDLoc DL(Op); 472 473 NegateCC(LHS, RHS, CC); 474 475 SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i64); 476 477 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 478 SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV}; 479 480 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops); 481 } 482 483 const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const { 484 switch ((BPFISD::NodeType)Opcode) { 485 case BPFISD::FIRST_NUMBER: 486 break; 487 case BPFISD::RET_FLAG: 488 return "BPFISD::RET_FLAG"; 489 case BPFISD::CALL: 490 return "BPFISD::CALL"; 491 case BPFISD::SELECT_CC: 492 return "BPFISD::SELECT_CC"; 493 case BPFISD::BR_CC: 494 return "BPFISD::BR_CC"; 495 case BPFISD::Wrapper: 496 return "BPFISD::Wrapper"; 497 } 498 return nullptr; 499 } 500 501 SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op, 502 SelectionDAG &DAG) const { 503 auto N = cast<GlobalAddressSDNode>(Op); 504 assert(N->getOffset() == 0 && "Invalid offset for global address"); 505 506 SDLoc DL(Op); 507 const GlobalValue *GV = N->getGlobal(); 508 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64); 509 510 return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA); 511 } 512 513 MachineBasicBlock * 514 BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 515 MachineBasicBlock *BB) const { 516 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); 517 DebugLoc DL = MI.getDebugLoc(); 518 519 assert(MI.getOpcode() == BPF::Select && "Unexpected instr type to insert"); 520 521 // To "insert" a SELECT instruction, we actually have to insert the diamond 522 // control-flow pattern. The incoming instruction knows the destination vreg 523 // to set, the condition code register to branch on, the true/false values to 524 // select between, and a branch opcode to use. 525 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 526 MachineFunction::iterator I = ++BB->getIterator(); 527 528 // ThisMBB: 529 // ... 530 // TrueVal = ... 531 // jmp_XX r1, r2 goto Copy1MBB 532 // fallthrough --> Copy0MBB 533 MachineBasicBlock *ThisMBB = BB; 534 MachineFunction *F = BB->getParent(); 535 MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 536 MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 537 538 F->insert(I, Copy0MBB); 539 F->insert(I, Copy1MBB); 540 // Update machine-CFG edges by transferring all successors of the current 541 // block to the new block which will contain the Phi node for the select. 542 Copy1MBB->splice(Copy1MBB->begin(), BB, 543 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 544 Copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 545 // Next, add the true and fallthrough blocks as its successors. 546 BB->addSuccessor(Copy0MBB); 547 BB->addSuccessor(Copy1MBB); 548 549 // Insert Branch if Flag 550 unsigned LHS = MI.getOperand(1).getReg(); 551 unsigned RHS = MI.getOperand(2).getReg(); 552 int CC = MI.getOperand(3).getImm(); 553 switch (CC) { 554 case ISD::SETGT: 555 BuildMI(BB, DL, TII.get(BPF::JSGT_rr)) 556 .addReg(LHS) 557 .addReg(RHS) 558 .addMBB(Copy1MBB); 559 break; 560 case ISD::SETUGT: 561 BuildMI(BB, DL, TII.get(BPF::JUGT_rr)) 562 .addReg(LHS) 563 .addReg(RHS) 564 .addMBB(Copy1MBB); 565 break; 566 case ISD::SETGE: 567 BuildMI(BB, DL, TII.get(BPF::JSGE_rr)) 568 .addReg(LHS) 569 .addReg(RHS) 570 .addMBB(Copy1MBB); 571 break; 572 case ISD::SETUGE: 573 BuildMI(BB, DL, TII.get(BPF::JUGE_rr)) 574 .addReg(LHS) 575 .addReg(RHS) 576 .addMBB(Copy1MBB); 577 break; 578 case ISD::SETEQ: 579 BuildMI(BB, DL, TII.get(BPF::JEQ_rr)) 580 .addReg(LHS) 581 .addReg(RHS) 582 .addMBB(Copy1MBB); 583 break; 584 case ISD::SETNE: 585 BuildMI(BB, DL, TII.get(BPF::JNE_rr)) 586 .addReg(LHS) 587 .addReg(RHS) 588 .addMBB(Copy1MBB); 589 break; 590 default: 591 report_fatal_error("unimplemented select CondCode " + Twine(CC)); 592 } 593 594 // Copy0MBB: 595 // %FalseValue = ... 596 // # fallthrough to Copy1MBB 597 BB = Copy0MBB; 598 599 // Update machine-CFG edges 600 BB->addSuccessor(Copy1MBB); 601 602 // Copy1MBB: 603 // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ] 604 // ... 605 BB = Copy1MBB; 606 BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg()) 607 .addReg(MI.getOperand(5).getReg()) 608 .addMBB(Copy0MBB) 609 .addReg(MI.getOperand(4).getReg()) 610 .addMBB(ThisMBB); 611 612 MI.eraseFromParent(); // The pseudo instruction is gone now. 613 return BB; 614 } 615