1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that BPF uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "BPFISelLowering.h" 16 #include "BPF.h" 17 #include "BPFSubtarget.h" 18 #include "BPFTargetMachine.h" 19 #include "llvm/CodeGen/CallingConvLower.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/SelectionDAGISel.h" 25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/IR/DiagnosticInfo.h" 28 #include "llvm/IR/DiagnosticPrinter.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/raw_ostream.h" 32 using namespace llvm; 33 34 #define DEBUG_TYPE "bpf-lower" 35 36 static void fail(SDLoc DL, SelectionDAG &DAG, const char *Msg) { 37 MachineFunction &MF = DAG.getMachineFunction(); 38 DAG.getContext()->diagnose( 39 DiagnosticInfoUnsupported(*MF.getFunction(), Msg, DL.getDebugLoc())); 40 } 41 42 static void fail(SDLoc DL, SelectionDAG &DAG, const char *Msg, SDValue Val) { 43 MachineFunction &MF = DAG.getMachineFunction(); 44 std::string Str; 45 raw_string_ostream OS(Str); 46 OS << Msg; 47 Val->print(OS); 48 OS.flush(); 49 DAG.getContext()->diagnose( 50 DiagnosticInfoUnsupported(*MF.getFunction(), Str, DL.getDebugLoc())); 51 } 52 53 BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM, 54 const BPFSubtarget &STI) 55 : TargetLowering(TM) { 56 57 // Set up the register classes. 58 addRegisterClass(MVT::i64, &BPF::GPRRegClass); 59 60 // Compute derived properties from the register classes 61 computeRegisterProperties(STI.getRegisterInfo()); 62 63 setStackPointerRegisterToSaveRestore(BPF::R11); 64 65 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 66 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 67 setOperationAction(ISD::BRIND, MVT::Other, Expand); 68 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 69 setOperationAction(ISD::SETCC, MVT::i64, Expand); 70 setOperationAction(ISD::SELECT, MVT::i64, Expand); 71 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 72 73 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 74 75 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 76 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 77 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 78 79 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 80 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 81 setOperationAction(ISD::SREM, MVT::i64, Expand); 82 setOperationAction(ISD::UREM, MVT::i64, Expand); 83 84 setOperationAction(ISD::MULHU, MVT::i64, Expand); 85 setOperationAction(ISD::MULHS, MVT::i64, Expand); 86 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 87 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 88 89 setOperationAction(ISD::ADDC, MVT::i64, Expand); 90 setOperationAction(ISD::ADDE, MVT::i64, Expand); 91 setOperationAction(ISD::SUBC, MVT::i64, Expand); 92 setOperationAction(ISD::SUBE, MVT::i64, Expand); 93 94 setOperationAction(ISD::ROTR, MVT::i64, Expand); 95 setOperationAction(ISD::ROTL, MVT::i64, Expand); 96 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); 97 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); 98 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); 99 100 setOperationAction(ISD::CTTZ, MVT::i64, Custom); 101 setOperationAction(ISD::CTLZ, MVT::i64, Custom); 102 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom); 103 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 104 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 105 106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); 110 111 // Extended load operations for i1 types must be promoted 112 for (MVT VT : MVT::integer_valuetypes()) { 113 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 114 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 115 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 116 117 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 118 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); 119 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); 120 } 121 122 setBooleanContents(ZeroOrOneBooleanContent); 123 124 // Function alignments (log2) 125 setMinFunctionAlignment(3); 126 setPrefFunctionAlignment(3); 127 128 // inline memcpy() for kernel to see explicit copy 129 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 128; 130 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 128; 131 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 128; 132 } 133 134 SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 135 switch (Op.getOpcode()) { 136 case ISD::BR_CC: 137 return LowerBR_CC(Op, DAG); 138 case ISD::GlobalAddress: 139 return LowerGlobalAddress(Op, DAG); 140 case ISD::SELECT_CC: 141 return LowerSELECT_CC(Op, DAG); 142 default: 143 llvm_unreachable("unimplemented operand"); 144 } 145 } 146 147 // Calling Convention Implementation 148 #include "BPFGenCallingConv.inc" 149 150 SDValue BPFTargetLowering::LowerFormalArguments( 151 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 152 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, 153 SmallVectorImpl<SDValue> &InVals) const { 154 switch (CallConv) { 155 default: 156 llvm_unreachable("Unsupported calling convention"); 157 case CallingConv::C: 158 case CallingConv::Fast: 159 break; 160 } 161 162 MachineFunction &MF = DAG.getMachineFunction(); 163 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 164 165 // Assign locations to all of the incoming arguments. 166 SmallVector<CCValAssign, 16> ArgLocs; 167 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 168 CCInfo.AnalyzeFormalArguments(Ins, CC_BPF64); 169 170 for (auto &VA : ArgLocs) { 171 if (VA.isRegLoc()) { 172 // Arguments passed in registers 173 EVT RegVT = VA.getLocVT(); 174 switch (RegVT.getSimpleVT().SimpleTy) { 175 default: { 176 errs() << "LowerFormalArguments Unhandled argument type: " 177 << RegVT.getEVTString() << '\n'; 178 llvm_unreachable(0); 179 } 180 case MVT::i64: 181 unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass); 182 RegInfo.addLiveIn(VA.getLocReg(), VReg); 183 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); 184 185 // If this is an 8/16/32-bit value, it is really passed promoted to 64 186 // bits. Insert an assert[sz]ext to capture this, then truncate to the 187 // right size. 188 if (VA.getLocInfo() == CCValAssign::SExt) 189 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, 190 DAG.getValueType(VA.getValVT())); 191 else if (VA.getLocInfo() == CCValAssign::ZExt) 192 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, 193 DAG.getValueType(VA.getValVT())); 194 195 if (VA.getLocInfo() != CCValAssign::Full) 196 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); 197 198 InVals.push_back(ArgValue); 199 } 200 } else { 201 fail(DL, DAG, "defined with too many args"); 202 } 203 } 204 205 if (IsVarArg || MF.getFunction()->hasStructRetAttr()) { 206 fail(DL, DAG, "functions with VarArgs or StructRet are not supported"); 207 } 208 209 return Chain; 210 } 211 212 SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 213 SmallVectorImpl<SDValue> &InVals) const { 214 SelectionDAG &DAG = CLI.DAG; 215 auto &Outs = CLI.Outs; 216 auto &OutVals = CLI.OutVals; 217 auto &Ins = CLI.Ins; 218 SDValue Chain = CLI.Chain; 219 SDValue Callee = CLI.Callee; 220 bool &IsTailCall = CLI.IsTailCall; 221 CallingConv::ID CallConv = CLI.CallConv; 222 bool IsVarArg = CLI.IsVarArg; 223 MachineFunction &MF = DAG.getMachineFunction(); 224 225 // BPF target does not support tail call optimization. 226 IsTailCall = false; 227 228 switch (CallConv) { 229 default: 230 report_fatal_error("Unsupported calling convention"); 231 case CallingConv::Fast: 232 case CallingConv::C: 233 break; 234 } 235 236 // Analyze operands of the call, assigning locations to each operand. 237 SmallVector<CCValAssign, 16> ArgLocs; 238 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 239 240 CCInfo.AnalyzeCallOperands(Outs, CC_BPF64); 241 242 unsigned NumBytes = CCInfo.getNextStackOffset(); 243 244 if (Outs.size() >= 6) { 245 fail(CLI.DL, DAG, "too many args to ", Callee); 246 } 247 248 for (auto &Arg : Outs) { 249 ISD::ArgFlagsTy Flags = Arg.Flags; 250 if (!Flags.isByVal()) 251 continue; 252 253 fail(CLI.DL, DAG, "pass by value not supported ", Callee); 254 } 255 256 auto PtrVT = getPointerTy(MF.getDataLayout()); 257 Chain = DAG.getCALLSEQ_START( 258 Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), CLI.DL); 259 260 SmallVector<std::pair<unsigned, SDValue>, 5> RegsToPass; 261 262 // Walk arg assignments 263 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 264 CCValAssign &VA = ArgLocs[i]; 265 SDValue Arg = OutVals[i]; 266 267 // Promote the value if needed. 268 switch (VA.getLocInfo()) { 269 default: 270 llvm_unreachable("Unknown loc info"); 271 case CCValAssign::Full: 272 break; 273 case CCValAssign::SExt: 274 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); 275 break; 276 case CCValAssign::ZExt: 277 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); 278 break; 279 case CCValAssign::AExt: 280 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg); 281 break; 282 } 283 284 // Push arguments into RegsToPass vector 285 if (VA.isRegLoc()) 286 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 287 else 288 llvm_unreachable("call arg pass bug"); 289 } 290 291 SDValue InFlag; 292 293 // Build a sequence of copy-to-reg nodes chained together with token chain and 294 // flag operands which copy the outgoing args into registers. The InFlag in 295 // necessary since all emitted instructions must be stuck together. 296 for (auto &Reg : RegsToPass) { 297 Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag); 298 InFlag = Chain.getValue(1); 299 } 300 301 // If the callee is a GlobalAddress node (quite common, every direct call is) 302 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 303 // Likewise ExternalSymbol -> TargetExternalSymbol. 304 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 305 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, PtrVT, 306 G->getOffset(), 0); 307 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 308 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0); 309 310 // Returns a chain & a flag for retval copy to use. 311 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 312 SmallVector<SDValue, 8> Ops; 313 Ops.push_back(Chain); 314 Ops.push_back(Callee); 315 316 // Add argument registers to the end of the list so that they are 317 // known live into the call. 318 for (auto &Reg : RegsToPass) 319 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); 320 321 if (InFlag.getNode()) 322 Ops.push_back(InFlag); 323 324 Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops); 325 InFlag = Chain.getValue(1); 326 327 // Create the CALLSEQ_END node. 328 Chain = DAG.getCALLSEQ_END( 329 Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), 330 DAG.getConstant(0, CLI.DL, PtrVT, true), InFlag, CLI.DL); 331 InFlag = Chain.getValue(1); 332 333 // Handle result values, copying them out of physregs into vregs that we 334 // return. 335 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG, 336 InVals); 337 } 338 339 SDValue 340 BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 341 bool IsVarArg, 342 const SmallVectorImpl<ISD::OutputArg> &Outs, 343 const SmallVectorImpl<SDValue> &OutVals, 344 SDLoc DL, SelectionDAG &DAG) const { 345 346 // CCValAssign - represent the assignment of the return value to a location 347 SmallVector<CCValAssign, 16> RVLocs; 348 MachineFunction &MF = DAG.getMachineFunction(); 349 350 // CCState - Info about the registers and stack slot. 351 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 352 353 if (MF.getFunction()->getReturnType()->isAggregateType()) { 354 fail(DL, DAG, "only integer returns supported"); 355 } 356 357 // Analize return values. 358 CCInfo.AnalyzeReturn(Outs, RetCC_BPF64); 359 360 SDValue Flag; 361 SmallVector<SDValue, 4> RetOps(1, Chain); 362 363 // Copy the result values into the output registers. 364 for (unsigned i = 0; i != RVLocs.size(); ++i) { 365 CCValAssign &VA = RVLocs[i]; 366 assert(VA.isRegLoc() && "Can only return in registers!"); 367 368 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); 369 370 // Guarantee that all emitted copies are stuck together, 371 // avoiding something bad. 372 Flag = Chain.getValue(1); 373 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 374 } 375 376 unsigned Opc = BPFISD::RET_FLAG; 377 RetOps[0] = Chain; // Update chain. 378 379 // Add the flag if we have it. 380 if (Flag.getNode()) 381 RetOps.push_back(Flag); 382 383 return DAG.getNode(Opc, DL, MVT::Other, RetOps); 384 } 385 386 SDValue BPFTargetLowering::LowerCallResult( 387 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 388 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, 389 SmallVectorImpl<SDValue> &InVals) const { 390 391 MachineFunction &MF = DAG.getMachineFunction(); 392 // Assign locations to each value returned by this call. 393 SmallVector<CCValAssign, 16> RVLocs; 394 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 395 396 if (Ins.size() >= 2) { 397 fail(DL, DAG, "only small returns supported"); 398 } 399 400 CCInfo.AnalyzeCallResult(Ins, RetCC_BPF64); 401 402 // Copy all of the result registers out of their specified physreg. 403 for (auto &Val : RVLocs) { 404 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), 405 Val.getValVT(), InFlag).getValue(1); 406 InFlag = Chain.getValue(2); 407 InVals.push_back(Chain.getValue(0)); 408 } 409 410 return Chain; 411 } 412 413 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { 414 switch (CC) { 415 default: 416 break; 417 case ISD::SETULT: 418 case ISD::SETULE: 419 case ISD::SETLT: 420 case ISD::SETLE: 421 CC = ISD::getSetCCSwappedOperands(CC); 422 std::swap(LHS, RHS); 423 break; 424 } 425 } 426 427 SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 428 SDValue Chain = Op.getOperand(0); 429 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 430 SDValue LHS = Op.getOperand(2); 431 SDValue RHS = Op.getOperand(3); 432 SDValue Dest = Op.getOperand(4); 433 SDLoc DL(Op); 434 435 NegateCC(LHS, RHS, CC); 436 437 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS, 438 DAG.getConstant(CC, DL, MVT::i64), Dest); 439 } 440 441 SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 442 SDValue LHS = Op.getOperand(0); 443 SDValue RHS = Op.getOperand(1); 444 SDValue TrueV = Op.getOperand(2); 445 SDValue FalseV = Op.getOperand(3); 446 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 447 SDLoc DL(Op); 448 449 NegateCC(LHS, RHS, CC); 450 451 SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i64); 452 453 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 454 SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV}; 455 456 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops); 457 } 458 459 const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const { 460 switch ((BPFISD::NodeType)Opcode) { 461 case BPFISD::FIRST_NUMBER: 462 break; 463 case BPFISD::RET_FLAG: 464 return "BPFISD::RET_FLAG"; 465 case BPFISD::CALL: 466 return "BPFISD::CALL"; 467 case BPFISD::SELECT_CC: 468 return "BPFISD::SELECT_CC"; 469 case BPFISD::BR_CC: 470 return "BPFISD::BR_CC"; 471 case BPFISD::Wrapper: 472 return "BPFISD::Wrapper"; 473 } 474 return nullptr; 475 } 476 477 SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op, 478 SelectionDAG &DAG) const { 479 SDLoc DL(Op); 480 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 481 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64); 482 483 return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA); 484 } 485 486 MachineBasicBlock * 487 BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 488 MachineBasicBlock *BB) const { 489 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); 490 DebugLoc DL = MI->getDebugLoc(); 491 492 assert(MI->getOpcode() == BPF::Select && "Unexpected instr type to insert"); 493 494 // To "insert" a SELECT instruction, we actually have to insert the diamond 495 // control-flow pattern. The incoming instruction knows the destination vreg 496 // to set, the condition code register to branch on, the true/false values to 497 // select between, and a branch opcode to use. 498 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 499 MachineFunction::iterator I = ++BB->getIterator(); 500 501 // ThisMBB: 502 // ... 503 // TrueVal = ... 504 // jmp_XX r1, r2 goto Copy1MBB 505 // fallthrough --> Copy0MBB 506 MachineBasicBlock *ThisMBB = BB; 507 MachineFunction *F = BB->getParent(); 508 MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 509 MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 510 511 F->insert(I, Copy0MBB); 512 F->insert(I, Copy1MBB); 513 // Update machine-CFG edges by transferring all successors of the current 514 // block to the new block which will contain the Phi node for the select. 515 Copy1MBB->splice(Copy1MBB->begin(), BB, 516 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 517 Copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 518 // Next, add the true and fallthrough blocks as its successors. 519 BB->addSuccessor(Copy0MBB); 520 BB->addSuccessor(Copy1MBB); 521 522 // Insert Branch if Flag 523 unsigned LHS = MI->getOperand(1).getReg(); 524 unsigned RHS = MI->getOperand(2).getReg(); 525 int CC = MI->getOperand(3).getImm(); 526 switch (CC) { 527 case ISD::SETGT: 528 BuildMI(BB, DL, TII.get(BPF::JSGT_rr)) 529 .addReg(LHS) 530 .addReg(RHS) 531 .addMBB(Copy1MBB); 532 break; 533 case ISD::SETUGT: 534 BuildMI(BB, DL, TII.get(BPF::JUGT_rr)) 535 .addReg(LHS) 536 .addReg(RHS) 537 .addMBB(Copy1MBB); 538 break; 539 case ISD::SETGE: 540 BuildMI(BB, DL, TII.get(BPF::JSGE_rr)) 541 .addReg(LHS) 542 .addReg(RHS) 543 .addMBB(Copy1MBB); 544 break; 545 case ISD::SETUGE: 546 BuildMI(BB, DL, TII.get(BPF::JUGE_rr)) 547 .addReg(LHS) 548 .addReg(RHS) 549 .addMBB(Copy1MBB); 550 break; 551 case ISD::SETEQ: 552 BuildMI(BB, DL, TII.get(BPF::JEQ_rr)) 553 .addReg(LHS) 554 .addReg(RHS) 555 .addMBB(Copy1MBB); 556 break; 557 case ISD::SETNE: 558 BuildMI(BB, DL, TII.get(BPF::JNE_rr)) 559 .addReg(LHS) 560 .addReg(RHS) 561 .addMBB(Copy1MBB); 562 break; 563 default: 564 report_fatal_error("unimplemented select CondCode " + Twine(CC)); 565 } 566 567 // Copy0MBB: 568 // %FalseValue = ... 569 // # fallthrough to Copy1MBB 570 BB = Copy0MBB; 571 572 // Update machine-CFG edges 573 BB->addSuccessor(Copy1MBB); 574 575 // Copy1MBB: 576 // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ] 577 // ... 578 BB = Copy1MBB; 579 BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI->getOperand(0).getReg()) 580 .addReg(MI->getOperand(5).getReg()) 581 .addMBB(Copy0MBB) 582 .addReg(MI->getOperand(4).getReg()) 583 .addMBB(ThisMBB); 584 585 MI->eraseFromParent(); // The pseudo instruction is gone now. 586 return BB; 587 } 588