1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation  ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that BPF uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "BPFISelLowering.h"
16 #include "BPF.h"
17 #include "BPFSubtarget.h"
18 #include "BPFTargetMachine.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/IR/DiagnosticInfo.h"
28 #include "llvm/IR/DiagnosticPrinter.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "bpf-lower"
35 
36 static void fail(SDLoc DL, SelectionDAG &DAG, const char *Msg) {
37   MachineFunction &MF = DAG.getMachineFunction();
38   DAG.getContext()->diagnose(
39       DiagnosticInfoUnsupported(*MF.getFunction(), Msg, DL.getDebugLoc()));
40 }
41 
42 static void fail(SDLoc DL, SelectionDAG &DAG, const char *Msg, SDValue Val) {
43   MachineFunction &MF = DAG.getMachineFunction();
44   std::string Str;
45   raw_string_ostream OS(Str);
46   OS << Msg;
47   Val->print(OS);
48   OS.flush();
49   DAG.getContext()->diagnose(
50       DiagnosticInfoUnsupported(*MF.getFunction(), Str, DL.getDebugLoc()));
51 }
52 
53 BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
54                                      const BPFSubtarget &STI)
55     : TargetLowering(TM) {
56 
57   // Set up the register classes.
58   addRegisterClass(MVT::i64, &BPF::GPRRegClass);
59 
60   // Compute derived properties from the register classes
61   computeRegisterProperties(STI.getRegisterInfo());
62 
63   setStackPointerRegisterToSaveRestore(BPF::R11);
64 
65   setOperationAction(ISD::BR_CC, MVT::i64, Custom);
66   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
67   setOperationAction(ISD::BRIND, MVT::Other, Expand);
68   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
69   setOperationAction(ISD::SETCC, MVT::i64, Expand);
70   setOperationAction(ISD::SELECT, MVT::i64, Expand);
71   setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
72 
73   setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
74 
75   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
76   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
77   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
78 
79   setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
80   setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
81   setOperationAction(ISD::SREM, MVT::i64, Expand);
82   setOperationAction(ISD::UREM, MVT::i64, Expand);
83 
84   setOperationAction(ISD::MULHU, MVT::i64, Expand);
85   setOperationAction(ISD::MULHS, MVT::i64, Expand);
86   setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
87   setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
88 
89   setOperationAction(ISD::ADDC, MVT::i64, Expand);
90   setOperationAction(ISD::ADDE, MVT::i64, Expand);
91   setOperationAction(ISD::SUBC, MVT::i64, Expand);
92   setOperationAction(ISD::SUBE, MVT::i64, Expand);
93 
94   setOperationAction(ISD::ROTR, MVT::i64, Expand);
95   setOperationAction(ISD::ROTL, MVT::i64, Expand);
96   setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
97   setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
98   setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
99 
100   setOperationAction(ISD::CTTZ, MVT::i64, Custom);
101   setOperationAction(ISD::CTLZ, MVT::i64, Custom);
102   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
103   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
104   setOperationAction(ISD::CTPOP, MVT::i64, Expand);
105 
106   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
107   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
108   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
109   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
110 
111   // Extended load operations for i1 types must be promoted
112   for (MVT VT : MVT::integer_valuetypes()) {
113     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
114     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
115     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
116 
117     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
118     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
119     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
120   }
121 
122   setBooleanContents(ZeroOrOneBooleanContent);
123 
124   // Function alignments (log2)
125   setMinFunctionAlignment(3);
126   setPrefFunctionAlignment(3);
127 
128   // inline memcpy() for kernel to see explicit copy
129   MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 128;
130   MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 128;
131   MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 128;
132 }
133 
134 SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
135   switch (Op.getOpcode()) {
136   case ISD::BR_CC:
137     return LowerBR_CC(Op, DAG);
138   case ISD::GlobalAddress:
139     return LowerGlobalAddress(Op, DAG);
140   case ISD::SELECT_CC:
141     return LowerSELECT_CC(Op, DAG);
142   default:
143     llvm_unreachable("unimplemented operand");
144   }
145 }
146 
147 // Calling Convention Implementation
148 #include "BPFGenCallingConv.inc"
149 
150 SDValue BPFTargetLowering::LowerFormalArguments(
151     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
152     const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
153     SmallVectorImpl<SDValue> &InVals) const {
154   switch (CallConv) {
155   default:
156     llvm_unreachable("Unsupported calling convention");
157   case CallingConv::C:
158   case CallingConv::Fast:
159     break;
160   }
161 
162   MachineFunction &MF = DAG.getMachineFunction();
163   MachineRegisterInfo &RegInfo = MF.getRegInfo();
164 
165   // Assign locations to all of the incoming arguments.
166   SmallVector<CCValAssign, 16> ArgLocs;
167   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
168   CCInfo.AnalyzeFormalArguments(Ins, CC_BPF64);
169 
170   for (auto &VA : ArgLocs) {
171     if (VA.isRegLoc()) {
172       // Arguments passed in registers
173       EVT RegVT = VA.getLocVT();
174       switch (RegVT.getSimpleVT().SimpleTy) {
175       default: {
176         errs() << "LowerFormalArguments Unhandled argument type: "
177                << RegVT.getEVTString() << '\n';
178         llvm_unreachable(0);
179       }
180       case MVT::i64:
181         unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass);
182         RegInfo.addLiveIn(VA.getLocReg(), VReg);
183         SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
184 
185         // If this is an 8/16/32-bit value, it is really passed promoted to 64
186         // bits. Insert an assert[sz]ext to capture this, then truncate to the
187         // right size.
188         if (VA.getLocInfo() == CCValAssign::SExt)
189           ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
190                                  DAG.getValueType(VA.getValVT()));
191         else if (VA.getLocInfo() == CCValAssign::ZExt)
192           ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
193                                  DAG.getValueType(VA.getValVT()));
194 
195         if (VA.getLocInfo() != CCValAssign::Full)
196           ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
197 
198         InVals.push_back(ArgValue);
199       }
200     } else {
201       fail(DL, DAG, "defined with too many args");
202       InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT()));
203     }
204   }
205 
206   if (IsVarArg || MF.getFunction()->hasStructRetAttr()) {
207     fail(DL, DAG, "functions with VarArgs or StructRet are not supported");
208   }
209 
210   return Chain;
211 }
212 
213 const unsigned BPFTargetLowering::MaxArgs = 5;
214 
215 SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
216                                      SmallVectorImpl<SDValue> &InVals) const {
217   SelectionDAG &DAG = CLI.DAG;
218   auto &Outs = CLI.Outs;
219   auto &OutVals = CLI.OutVals;
220   auto &Ins = CLI.Ins;
221   SDValue Chain = CLI.Chain;
222   SDValue Callee = CLI.Callee;
223   bool &IsTailCall = CLI.IsTailCall;
224   CallingConv::ID CallConv = CLI.CallConv;
225   bool IsVarArg = CLI.IsVarArg;
226   MachineFunction &MF = DAG.getMachineFunction();
227 
228   // BPF target does not support tail call optimization.
229   IsTailCall = false;
230 
231   switch (CallConv) {
232   default:
233     report_fatal_error("Unsupported calling convention");
234   case CallingConv::Fast:
235   case CallingConv::C:
236     break;
237   }
238 
239   // Analyze operands of the call, assigning locations to each operand.
240   SmallVector<CCValAssign, 16> ArgLocs;
241   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
242 
243   CCInfo.AnalyzeCallOperands(Outs, CC_BPF64);
244 
245   unsigned NumBytes = CCInfo.getNextStackOffset();
246 
247   if (Outs.size() > MaxArgs)
248     fail(CLI.DL, DAG, "too many args to ", Callee);
249 
250   for (auto &Arg : Outs) {
251     ISD::ArgFlagsTy Flags = Arg.Flags;
252     if (!Flags.isByVal())
253       continue;
254 
255     fail(CLI.DL, DAG, "pass by value not supported ", Callee);
256   }
257 
258   auto PtrVT = getPointerTy(MF.getDataLayout());
259   Chain = DAG.getCALLSEQ_START(
260       Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), CLI.DL);
261 
262   SmallVector<std::pair<unsigned, SDValue>, MaxArgs> RegsToPass;
263 
264   // Walk arg assignments
265   for (unsigned i = 0,
266                 e = std::min(static_cast<unsigned>(ArgLocs.size()), MaxArgs);
267        i != e; ++i) {
268     CCValAssign &VA = ArgLocs[i];
269     SDValue Arg = OutVals[i];
270 
271     // Promote the value if needed.
272     switch (VA.getLocInfo()) {
273     default:
274       llvm_unreachable("Unknown loc info");
275     case CCValAssign::Full:
276       break;
277     case CCValAssign::SExt:
278       Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);
279       break;
280     case CCValAssign::ZExt:
281       Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg);
282       break;
283     case CCValAssign::AExt:
284       Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg);
285       break;
286     }
287 
288     // Push arguments into RegsToPass vector
289     if (VA.isRegLoc())
290       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
291     else
292       llvm_unreachable("call arg pass bug");
293   }
294 
295   SDValue InFlag;
296 
297   // Build a sequence of copy-to-reg nodes chained together with token chain and
298   // flag operands which copy the outgoing args into registers.  The InFlag in
299   // necessary since all emitted instructions must be stuck together.
300   for (auto &Reg : RegsToPass) {
301     Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag);
302     InFlag = Chain.getValue(1);
303   }
304 
305   // If the callee is a GlobalAddress node (quite common, every direct call is)
306   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
307   // Likewise ExternalSymbol -> TargetExternalSymbol.
308   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
309     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, PtrVT,
310                                         G->getOffset(), 0);
311   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
312     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0);
313 
314   // Returns a chain & a flag for retval copy to use.
315   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
316   SmallVector<SDValue, 8> Ops;
317   Ops.push_back(Chain);
318   Ops.push_back(Callee);
319 
320   // Add argument registers to the end of the list so that they are
321   // known live into the call.
322   for (auto &Reg : RegsToPass)
323     Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
324 
325   if (InFlag.getNode())
326     Ops.push_back(InFlag);
327 
328   Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops);
329   InFlag = Chain.getValue(1);
330 
331   // Create the CALLSEQ_END node.
332   Chain = DAG.getCALLSEQ_END(
333       Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true),
334       DAG.getConstant(0, CLI.DL, PtrVT, true), InFlag, CLI.DL);
335   InFlag = Chain.getValue(1);
336 
337   // Handle result values, copying them out of physregs into vregs that we
338   // return.
339   return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG,
340                          InVals);
341 }
342 
343 SDValue
344 BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
345                                bool IsVarArg,
346                                const SmallVectorImpl<ISD::OutputArg> &Outs,
347                                const SmallVectorImpl<SDValue> &OutVals,
348                                SDLoc DL, SelectionDAG &DAG) const {
349 
350   // CCValAssign - represent the assignment of the return value to a location
351   SmallVector<CCValAssign, 16> RVLocs;
352   MachineFunction &MF = DAG.getMachineFunction();
353 
354   // CCState - Info about the registers and stack slot.
355   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
356 
357   if (MF.getFunction()->getReturnType()->isAggregateType()) {
358     fail(DL, DAG, "only integer returns supported");
359   }
360 
361   // Analize return values.
362   CCInfo.AnalyzeReturn(Outs, RetCC_BPF64);
363 
364   SDValue Flag;
365   SmallVector<SDValue, 4> RetOps(1, Chain);
366 
367   // Copy the result values into the output registers.
368   for (unsigned i = 0; i != RVLocs.size(); ++i) {
369     CCValAssign &VA = RVLocs[i];
370     assert(VA.isRegLoc() && "Can only return in registers!");
371 
372     Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
373 
374     // Guarantee that all emitted copies are stuck together,
375     // avoiding something bad.
376     Flag = Chain.getValue(1);
377     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
378   }
379 
380   unsigned Opc = BPFISD::RET_FLAG;
381   RetOps[0] = Chain; // Update chain.
382 
383   // Add the flag if we have it.
384   if (Flag.getNode())
385     RetOps.push_back(Flag);
386 
387   return DAG.getNode(Opc, DL, MVT::Other, RetOps);
388 }
389 
390 SDValue BPFTargetLowering::LowerCallResult(
391     SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
392     const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
393     SmallVectorImpl<SDValue> &InVals) const {
394 
395   MachineFunction &MF = DAG.getMachineFunction();
396   // Assign locations to each value returned by this call.
397   SmallVector<CCValAssign, 16> RVLocs;
398   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
399 
400   if (Ins.size() >= 2) {
401     fail(DL, DAG, "only small returns supported");
402   }
403 
404   CCInfo.AnalyzeCallResult(Ins, RetCC_BPF64);
405 
406   // Copy all of the result registers out of their specified physreg.
407   for (auto &Val : RVLocs) {
408     Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(),
409                                Val.getValVT(), InFlag).getValue(1);
410     InFlag = Chain.getValue(2);
411     InVals.push_back(Chain.getValue(0));
412   }
413 
414   return Chain;
415 }
416 
417 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
418   switch (CC) {
419   default:
420     break;
421   case ISD::SETULT:
422   case ISD::SETULE:
423   case ISD::SETLT:
424   case ISD::SETLE:
425     CC = ISD::getSetCCSwappedOperands(CC);
426     std::swap(LHS, RHS);
427     break;
428   }
429 }
430 
431 SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
432   SDValue Chain = Op.getOperand(0);
433   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
434   SDValue LHS = Op.getOperand(2);
435   SDValue RHS = Op.getOperand(3);
436   SDValue Dest = Op.getOperand(4);
437   SDLoc DL(Op);
438 
439   NegateCC(LHS, RHS, CC);
440 
441   return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
442                      DAG.getConstant(CC, DL, MVT::i64), Dest);
443 }
444 
445 SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
446   SDValue LHS = Op.getOperand(0);
447   SDValue RHS = Op.getOperand(1);
448   SDValue TrueV = Op.getOperand(2);
449   SDValue FalseV = Op.getOperand(3);
450   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
451   SDLoc DL(Op);
452 
453   NegateCC(LHS, RHS, CC);
454 
455   SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i64);
456 
457   SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
458   SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
459 
460   return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
461 }
462 
463 const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
464   switch ((BPFISD::NodeType)Opcode) {
465   case BPFISD::FIRST_NUMBER:
466     break;
467   case BPFISD::RET_FLAG:
468     return "BPFISD::RET_FLAG";
469   case BPFISD::CALL:
470     return "BPFISD::CALL";
471   case BPFISD::SELECT_CC:
472     return "BPFISD::SELECT_CC";
473   case BPFISD::BR_CC:
474     return "BPFISD::BR_CC";
475   case BPFISD::Wrapper:
476     return "BPFISD::Wrapper";
477   }
478   return nullptr;
479 }
480 
481 SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op,
482                                               SelectionDAG &DAG) const {
483   SDLoc DL(Op);
484   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
485   SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64);
486 
487   return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA);
488 }
489 
490 MachineBasicBlock *
491 BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
492                                                MachineBasicBlock *BB) const {
493   const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
494   DebugLoc DL = MI->getDebugLoc();
495 
496   assert(MI->getOpcode() == BPF::Select && "Unexpected instr type to insert");
497 
498   // To "insert" a SELECT instruction, we actually have to insert the diamond
499   // control-flow pattern.  The incoming instruction knows the destination vreg
500   // to set, the condition code register to branch on, the true/false values to
501   // select between, and a branch opcode to use.
502   const BasicBlock *LLVM_BB = BB->getBasicBlock();
503   MachineFunction::iterator I = ++BB->getIterator();
504 
505   // ThisMBB:
506   // ...
507   //  TrueVal = ...
508   //  jmp_XX r1, r2 goto Copy1MBB
509   //  fallthrough --> Copy0MBB
510   MachineBasicBlock *ThisMBB = BB;
511   MachineFunction *F = BB->getParent();
512   MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
513   MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
514 
515   F->insert(I, Copy0MBB);
516   F->insert(I, Copy1MBB);
517   // Update machine-CFG edges by transferring all successors of the current
518   // block to the new block which will contain the Phi node for the select.
519   Copy1MBB->splice(Copy1MBB->begin(), BB,
520                    std::next(MachineBasicBlock::iterator(MI)), BB->end());
521   Copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
522   // Next, add the true and fallthrough blocks as its successors.
523   BB->addSuccessor(Copy0MBB);
524   BB->addSuccessor(Copy1MBB);
525 
526   // Insert Branch if Flag
527   unsigned LHS = MI->getOperand(1).getReg();
528   unsigned RHS = MI->getOperand(2).getReg();
529   int CC = MI->getOperand(3).getImm();
530   switch (CC) {
531   case ISD::SETGT:
532     BuildMI(BB, DL, TII.get(BPF::JSGT_rr))
533         .addReg(LHS)
534         .addReg(RHS)
535         .addMBB(Copy1MBB);
536     break;
537   case ISD::SETUGT:
538     BuildMI(BB, DL, TII.get(BPF::JUGT_rr))
539         .addReg(LHS)
540         .addReg(RHS)
541         .addMBB(Copy1MBB);
542     break;
543   case ISD::SETGE:
544     BuildMI(BB, DL, TII.get(BPF::JSGE_rr))
545         .addReg(LHS)
546         .addReg(RHS)
547         .addMBB(Copy1MBB);
548     break;
549   case ISD::SETUGE:
550     BuildMI(BB, DL, TII.get(BPF::JUGE_rr))
551         .addReg(LHS)
552         .addReg(RHS)
553         .addMBB(Copy1MBB);
554     break;
555   case ISD::SETEQ:
556     BuildMI(BB, DL, TII.get(BPF::JEQ_rr))
557         .addReg(LHS)
558         .addReg(RHS)
559         .addMBB(Copy1MBB);
560     break;
561   case ISD::SETNE:
562     BuildMI(BB, DL, TII.get(BPF::JNE_rr))
563         .addReg(LHS)
564         .addReg(RHS)
565         .addMBB(Copy1MBB);
566     break;
567   default:
568     report_fatal_error("unimplemented select CondCode " + Twine(CC));
569   }
570 
571   // Copy0MBB:
572   //  %FalseValue = ...
573   //  # fallthrough to Copy1MBB
574   BB = Copy0MBB;
575 
576   // Update machine-CFG edges
577   BB->addSuccessor(Copy1MBB);
578 
579   // Copy1MBB:
580   //  %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
581   // ...
582   BB = Copy1MBB;
583   BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI->getOperand(0).getReg())
584       .addReg(MI->getOperand(5).getReg())
585       .addMBB(Copy0MBB)
586       .addReg(MI->getOperand(4).getReg())
587       .addMBB(ThisMBB);
588 
589   MI->eraseFromParent(); // The pseudo instruction is gone now.
590   return BB;
591 }
592