1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that BPF uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "BPFISelLowering.h" 16 #include "BPF.h" 17 #include "BPFTargetMachine.h" 18 #include "BPFSubtarget.h" 19 #include "llvm/CodeGen/CallingConvLower.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/SelectionDAGISel.h" 25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/Debug.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/IR/DiagnosticInfo.h" 32 #include "llvm/IR/DiagnosticPrinter.h" 33 using namespace llvm; 34 35 #define DEBUG_TYPE "bpf-lower" 36 37 static void fail(SDLoc DL, SelectionDAG &DAG, const char *Msg) { 38 MachineFunction &MF = DAG.getMachineFunction(); 39 DAG.getContext()->diagnose( 40 DiagnosticInfoUnsupported(*MF.getFunction(), Msg, DL.getDebugLoc())); 41 } 42 43 static void fail(SDLoc DL, SelectionDAG &DAG, const char *Msg, SDValue Val) { 44 MachineFunction &MF = DAG.getMachineFunction(); 45 std::string Str; 46 raw_string_ostream OS(Str); 47 OS << Msg; 48 Val->print(OS); 49 OS.flush(); 50 DAG.getContext()->diagnose( 51 DiagnosticInfoUnsupported(*MF.getFunction(), Str, DL.getDebugLoc())); 52 } 53 54 BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM, 55 const BPFSubtarget &STI) 56 : TargetLowering(TM) { 57 58 // Set up the register classes. 59 addRegisterClass(MVT::i64, &BPF::GPRRegClass); 60 61 // Compute derived properties from the register classes 62 computeRegisterProperties(STI.getRegisterInfo()); 63 64 setStackPointerRegisterToSaveRestore(BPF::R11); 65 66 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 67 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 68 setOperationAction(ISD::BRIND, MVT::Other, Expand); 69 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 70 setOperationAction(ISD::SETCC, MVT::i64, Expand); 71 setOperationAction(ISD::SELECT, MVT::i64, Expand); 72 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 73 74 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 75 76 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 77 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 78 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 79 80 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 81 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 82 setOperationAction(ISD::SREM, MVT::i64, Expand); 83 setOperationAction(ISD::UREM, MVT::i64, Expand); 84 85 setOperationAction(ISD::MULHU, MVT::i64, Expand); 86 setOperationAction(ISD::MULHS, MVT::i64, Expand); 87 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 88 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 89 90 setOperationAction(ISD::ADDC, MVT::i64, Expand); 91 setOperationAction(ISD::ADDE, MVT::i64, Expand); 92 setOperationAction(ISD::SUBC, MVT::i64, Expand); 93 setOperationAction(ISD::SUBE, MVT::i64, Expand); 94 95 setOperationAction(ISD::ROTR, MVT::i64, Expand); 96 setOperationAction(ISD::ROTL, MVT::i64, Expand); 97 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); 98 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); 99 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); 100 101 setOperationAction(ISD::CTTZ, MVT::i64, Custom); 102 setOperationAction(ISD::CTLZ, MVT::i64, Custom); 103 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom); 104 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 105 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 106 107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); 111 112 // Extended load operations for i1 types must be promoted 113 for (MVT VT : MVT::integer_valuetypes()) { 114 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 115 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 116 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 117 118 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 119 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); 120 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); 121 } 122 123 setBooleanContents(ZeroOrOneBooleanContent); 124 125 // Function alignments (log2) 126 setMinFunctionAlignment(3); 127 setPrefFunctionAlignment(3); 128 129 // inline memcpy() for kernel to see explicit copy 130 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 128; 131 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 128; 132 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 128; 133 } 134 135 SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 136 switch (Op.getOpcode()) { 137 case ISD::BR_CC: 138 return LowerBR_CC(Op, DAG); 139 case ISD::GlobalAddress: 140 return LowerGlobalAddress(Op, DAG); 141 case ISD::SELECT_CC: 142 return LowerSELECT_CC(Op, DAG); 143 default: 144 llvm_unreachable("unimplemented operand"); 145 } 146 } 147 148 // Calling Convention Implementation 149 #include "BPFGenCallingConv.inc" 150 151 SDValue BPFTargetLowering::LowerFormalArguments( 152 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 153 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, 154 SmallVectorImpl<SDValue> &InVals) const { 155 switch (CallConv) { 156 default: 157 llvm_unreachable("Unsupported calling convention"); 158 case CallingConv::C: 159 case CallingConv::Fast: 160 break; 161 } 162 163 MachineFunction &MF = DAG.getMachineFunction(); 164 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 165 166 // Assign locations to all of the incoming arguments. 167 SmallVector<CCValAssign, 16> ArgLocs; 168 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 169 CCInfo.AnalyzeFormalArguments(Ins, CC_BPF64); 170 171 for (auto &VA : ArgLocs) { 172 if (VA.isRegLoc()) { 173 // Arguments passed in registers 174 EVT RegVT = VA.getLocVT(); 175 switch (RegVT.getSimpleVT().SimpleTy) { 176 default: { 177 errs() << "LowerFormalArguments Unhandled argument type: " 178 << RegVT.getSimpleVT().SimpleTy << '\n'; 179 llvm_unreachable(0); 180 } 181 case MVT::i64: 182 unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass); 183 RegInfo.addLiveIn(VA.getLocReg(), VReg); 184 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); 185 186 // If this is an 8/16/32-bit value, it is really passed promoted to 64 187 // bits. Insert an assert[sz]ext to capture this, then truncate to the 188 // right size. 189 if (VA.getLocInfo() == CCValAssign::SExt) 190 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, 191 DAG.getValueType(VA.getValVT())); 192 else if (VA.getLocInfo() == CCValAssign::ZExt) 193 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, 194 DAG.getValueType(VA.getValVT())); 195 196 if (VA.getLocInfo() != CCValAssign::Full) 197 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); 198 199 InVals.push_back(ArgValue); 200 } 201 } else { 202 fail(DL, DAG, "defined with too many args"); 203 } 204 } 205 206 if (IsVarArg || MF.getFunction()->hasStructRetAttr()) { 207 fail(DL, DAG, "functions with VarArgs or StructRet are not supported"); 208 } 209 210 return Chain; 211 } 212 213 SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 214 SmallVectorImpl<SDValue> &InVals) const { 215 SelectionDAG &DAG = CLI.DAG; 216 auto &Outs = CLI.Outs; 217 auto &OutVals = CLI.OutVals; 218 auto &Ins = CLI.Ins; 219 SDValue Chain = CLI.Chain; 220 SDValue Callee = CLI.Callee; 221 bool &IsTailCall = CLI.IsTailCall; 222 CallingConv::ID CallConv = CLI.CallConv; 223 bool IsVarArg = CLI.IsVarArg; 224 MachineFunction &MF = DAG.getMachineFunction(); 225 226 // BPF target does not support tail call optimization. 227 IsTailCall = false; 228 229 switch (CallConv) { 230 default: 231 report_fatal_error("Unsupported calling convention"); 232 case CallingConv::Fast: 233 case CallingConv::C: 234 break; 235 } 236 237 // Analyze operands of the call, assigning locations to each operand. 238 SmallVector<CCValAssign, 16> ArgLocs; 239 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 240 241 CCInfo.AnalyzeCallOperands(Outs, CC_BPF64); 242 243 unsigned NumBytes = CCInfo.getNextStackOffset(); 244 245 if (Outs.size() >= 6) { 246 fail(CLI.DL, DAG, "too many args to ", Callee); 247 } 248 249 for (auto &Arg : Outs) { 250 ISD::ArgFlagsTy Flags = Arg.Flags; 251 if (!Flags.isByVal()) 252 continue; 253 254 fail(CLI.DL, DAG, "pass by value not supported ", Callee); 255 } 256 257 auto PtrVT = getPointerTy(MF.getDataLayout()); 258 Chain = DAG.getCALLSEQ_START( 259 Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), CLI.DL); 260 261 SmallVector<std::pair<unsigned, SDValue>, 5> RegsToPass; 262 263 // Walk arg assignments 264 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 265 CCValAssign &VA = ArgLocs[i]; 266 SDValue Arg = OutVals[i]; 267 268 // Promote the value if needed. 269 switch (VA.getLocInfo()) { 270 default: 271 llvm_unreachable("Unknown loc info"); 272 case CCValAssign::Full: 273 break; 274 case CCValAssign::SExt: 275 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); 276 break; 277 case CCValAssign::ZExt: 278 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); 279 break; 280 case CCValAssign::AExt: 281 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg); 282 break; 283 } 284 285 // Push arguments into RegsToPass vector 286 if (VA.isRegLoc()) 287 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 288 else 289 llvm_unreachable("call arg pass bug"); 290 } 291 292 SDValue InFlag; 293 294 // Build a sequence of copy-to-reg nodes chained together with token chain and 295 // flag operands which copy the outgoing args into registers. The InFlag in 296 // necessary since all emitted instructions must be stuck together. 297 for (auto &Reg : RegsToPass) { 298 Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag); 299 InFlag = Chain.getValue(1); 300 } 301 302 // If the callee is a GlobalAddress node (quite common, every direct call is) 303 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 304 // Likewise ExternalSymbol -> TargetExternalSymbol. 305 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 306 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, PtrVT, 307 G->getOffset(), 0); 308 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 309 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0); 310 311 // Returns a chain & a flag for retval copy to use. 312 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 313 SmallVector<SDValue, 8> Ops; 314 Ops.push_back(Chain); 315 Ops.push_back(Callee); 316 317 // Add argument registers to the end of the list so that they are 318 // known live into the call. 319 for (auto &Reg : RegsToPass) 320 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); 321 322 if (InFlag.getNode()) 323 Ops.push_back(InFlag); 324 325 Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops); 326 InFlag = Chain.getValue(1); 327 328 // Create the CALLSEQ_END node. 329 Chain = DAG.getCALLSEQ_END( 330 Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), 331 DAG.getConstant(0, CLI.DL, PtrVT, true), InFlag, CLI.DL); 332 InFlag = Chain.getValue(1); 333 334 // Handle result values, copying them out of physregs into vregs that we 335 // return. 336 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG, 337 InVals); 338 } 339 340 SDValue 341 BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 342 bool IsVarArg, 343 const SmallVectorImpl<ISD::OutputArg> &Outs, 344 const SmallVectorImpl<SDValue> &OutVals, 345 SDLoc DL, SelectionDAG &DAG) const { 346 347 // CCValAssign - represent the assignment of the return value to a location 348 SmallVector<CCValAssign, 16> RVLocs; 349 MachineFunction &MF = DAG.getMachineFunction(); 350 351 // CCState - Info about the registers and stack slot. 352 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 353 354 if (MF.getFunction()->getReturnType()->isAggregateType()) { 355 fail(DL, DAG, "only integer returns supported"); 356 } 357 358 // Analize return values. 359 CCInfo.AnalyzeReturn(Outs, RetCC_BPF64); 360 361 SDValue Flag; 362 SmallVector<SDValue, 4> RetOps(1, Chain); 363 364 // Copy the result values into the output registers. 365 for (unsigned i = 0; i != RVLocs.size(); ++i) { 366 CCValAssign &VA = RVLocs[i]; 367 assert(VA.isRegLoc() && "Can only return in registers!"); 368 369 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); 370 371 // Guarantee that all emitted copies are stuck together, 372 // avoiding something bad. 373 Flag = Chain.getValue(1); 374 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 375 } 376 377 unsigned Opc = BPFISD::RET_FLAG; 378 RetOps[0] = Chain; // Update chain. 379 380 // Add the flag if we have it. 381 if (Flag.getNode()) 382 RetOps.push_back(Flag); 383 384 return DAG.getNode(Opc, DL, MVT::Other, RetOps); 385 } 386 387 SDValue BPFTargetLowering::LowerCallResult( 388 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 389 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, 390 SmallVectorImpl<SDValue> &InVals) const { 391 392 MachineFunction &MF = DAG.getMachineFunction(); 393 // Assign locations to each value returned by this call. 394 SmallVector<CCValAssign, 16> RVLocs; 395 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 396 397 if (Ins.size() >= 2) { 398 fail(DL, DAG, "only small returns supported"); 399 } 400 401 CCInfo.AnalyzeCallResult(Ins, RetCC_BPF64); 402 403 // Copy all of the result registers out of their specified physreg. 404 for (auto &Val : RVLocs) { 405 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), 406 Val.getValVT(), InFlag).getValue(1); 407 InFlag = Chain.getValue(2); 408 InVals.push_back(Chain.getValue(0)); 409 } 410 411 return Chain; 412 } 413 414 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { 415 switch (CC) { 416 default: 417 break; 418 case ISD::SETULT: 419 case ISD::SETULE: 420 case ISD::SETLT: 421 case ISD::SETLE: 422 CC = ISD::getSetCCSwappedOperands(CC); 423 std::swap(LHS, RHS); 424 break; 425 } 426 } 427 428 SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 429 SDValue Chain = Op.getOperand(0); 430 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 431 SDValue LHS = Op.getOperand(2); 432 SDValue RHS = Op.getOperand(3); 433 SDValue Dest = Op.getOperand(4); 434 SDLoc DL(Op); 435 436 NegateCC(LHS, RHS, CC); 437 438 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS, 439 DAG.getConstant(CC, DL, MVT::i64), Dest); 440 } 441 442 SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 443 SDValue LHS = Op.getOperand(0); 444 SDValue RHS = Op.getOperand(1); 445 SDValue TrueV = Op.getOperand(2); 446 SDValue FalseV = Op.getOperand(3); 447 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 448 SDLoc DL(Op); 449 450 NegateCC(LHS, RHS, CC); 451 452 SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i64); 453 454 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 455 SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV}; 456 457 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops); 458 } 459 460 const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const { 461 switch ((BPFISD::NodeType)Opcode) { 462 case BPFISD::FIRST_NUMBER: 463 break; 464 case BPFISD::RET_FLAG: 465 return "BPFISD::RET_FLAG"; 466 case BPFISD::CALL: 467 return "BPFISD::CALL"; 468 case BPFISD::SELECT_CC: 469 return "BPFISD::SELECT_CC"; 470 case BPFISD::BR_CC: 471 return "BPFISD::BR_CC"; 472 case BPFISD::Wrapper: 473 return "BPFISD::Wrapper"; 474 } 475 return nullptr; 476 } 477 478 SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op, 479 SelectionDAG &DAG) const { 480 SDLoc DL(Op); 481 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 482 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64); 483 484 return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA); 485 } 486 487 MachineBasicBlock * 488 BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 489 MachineBasicBlock *BB) const { 490 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); 491 DebugLoc DL = MI->getDebugLoc(); 492 493 assert(MI->getOpcode() == BPF::Select && "Unexpected instr type to insert"); 494 495 // To "insert" a SELECT instruction, we actually have to insert the diamond 496 // control-flow pattern. The incoming instruction knows the destination vreg 497 // to set, the condition code register to branch on, the true/false values to 498 // select between, and a branch opcode to use. 499 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 500 MachineFunction::iterator I = ++BB->getIterator(); 501 502 // ThisMBB: 503 // ... 504 // TrueVal = ... 505 // jmp_XX r1, r2 goto Copy1MBB 506 // fallthrough --> Copy0MBB 507 MachineBasicBlock *ThisMBB = BB; 508 MachineFunction *F = BB->getParent(); 509 MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 510 MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 511 512 F->insert(I, Copy0MBB); 513 F->insert(I, Copy1MBB); 514 // Update machine-CFG edges by transferring all successors of the current 515 // block to the new block which will contain the Phi node for the select. 516 Copy1MBB->splice(Copy1MBB->begin(), BB, 517 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 518 Copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 519 // Next, add the true and fallthrough blocks as its successors. 520 BB->addSuccessor(Copy0MBB); 521 BB->addSuccessor(Copy1MBB); 522 523 // Insert Branch if Flag 524 unsigned LHS = MI->getOperand(1).getReg(); 525 unsigned RHS = MI->getOperand(2).getReg(); 526 int CC = MI->getOperand(3).getImm(); 527 switch (CC) { 528 case ISD::SETGT: 529 BuildMI(BB, DL, TII.get(BPF::JSGT_rr)) 530 .addReg(LHS) 531 .addReg(RHS) 532 .addMBB(Copy1MBB); 533 break; 534 case ISD::SETUGT: 535 BuildMI(BB, DL, TII.get(BPF::JUGT_rr)) 536 .addReg(LHS) 537 .addReg(RHS) 538 .addMBB(Copy1MBB); 539 break; 540 case ISD::SETGE: 541 BuildMI(BB, DL, TII.get(BPF::JSGE_rr)) 542 .addReg(LHS) 543 .addReg(RHS) 544 .addMBB(Copy1MBB); 545 break; 546 case ISD::SETUGE: 547 BuildMI(BB, DL, TII.get(BPF::JUGE_rr)) 548 .addReg(LHS) 549 .addReg(RHS) 550 .addMBB(Copy1MBB); 551 break; 552 case ISD::SETEQ: 553 BuildMI(BB, DL, TII.get(BPF::JEQ_rr)) 554 .addReg(LHS) 555 .addReg(RHS) 556 .addMBB(Copy1MBB); 557 break; 558 case ISD::SETNE: 559 BuildMI(BB, DL, TII.get(BPF::JNE_rr)) 560 .addReg(LHS) 561 .addReg(RHS) 562 .addMBB(Copy1MBB); 563 break; 564 default: 565 report_fatal_error("unimplemented select CondCode " + Twine(CC)); 566 } 567 568 // Copy0MBB: 569 // %FalseValue = ... 570 // # fallthrough to Copy1MBB 571 BB = Copy0MBB; 572 573 // Update machine-CFG edges 574 BB->addSuccessor(Copy1MBB); 575 576 // Copy1MBB: 577 // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ] 578 // ... 579 BB = Copy1MBB; 580 BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI->getOperand(0).getReg()) 581 .addReg(MI->getOperand(5).getReg()) 582 .addMBB(Copy0MBB) 583 .addReg(MI->getOperand(4).getReg()) 584 .addMBB(ThisMBB); 585 586 MI->eraseFromParent(); // The pseudo instruction is gone now. 587 return BB; 588 } 589