1 //===-- AVRInstrInfo.cpp - AVR Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AVR implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRInstrInfo.h"
15 
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/IR/Constants.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
27 
28 #include "AVR.h"
29 #include "AVRMachineFunctionInfo.h"
30 #include "AVRTargetMachine.h"
31 #include "MCTargetDesc/AVRMCTargetDesc.h"
32 
33 #define GET_INSTRINFO_CTOR_DTOR
34 #include "AVRGenInstrInfo.inc"
35 
36 namespace llvm {
37 
38 AVRInstrInfo::AVRInstrInfo()
39     : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {}
40 
41 void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
42                                MachineBasicBlock::iterator MI, DebugLoc DL,
43                                unsigned DestReg, unsigned SrcReg,
44                                bool KillSrc) const {
45   unsigned Opc;
46 
47   if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) {
48     Opc = AVR::MOVRdRr;
49   } else if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) {
50     Opc = AVR::MOVWRdRr;
51   } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) {
52     Opc = AVR::SPREAD;
53   } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) {
54     Opc = AVR::SPWRITE;
55   } else {
56     llvm_unreachable("Impossible reg-to-reg copy");
57   }
58 
59   BuildMI(MBB, MI, DL, get(Opc), DestReg)
60       .addReg(SrcReg, getKillRegState(KillSrc));
61 }
62 
63 unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
64                                            int &FrameIndex) const {
65   switch (MI->getOpcode()) {
66   case AVR::LDDRdPtrQ:
67   case AVR::LDDWRdYQ: { //:FIXME: remove this once PR13375 gets fixed
68     if ((MI->getOperand(1).isFI()) && (MI->getOperand(2).isImm()) &&
69         (MI->getOperand(2).getImm() == 0)) {
70       FrameIndex = MI->getOperand(1).getIndex();
71       return MI->getOperand(0).getReg();
72     }
73     break;
74   }
75   default:
76     break;
77   }
78 
79   return 0;
80 }
81 
82 unsigned AVRInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
83                                           int &FrameIndex) const {
84   switch (MI->getOpcode()) {
85   case AVR::STDPtrQRr:
86   case AVR::STDWPtrQRr: {
87     if ((MI->getOperand(0).isFI()) && (MI->getOperand(1).isImm()) &&
88         (MI->getOperand(1).getImm() == 0)) {
89       FrameIndex = MI->getOperand(0).getIndex();
90       return MI->getOperand(2).getReg();
91     }
92     break;
93   }
94   default:
95     break;
96   }
97 
98   return 0;
99 }
100 
101 void AVRInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
102                                        MachineBasicBlock::iterator MI,
103                                        unsigned SrcReg, bool isKill,
104                                        int FrameIndex,
105                                        const TargetRegisterClass *RC,
106                                        const TargetRegisterInfo *TRI) const {
107   MachineFunction &MF = *MBB.getParent();
108   AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
109 
110   DebugLoc DL;
111   if (MI != MBB.end()) {
112     DL = MI->getDebugLoc();
113   }
114 
115   const MachineFrameInfo &MFI = *MF.getFrameInfo();
116 
117   MachineMemOperand *MMO = MF.getMachineMemOperand(
118       MachinePointerInfo::getFixedStack(MF, FrameIndex),
119       MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex),
120       MFI.getObjectAlignment(FrameIndex));
121 
122   unsigned Opcode = 0;
123   if (RC->hasType(MVT::i8)) {
124     Opcode = AVR::STDPtrQRr;
125   } else if (RC->hasType(MVT::i16)) {
126     Opcode = AVR::STDWPtrQRr;
127   } else {
128     llvm_unreachable("Cannot store this register into a stack slot!");
129   }
130 
131   BuildMI(MBB, MI, DL, get(Opcode))
132       .addFrameIndex(FrameIndex)
133       .addImm(0)
134       .addReg(SrcReg, getKillRegState(isKill))
135       .addMemOperand(MMO);
136 }
137 
138 void AVRInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
139                                         MachineBasicBlock::iterator MI,
140                                         unsigned DestReg, int FrameIndex,
141                                         const TargetRegisterClass *RC,
142                                         const TargetRegisterInfo *TRI) const {
143   DebugLoc DL;
144   if (MI != MBB.end()) {
145     DL = MI->getDebugLoc();
146   }
147 
148   MachineFunction &MF = *MBB.getParent();
149   const MachineFrameInfo &MFI = *MF.getFrameInfo();
150 
151   MachineMemOperand *MMO = MF.getMachineMemOperand(
152       MachinePointerInfo::getFixedStack(MF, FrameIndex),
153       MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex),
154       MFI.getObjectAlignment(FrameIndex));
155 
156   unsigned Opcode = 0;
157   if (RC->hasType(MVT::i8)) {
158     Opcode = AVR::LDDRdPtrQ;
159   } else if (RC->hasType(MVT::i16)) {
160     // Opcode = AVR::LDDWRdPtrQ;
161     //:FIXME: remove this once PR13375 gets fixed
162     Opcode = AVR::LDDWRdYQ;
163   } else {
164     llvm_unreachable("Cannot load this register from a stack slot!");
165   }
166 
167   BuildMI(MBB, MI, DL, get(Opcode), DestReg)
168       .addFrameIndex(FrameIndex)
169       .addImm(0)
170       .addMemOperand(MMO);
171 }
172 
173 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const {
174   switch (CC) {
175   default:
176     llvm_unreachable("Unknown condition code!");
177   case AVRCC::COND_EQ:
178     return get(AVR::BREQk);
179   case AVRCC::COND_NE:
180     return get(AVR::BRNEk);
181   case AVRCC::COND_GE:
182     return get(AVR::BRGEk);
183   case AVRCC::COND_LT:
184     return get(AVR::BRLTk);
185   case AVRCC::COND_SH:
186     return get(AVR::BRSHk);
187   case AVRCC::COND_LO:
188     return get(AVR::BRLOk);
189   case AVRCC::COND_MI:
190     return get(AVR::BRMIk);
191   case AVRCC::COND_PL:
192     return get(AVR::BRPLk);
193   }
194 }
195 
196 AVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
197   switch (Opc) {
198   default:
199     return AVRCC::COND_INVALID;
200   case AVR::BREQk:
201     return AVRCC::COND_EQ;
202   case AVR::BRNEk:
203     return AVRCC::COND_NE;
204   case AVR::BRSHk:
205     return AVRCC::COND_SH;
206   case AVR::BRLOk:
207     return AVRCC::COND_LO;
208   case AVR::BRMIk:
209     return AVRCC::COND_MI;
210   case AVR::BRPLk:
211     return AVRCC::COND_PL;
212   case AVR::BRGEk:
213     return AVRCC::COND_GE;
214   case AVR::BRLTk:
215     return AVRCC::COND_LT;
216   }
217 }
218 
219 AVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const {
220   switch (CC) {
221   default:
222     llvm_unreachable("Invalid condition!");
223   case AVRCC::COND_EQ:
224     return AVRCC::COND_NE;
225   case AVRCC::COND_NE:
226     return AVRCC::COND_EQ;
227   case AVRCC::COND_SH:
228     return AVRCC::COND_LO;
229   case AVRCC::COND_LO:
230     return AVRCC::COND_SH;
231   case AVRCC::COND_GE:
232     return AVRCC::COND_LT;
233   case AVRCC::COND_LT:
234     return AVRCC::COND_GE;
235   case AVRCC::COND_MI:
236     return AVRCC::COND_PL;
237   case AVRCC::COND_PL:
238     return AVRCC::COND_MI;
239   }
240 }
241 
242 bool AVRInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
243                                  MachineBasicBlock *&TBB,
244                                  MachineBasicBlock *&FBB,
245                                  SmallVectorImpl<MachineOperand> &Cond,
246                                  bool AllowModify) const {
247   // Start from the bottom of the block and work up, examining the
248   // terminator instructions.
249   MachineBasicBlock::iterator I = MBB.end();
250   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
251 
252   while (I != MBB.begin()) {
253     --I;
254     if (I->isDebugValue()) {
255       continue;
256     }
257 
258     // Working from the bottom, when we see a non-terminator
259     // instruction, we're done.
260     if (!isUnpredicatedTerminator(*I)) {
261       break;
262     }
263 
264     // A terminator that isn't a branch can't easily be handled
265     // by this analysis.
266     if (!I->getDesc().isBranch()) {
267       return true;
268     }
269 
270     // Handle unconditional branches.
271     //:TODO: add here jmp
272     if (I->getOpcode() == AVR::RJMPk) {
273       UnCondBrIter = I;
274 
275       if (!AllowModify) {
276         TBB = I->getOperand(0).getMBB();
277         continue;
278       }
279 
280       // If the block has any instructions after a JMP, delete them.
281       while (std::next(I) != MBB.end()) {
282         std::next(I)->eraseFromParent();
283       }
284 
285       Cond.clear();
286       FBB = 0;
287 
288       // Delete the JMP if it's equivalent to a fall-through.
289       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
290         TBB = 0;
291         I->eraseFromParent();
292         I = MBB.end();
293         UnCondBrIter = MBB.end();
294         continue;
295       }
296 
297       // TBB is used to indicate the unconditinal destination.
298       TBB = I->getOperand(0).getMBB();
299       continue;
300     }
301 
302     // Handle conditional branches.
303     AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
304     if (BranchCode == AVRCC::COND_INVALID) {
305       return true; // Can't handle indirect branch.
306     }
307 
308     // Working from the bottom, handle the first conditional branch.
309     if (Cond.empty()) {
310       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
311       if (AllowModify && UnCondBrIter != MBB.end() &&
312           MBB.isLayoutSuccessor(TargetBB)) {
313         // If we can modify the code and it ends in something like:
314         //
315         //     jCC L1
316         //     jmp L2
317         //   L1:
318         //     ...
319         //   L2:
320         //
321         // Then we can change this to:
322         //
323         //     jnCC L2
324         //   L1:
325         //     ...
326         //   L2:
327         //
328         // Which is a bit more efficient.
329         // We conditionally jump to the fall-through block.
330         BranchCode = getOppositeCondition(BranchCode);
331         unsigned JNCC = getBrCond(BranchCode).getOpcode();
332         MachineBasicBlock::iterator OldInst = I;
333 
334         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
335             .addMBB(UnCondBrIter->getOperand(0).getMBB());
336         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(AVR::RJMPk))
337             .addMBB(TargetBB);
338 
339         OldInst->eraseFromParent();
340         UnCondBrIter->eraseFromParent();
341 
342         // Restart the analysis.
343         UnCondBrIter = MBB.end();
344         I = MBB.end();
345         continue;
346       }
347 
348       FBB = TBB;
349       TBB = I->getOperand(0).getMBB();
350       Cond.push_back(MachineOperand::CreateImm(BranchCode));
351       continue;
352     }
353 
354     // Handle subsequent conditional branches. Only handle the case where all
355     // conditional branches branch to the same destination.
356     assert(Cond.size() == 1);
357     assert(TBB);
358 
359     // Only handle the case where all conditional branches branch to
360     // the same destination.
361     if (TBB != I->getOperand(0).getMBB()) {
362       return true;
363     }
364 
365     AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm();
366     // If the conditions are the same, we can leave them alone.
367     if (OldBranchCode == BranchCode) {
368       continue;
369     }
370 
371     return true;
372   }
373 
374   return false;
375 }
376 
377 unsigned AVRInstrInfo::InsertBranch(MachineBasicBlock &MBB,
378                                     MachineBasicBlock *TBB,
379                                     MachineBasicBlock *FBB,
380                                     ArrayRef<MachineOperand> Cond,
381                                     DebugLoc DL) const {
382   // Shouldn't be a fall through.
383   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
384   assert((Cond.size() == 1 || Cond.size() == 0) &&
385          "AVR branch conditions have one component!");
386 
387   if (Cond.empty()) {
388     assert(!FBB && "Unconditional branch with multiple successors!");
389     BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(TBB);
390     return 1;
391   }
392 
393   // Conditional branch.
394   unsigned Count = 0;
395   AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm();
396   BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
397   ++Count;
398 
399   if (FBB) {
400     // Two-way Conditional branch. Insert the second branch.
401     BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(FBB);
402     ++Count;
403   }
404 
405   return Count;
406 }
407 
408 unsigned AVRInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
409   MachineBasicBlock::iterator I = MBB.end();
410   unsigned Count = 0;
411 
412   while (I != MBB.begin()) {
413     --I;
414     if (I->isDebugValue()) {
415       continue;
416     }
417     //:TODO: add here the missing jmp instructions once they are implemented
418     // like jmp, {e}ijmp, and other cond branches, ...
419     if (I->getOpcode() != AVR::RJMPk &&
420         getCondFromBranchOpc(I->getOpcode()) == AVRCC::COND_INVALID) {
421       break;
422     }
423 
424     // Remove the branch.
425     I->eraseFromParent();
426     I = MBB.end();
427     ++Count;
428   }
429 
430   return Count;
431 }
432 
433 bool AVRInstrInfo::ReverseBranchCondition(
434     SmallVectorImpl<MachineOperand> &Cond) const {
435   assert(Cond.size() == 1 && "Invalid AVR branch condition!");
436 
437   AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm());
438   Cond[0].setImm(getOppositeCondition(CC));
439 
440   return false;
441 }
442 
443 unsigned AVRInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
444   unsigned Opcode = MI->getOpcode();
445 
446   switch (Opcode) {
447   // A regular instruction
448   default: {
449     const MCInstrDesc &Desc = get(Opcode);
450     return Desc.getSize();
451   }
452   case TargetOpcode::EH_LABEL:
453   case TargetOpcode::IMPLICIT_DEF:
454   case TargetOpcode::KILL:
455   case TargetOpcode::DBG_VALUE:
456     return 0;
457   case TargetOpcode::INLINEASM: {
458     const MachineFunction *MF = MI->getParent()->getParent();
459     const AVRTargetMachine &TM = static_cast<const AVRTargetMachine&>(MF->getTarget());
460     const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
461     return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
462                                   *TM.getMCAsmInfo());
463   }
464   }
465 }
466 
467 } // end of namespace llvm
468