1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that AVR uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "AVRISelLowering.h" 16 17 #include "llvm/CodeGen/CallingConvLower.h" 18 #include "llvm/CodeGen/MachineFrameInfo.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/Support/ErrorHandling.h" 25 26 #include "AVR.h" 27 #include "AVRMachineFunctionInfo.h" 28 #include "AVRTargetMachine.h" 29 #include "MCTargetDesc/AVRMCTargetDesc.h" 30 31 namespace llvm { 32 33 AVRTargetLowering::AVRTargetLowering(AVRTargetMachine &tm) 34 : TargetLowering(tm) { 35 // Set up the register classes. 36 addRegisterClass(MVT::i8, &AVR::GPR8RegClass); 37 addRegisterClass(MVT::i16, &AVR::DREGSRegClass); 38 39 // Compute derived properties from the register classes. 40 computeRegisterProperties(tm.getSubtargetImpl()->getRegisterInfo()); 41 42 setBooleanContents(ZeroOrOneBooleanContent); 43 setBooleanVectorContents(ZeroOrOneBooleanContent); 44 setSchedulingPreference(Sched::RegPressure); 45 setStackPointerRegisterToSaveRestore(AVR::SP); 46 47 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); 48 setOperationAction(ISD::BlockAddress, MVT::i16, Custom); 49 50 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); 51 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); 52 53 for (MVT VT : MVT::integer_valuetypes()) { 54 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { 55 setLoadExtAction(N, VT, MVT::i1, Promote); 56 setLoadExtAction(N, VT, MVT::i8, Expand); 57 } 58 } 59 60 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 61 62 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types 63 // revert into a sub since we don't have an add with immediate instruction. 64 setOperationAction(ISD::ADD, MVT::i32, Custom); 65 setOperationAction(ISD::ADD, MVT::i64, Custom); 66 67 // our shift instructions are only able to shift 1 bit at a time, so handle 68 // this in a custom way. 69 setOperationAction(ISD::SRA, MVT::i8, Custom); 70 setOperationAction(ISD::SHL, MVT::i8, Custom); 71 setOperationAction(ISD::SRL, MVT::i8, Custom); 72 setOperationAction(ISD::SRA, MVT::i16, Custom); 73 setOperationAction(ISD::SHL, MVT::i16, Custom); 74 setOperationAction(ISD::SRL, MVT::i16, Custom); 75 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); 76 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); 77 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); 78 79 setOperationAction(ISD::BR_CC, MVT::i8, Custom); 80 setOperationAction(ISD::BR_CC, MVT::i16, Custom); 81 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 82 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 83 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 84 85 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); 86 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 87 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 88 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 89 setOperationAction(ISD::SETCC, MVT::i8, Custom); 90 setOperationAction(ISD::SETCC, MVT::i16, Custom); 91 setOperationAction(ISD::SETCC, MVT::i32, Custom); 92 setOperationAction(ISD::SETCC, MVT::i64, Custom); 93 setOperationAction(ISD::SELECT, MVT::i8, Expand); 94 setOperationAction(ISD::SELECT, MVT::i16, Expand); 95 96 setOperationAction(ISD::BSWAP, MVT::i16, Expand); 97 98 // Add support for postincrement and predecrement load/stores. 99 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 100 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 101 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal); 102 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal); 103 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); 104 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); 105 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal); 106 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal); 107 108 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 109 110 setOperationAction(ISD::VASTART, MVT::Other, Custom); 111 setOperationAction(ISD::VAEND, MVT::Other, Expand); 112 setOperationAction(ISD::VAARG, MVT::Other, Expand); 113 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 114 115 // Atomic operations which must be lowered to rtlib calls 116 for (MVT VT : MVT::integer_valuetypes()) { 117 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); 118 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); 119 setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand); 120 setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand); 121 setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand); 122 setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand); 123 setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand); 124 } 125 126 // Division/remainder 127 setOperationAction(ISD::UDIV, MVT::i8, Expand); 128 setOperationAction(ISD::UDIV, MVT::i16, Expand); 129 setOperationAction(ISD::UREM, MVT::i8, Expand); 130 setOperationAction(ISD::UREM, MVT::i16, Expand); 131 setOperationAction(ISD::SDIV, MVT::i8, Expand); 132 setOperationAction(ISD::SDIV, MVT::i16, Expand); 133 setOperationAction(ISD::SREM, MVT::i8, Expand); 134 setOperationAction(ISD::SREM, MVT::i16, Expand); 135 136 // Make division and modulus custom 137 for (MVT VT : MVT::integer_valuetypes()) { 138 setOperationAction(ISD::UDIVREM, VT, Custom); 139 setOperationAction(ISD::SDIVREM, VT, Custom); 140 } 141 142 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co. 143 setOperationAction(ISD::MUL, MVT::i8, Expand); 144 setOperationAction(ISD::MUL, MVT::i16, Expand); 145 146 // Expand 16 bit multiplications. 147 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); 148 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); 149 150 for (MVT VT : MVT::integer_valuetypes()) { 151 setOperationAction(ISD::MULHS, VT, Expand); 152 setOperationAction(ISD::MULHU, VT, Expand); 153 } 154 155 for (MVT VT : MVT::integer_valuetypes()) { 156 setOperationAction(ISD::CTPOP, VT, Expand); 157 setOperationAction(ISD::CTLZ, VT, Expand); 158 setOperationAction(ISD::CTTZ, VT, Expand); 159 } 160 161 for (MVT VT : MVT::integer_valuetypes()) { 162 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 163 // TODO: The generated code is pretty poor. Investigate using the 164 // same "shift and subtract with carry" trick that we do for 165 // extending 8-bit to 16-bit. This may require infrastructure 166 // improvements in how we treat 16-bit "registers" to be feasible. 167 } 168 169 // Division rtlib functions (not supported) 170 setLibcallName(RTLIB::SDIV_I8, nullptr); 171 setLibcallName(RTLIB::SDIV_I16, nullptr); 172 setLibcallName(RTLIB::SDIV_I32, nullptr); 173 setLibcallName(RTLIB::SDIV_I64, nullptr); 174 setLibcallName(RTLIB::SDIV_I128, nullptr); 175 setLibcallName(RTLIB::UDIV_I8, nullptr); 176 setLibcallName(RTLIB::UDIV_I16, nullptr); 177 setLibcallName(RTLIB::UDIV_I32, nullptr); 178 setLibcallName(RTLIB::UDIV_I64, nullptr); 179 setLibcallName(RTLIB::UDIV_I128, nullptr); 180 181 // Modulus rtlib functions (not supported) 182 setLibcallName(RTLIB::SREM_I8, nullptr); 183 setLibcallName(RTLIB::SREM_I16, nullptr); 184 setLibcallName(RTLIB::SREM_I32, nullptr); 185 setLibcallName(RTLIB::SREM_I64, nullptr); 186 setLibcallName(RTLIB::SREM_I128, nullptr); 187 setLibcallName(RTLIB::UREM_I8, nullptr); 188 setLibcallName(RTLIB::UREM_I16, nullptr); 189 setLibcallName(RTLIB::UREM_I32, nullptr); 190 setLibcallName(RTLIB::UREM_I64, nullptr); 191 setLibcallName(RTLIB::UREM_I128, nullptr); 192 193 // Division and modulus rtlib functions 194 setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4"); 195 setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4"); 196 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4"); 197 setLibcallName(RTLIB::SDIVREM_I64, "__divmoddi4"); 198 setLibcallName(RTLIB::SDIVREM_I128, "__divmodti4"); 199 setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4"); 200 setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4"); 201 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4"); 202 setLibcallName(RTLIB::UDIVREM_I64, "__udivmoddi4"); 203 setLibcallName(RTLIB::UDIVREM_I128, "__udivmodti4"); 204 205 // Several of the runtime library functions use a special calling conv 206 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::AVR_BUILTIN); 207 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN); 208 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::AVR_BUILTIN); 209 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN); 210 211 // Trigonometric rtlib functions 212 setLibcallName(RTLIB::SIN_F32, "sin"); 213 setLibcallName(RTLIB::COS_F32, "cos"); 214 215 setMinFunctionAlignment(1); 216 setMinimumJumpTableEntries(INT_MAX); 217 } 218 219 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const { 220 #define NODE(name) \ 221 case AVRISD::name: \ 222 return #name 223 224 switch (Opcode) { 225 default: 226 return nullptr; 227 NODE(RET_FLAG); 228 NODE(RETI_FLAG); 229 NODE(CALL); 230 NODE(WRAPPER); 231 NODE(LSL); 232 NODE(LSR); 233 NODE(ROL); 234 NODE(ROR); 235 NODE(ASR); 236 NODE(LSLLOOP); 237 NODE(LSRLOOP); 238 NODE(ASRLOOP); 239 NODE(BRCOND); 240 NODE(CMP); 241 NODE(CMPC); 242 NODE(TST); 243 NODE(SELECT_CC); 244 #undef NODE 245 } 246 } 247 248 EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, 249 EVT VT) const { 250 assert(!VT.isVector() && "No AVR SetCC type for vectors!"); 251 return MVT::i8; 252 } 253 254 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const { 255 //:TODO: this function has to be completely rewritten to produce optimal 256 // code, for now it's producing very long but correct code. 257 unsigned Opc8; 258 const SDNode *N = Op.getNode(); 259 EVT VT = Op.getValueType(); 260 SDLoc dl(N); 261 262 // Expand non-constant shifts to loops. 263 if (!isa<ConstantSDNode>(N->getOperand(1))) { 264 switch (Op.getOpcode()) { 265 default: 266 llvm_unreachable("Invalid shift opcode!"); 267 case ISD::SHL: 268 return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0), 269 N->getOperand(1)); 270 case ISD::SRL: 271 return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0), 272 N->getOperand(1)); 273 case ISD::SRA: 274 return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0), 275 N->getOperand(1)); 276 } 277 } 278 279 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 280 SDValue Victim = N->getOperand(0); 281 282 switch (Op.getOpcode()) { 283 case ISD::SRA: 284 Opc8 = AVRISD::ASR; 285 break; 286 case ISD::ROTL: 287 Opc8 = AVRISD::ROL; 288 break; 289 case ISD::ROTR: 290 Opc8 = AVRISD::ROR; 291 break; 292 case ISD::SRL: 293 Opc8 = AVRISD::LSR; 294 break; 295 case ISD::SHL: 296 Opc8 = AVRISD::LSL; 297 break; 298 default: 299 llvm_unreachable("Invalid shift opcode"); 300 } 301 302 while (ShiftAmount--) { 303 Victim = DAG.getNode(Opc8, dl, VT, Victim); 304 } 305 306 return Victim; 307 } 308 309 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const { 310 unsigned Opcode = Op->getOpcode(); 311 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && 312 "Invalid opcode for Div/Rem lowering"); 313 bool isSigned = (Opcode == ISD::SDIVREM); 314 EVT VT = Op->getValueType(0); 315 Type *Ty = VT.getTypeForEVT(*DAG.getContext()); 316 317 RTLIB::Libcall LC; 318 switch (VT.getSimpleVT().SimpleTy) { 319 default: 320 llvm_unreachable("Unexpected request for libcall!"); 321 case MVT::i8: 322 LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; 323 break; 324 case MVT::i16: 325 LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; 326 break; 327 case MVT::i32: 328 LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 329 break; 330 case MVT::i64: 331 LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; 332 break; 333 } 334 335 SDValue InChain = DAG.getEntryNode(); 336 337 TargetLowering::ArgListTy Args; 338 TargetLowering::ArgListEntry Entry; 339 for (SDValue const &Value : Op->op_values()) { 340 Entry.Node = Value; 341 Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext()); 342 Entry.isSExt = isSigned; 343 Entry.isZExt = !isSigned; 344 Args.push_back(Entry); 345 } 346 347 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), 348 getPointerTy(DAG.getDataLayout())); 349 350 Type *RetTy = (Type *)StructType::get(Ty, Ty, nullptr); 351 352 SDLoc dl(Op); 353 TargetLowering::CallLoweringInfo CLI(DAG); 354 CLI.setDebugLoc(dl) 355 .setChain(InChain) 356 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) 357 .setInRegister() 358 .setSExtResult(isSigned) 359 .setZExtResult(!isSigned); 360 361 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); 362 return CallInfo.first; 363 } 364 365 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op, 366 SelectionDAG &DAG) const { 367 auto DL = DAG.getDataLayout(); 368 369 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 370 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 371 372 // Create the TargetGlobalAddress node, folding in the constant offset. 373 SDValue Result = 374 DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset); 375 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result); 376 } 377 378 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op, 379 SelectionDAG &DAG) const { 380 auto DL = DAG.getDataLayout(); 381 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 382 383 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL)); 384 385 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result); 386 } 387 388 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC. 389 static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) { 390 switch (CC) { 391 default: 392 llvm_unreachable("Unknown condition code!"); 393 case ISD::SETEQ: 394 return AVRCC::COND_EQ; 395 case ISD::SETNE: 396 return AVRCC::COND_NE; 397 case ISD::SETGE: 398 return AVRCC::COND_GE; 399 case ISD::SETLT: 400 return AVRCC::COND_LT; 401 case ISD::SETUGE: 402 return AVRCC::COND_SH; 403 case ISD::SETULT: 404 return AVRCC::COND_LO; 405 } 406 } 407 408 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for 409 /// the given operands. 410 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 411 SDValue &AVRcc, SelectionDAG &DAG, 412 SDLoc DL) const { 413 SDValue Cmp; 414 EVT VT = LHS.getValueType(); 415 bool UseTest = false; 416 417 switch (CC) { 418 default: 419 break; 420 case ISD::SETLE: { 421 // Swap operands and reverse the branching condition. 422 std::swap(LHS, RHS); 423 CC = ISD::SETGE; 424 break; 425 } 426 case ISD::SETGT: { 427 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { 428 switch (C->getSExtValue()) { 429 case -1: { 430 // When doing lhs > -1 use a tst instruction on the top part of lhs 431 // and use brpl instead of using a chain of cp/cpc. 432 UseTest = true; 433 AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8); 434 break; 435 } 436 case 0: { 437 // Turn lhs > 0 into 0 < lhs since 0 can be materialized with 438 // __zero_reg__ in lhs. 439 RHS = LHS; 440 LHS = DAG.getConstant(0, DL, VT); 441 CC = ISD::SETLT; 442 break; 443 } 444 default: { 445 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows 446 // us to fold the constant into the cmp instruction. 447 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); 448 CC = ISD::SETGE; 449 break; 450 } 451 } 452 break; 453 } 454 // Swap operands and reverse the branching condition. 455 std::swap(LHS, RHS); 456 CC = ISD::SETLT; 457 break; 458 } 459 case ISD::SETLT: { 460 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { 461 switch (C->getSExtValue()) { 462 case 1: { 463 // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with 464 // __zero_reg__ in lhs. 465 RHS = LHS; 466 LHS = DAG.getConstant(0, DL, VT); 467 CC = ISD::SETGE; 468 break; 469 } 470 case 0: { 471 // When doing lhs < 0 use a tst instruction on the top part of lhs 472 // and use brmi instead of using a chain of cp/cpc. 473 UseTest = true; 474 AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8); 475 break; 476 } 477 } 478 } 479 break; 480 } 481 case ISD::SETULE: { 482 // Swap operands and reverse the branching condition. 483 std::swap(LHS, RHS); 484 CC = ISD::SETUGE; 485 break; 486 } 487 case ISD::SETUGT: { 488 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to 489 // fold the constant into the cmp instruction. 490 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { 491 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); 492 CC = ISD::SETUGE; 493 break; 494 } 495 // Swap operands and reverse the branching condition. 496 std::swap(LHS, RHS); 497 CC = ISD::SETULT; 498 break; 499 } 500 } 501 502 // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of 503 // using the default and/or/xor expansion code which is much longer. 504 if (VT == MVT::i32) { 505 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS, 506 DAG.getIntPtrConstant(0, DL)); 507 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS, 508 DAG.getIntPtrConstant(1, DL)); 509 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS, 510 DAG.getIntPtrConstant(0, DL)); 511 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS, 512 DAG.getIntPtrConstant(1, DL)); 513 514 if (UseTest) { 515 // When using tst we only care about the highest part. 516 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi, 517 DAG.getIntPtrConstant(1, DL)); 518 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top); 519 } else { 520 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo); 521 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp); 522 } 523 } else if (VT == MVT::i64) { 524 SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, 525 DAG.getIntPtrConstant(0, DL)); 526 SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, 527 DAG.getIntPtrConstant(1, DL)); 528 529 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, 530 DAG.getIntPtrConstant(0, DL)); 531 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, 532 DAG.getIntPtrConstant(1, DL)); 533 SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1, 534 DAG.getIntPtrConstant(0, DL)); 535 SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1, 536 DAG.getIntPtrConstant(1, DL)); 537 538 SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, 539 DAG.getIntPtrConstant(0, DL)); 540 SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, 541 DAG.getIntPtrConstant(1, DL)); 542 543 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, 544 DAG.getIntPtrConstant(0, DL)); 545 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, 546 DAG.getIntPtrConstant(1, DL)); 547 SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1, 548 DAG.getIntPtrConstant(0, DL)); 549 SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1, 550 DAG.getIntPtrConstant(1, DL)); 551 552 if (UseTest) { 553 // When using tst we only care about the highest part. 554 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3, 555 DAG.getIntPtrConstant(1, DL)); 556 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top); 557 } else { 558 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS0, RHS0); 559 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); 560 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp); 561 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp); 562 } 563 } else if (VT == MVT::i8 || VT == MVT::i16) { 564 if (UseTest) { 565 // When using tst we only care about the highest part. 566 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, 567 (VT == MVT::i8) 568 ? LHS 569 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, 570 LHS, DAG.getIntPtrConstant(1, DL))); 571 } else { 572 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS); 573 } 574 } else { 575 llvm_unreachable("Invalid comparison size"); 576 } 577 578 // When using a test instruction AVRcc is already set. 579 if (!UseTest) { 580 AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8); 581 } 582 583 return Cmp; 584 } 585 586 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 587 SDValue Chain = Op.getOperand(0); 588 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 589 SDValue LHS = Op.getOperand(2); 590 SDValue RHS = Op.getOperand(3); 591 SDValue Dest = Op.getOperand(4); 592 SDLoc dl(Op); 593 594 SDValue TargetCC; 595 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl); 596 597 return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC, 598 Cmp); 599 } 600 601 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 602 SDValue LHS = Op.getOperand(0); 603 SDValue RHS = Op.getOperand(1); 604 SDValue TrueV = Op.getOperand(2); 605 SDValue FalseV = Op.getOperand(3); 606 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 607 SDLoc dl(Op); 608 609 SDValue TargetCC; 610 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl); 611 612 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 613 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp}; 614 615 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops); 616 } 617 618 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 619 SDValue LHS = Op.getOperand(0); 620 SDValue RHS = Op.getOperand(1); 621 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 622 SDLoc DL(Op); 623 624 SDValue TargetCC; 625 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL); 626 627 SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType()); 628 SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType()); 629 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 630 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp}; 631 632 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops); 633 } 634 635 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 636 const MachineFunction &MF = DAG.getMachineFunction(); 637 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); 638 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 639 auto DL = DAG.getDataLayout(); 640 SDLoc dl(Op); 641 642 // Vastart just stores the address of the VarArgsFrameIndex slot into the 643 // memory location argument. 644 SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL)); 645 646 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 647 MachinePointerInfo(SV), 0); 648 } 649 650 SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 651 switch (Op.getOpcode()) { 652 default: 653 llvm_unreachable("Don't know how to custom lower this!"); 654 case ISD::SHL: 655 case ISD::SRA: 656 case ISD::SRL: 657 case ISD::ROTL: 658 case ISD::ROTR: 659 return LowerShifts(Op, DAG); 660 case ISD::GlobalAddress: 661 return LowerGlobalAddress(Op, DAG); 662 case ISD::BlockAddress: 663 return LowerBlockAddress(Op, DAG); 664 case ISD::BR_CC: 665 return LowerBR_CC(Op, DAG); 666 case ISD::SELECT_CC: 667 return LowerSELECT_CC(Op, DAG); 668 case ISD::SETCC: 669 return LowerSETCC(Op, DAG); 670 case ISD::VASTART: 671 return LowerVASTART(Op, DAG); 672 case ISD::SDIVREM: 673 case ISD::UDIVREM: 674 return LowerDivRem(Op, DAG); 675 } 676 677 return SDValue(); 678 } 679 680 /// Replace a node with an illegal result type 681 /// with a new node built out of custom code. 682 void AVRTargetLowering::ReplaceNodeResults(SDNode *N, 683 SmallVectorImpl<SDValue> &Results, 684 SelectionDAG &DAG) const { 685 SDLoc DL(N); 686 687 switch (N->getOpcode()) { 688 case ISD::ADD: { 689 // Convert add (x, imm) into sub (x, -imm). 690 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 691 SDValue Sub = DAG.getNode( 692 ISD::SUB, DL, N->getValueType(0), N->getOperand(0), 693 DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0))); 694 Results.push_back(Sub); 695 } 696 break; 697 } 698 default: { 699 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 700 701 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 702 Results.push_back(Res.getValue(I)); 703 704 break; 705 } 706 } 707 } 708 709 /// Return true if the addressing mode represented 710 /// by AM is legal for this target, for a load/store of the specified type. 711 bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL, 712 const AddrMode &AM, Type *Ty, 713 unsigned AS) const { 714 int64_t Offs = AM.BaseOffs; 715 716 // Allow absolute addresses. 717 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { 718 return true; 719 } 720 721 // Flash memory instructions only allow zero offsets. 722 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) { 723 return false; 724 } 725 726 // Allow reg+<6bit> offset. 727 if (Offs < 0) 728 Offs = -Offs; 729 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) { 730 return true; 731 } 732 733 return false; 734 } 735 736 /// Returns true by value, base pointer and 737 /// offset pointer and addressing mode by reference if the node's address 738 /// can be legally represented as pre-indexed load / store address. 739 bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 740 SDValue &Offset, 741 ISD::MemIndexedMode &AM, 742 SelectionDAG &DAG) const { 743 EVT VT; 744 const SDNode *Op; 745 SDLoc DL(N); 746 747 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 748 VT = LD->getMemoryVT(); 749 Op = LD->getBasePtr().getNode(); 750 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 751 return false; 752 if (AVR::isProgramMemoryAccess(LD)) { 753 return false; 754 } 755 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 756 VT = ST->getMemoryVT(); 757 Op = ST->getBasePtr().getNode(); 758 if (AVR::isProgramMemoryAccess(ST)) { 759 return false; 760 } 761 } else { 762 return false; 763 } 764 765 if (VT != MVT::i8 && VT != MVT::i16) { 766 return false; 767 } 768 769 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { 770 return false; 771 } 772 773 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 774 int RHSC = RHS->getSExtValue(); 775 if (Op->getOpcode() == ISD::SUB) 776 RHSC = -RHSC; 777 778 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) { 779 return false; 780 } 781 782 Base = Op->getOperand(0); 783 Offset = DAG.getConstant(RHSC, DL, MVT::i8); 784 AM = ISD::PRE_DEC; 785 786 return true; 787 } 788 789 return false; 790 } 791 792 /// Returns true by value, base pointer and 793 /// offset pointer and addressing mode by reference if this node can be 794 /// combined with a load / store to form a post-indexed load / store. 795 bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 796 SDValue &Base, 797 SDValue &Offset, 798 ISD::MemIndexedMode &AM, 799 SelectionDAG &DAG) const { 800 EVT VT; 801 SDLoc DL(N); 802 803 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 804 VT = LD->getMemoryVT(); 805 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 806 return false; 807 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 808 VT = ST->getMemoryVT(); 809 if (AVR::isProgramMemoryAccess(ST)) { 810 return false; 811 } 812 } else { 813 return false; 814 } 815 816 if (VT != MVT::i8 && VT != MVT::i16) { 817 return false; 818 } 819 820 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { 821 return false; 822 } 823 824 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 825 int RHSC = RHS->getSExtValue(); 826 if (Op->getOpcode() == ISD::SUB) 827 RHSC = -RHSC; 828 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) { 829 return false; 830 } 831 832 Base = Op->getOperand(0); 833 Offset = DAG.getConstant(RHSC, DL, MVT::i8); 834 AM = ISD::POST_INC; 835 836 return true; 837 } 838 839 return false; 840 } 841 842 bool AVRTargetLowering::isOffsetFoldingLegal( 843 const GlobalAddressSDNode *GA) const { 844 return true; 845 } 846 847 //===----------------------------------------------------------------------===// 848 // Formal Arguments Calling Convention Implementation 849 //===----------------------------------------------------------------------===// 850 851 #include "AVRGenCallingConv.inc" 852 853 /// For each argument in a function store the number of pieces it is composed 854 /// of. 855 static void parseFunctionArgs(const Function *F, const DataLayout *TD, 856 SmallVectorImpl<unsigned> &Out) { 857 for (Argument const &Arg : F->args()) { 858 unsigned Bytes = (TD->getTypeSizeInBits(Arg.getType()) + 7) / 8; 859 Out.push_back((Bytes + 1) / 2); 860 } 861 } 862 863 /// For external symbols there is no function prototype information so we 864 /// have to rely directly on argument sizes. 865 static void parseExternFuncCallArgs(const SmallVectorImpl<ISD::OutputArg> &In, 866 SmallVectorImpl<unsigned> &Out) { 867 for (unsigned i = 0, e = In.size(); i != e;) { 868 unsigned Size = 0; 869 unsigned Offset = 0; 870 while ((i != e) && (In[i].PartOffset == Offset)) { 871 Offset += In[i].VT.getStoreSize(); 872 ++i; 873 ++Size; 874 } 875 Out.push_back(Size); 876 } 877 } 878 879 static StringRef getFunctionName(TargetLowering::CallLoweringInfo &CLI) { 880 SDValue Callee = CLI.Callee; 881 882 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee)) { 883 return G->getSymbol(); 884 } 885 886 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 887 return G->getGlobal()->getName(); 888 } 889 890 llvm_unreachable("don't know how to get the name for this callee"); 891 } 892 893 /// Analyze incoming and outgoing function arguments. We need custom C++ code 894 /// to handle special constraints in the ABI like reversing the order of the 895 /// pieces of splitted arguments. In addition, all pieces of a certain argument 896 /// have to be passed either using registers or the stack but never mixing both. 897 static void analyzeStandardArguments(TargetLowering::CallLoweringInfo *CLI, 898 const Function *F, const DataLayout *TD, 899 const SmallVectorImpl<ISD::OutputArg> *Outs, 900 const SmallVectorImpl<ISD::InputArg> *Ins, 901 CallingConv::ID CallConv, 902 SmallVectorImpl<CCValAssign> &ArgLocs, 903 CCState &CCInfo, bool IsCall, bool IsVarArg) { 904 static const MCPhysReg RegList8[] = {AVR::R24, AVR::R22, AVR::R20, 905 AVR::R18, AVR::R16, AVR::R14, 906 AVR::R12, AVR::R10, AVR::R8}; 907 static const MCPhysReg RegList16[] = {AVR::R25R24, AVR::R23R22, AVR::R21R20, 908 AVR::R19R18, AVR::R17R16, AVR::R15R14, 909 AVR::R13R12, AVR::R11R10, AVR::R9R8}; 910 if (IsVarArg) { 911 // Variadic functions do not need all the analisys below. 912 if (IsCall) { 913 CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_Vararg); 914 } else { 915 CCInfo.AnalyzeFormalArguments(*Ins, ArgCC_AVR_Vararg); 916 } 917 return; 918 } 919 920 // Fill in the Args array which will contain original argument sizes. 921 SmallVector<unsigned, 8> Args; 922 if (IsCall) { 923 parseExternFuncCallArgs(*Outs, Args); 924 } else { 925 assert(F != nullptr && "function should not be null"); 926 parseFunctionArgs(F, TD, Args); 927 } 928 929 unsigned RegsLeft = array_lengthof(RegList8), ValNo = 0; 930 // Variadic functions always use the stack. 931 bool UsesStack = false; 932 for (unsigned i = 0, pos = 0, e = Args.size(); i != e; ++i) { 933 unsigned Size = Args[i]; 934 MVT LocVT = (IsCall) ? (*Outs)[pos].VT : (*Ins)[pos].VT; 935 936 // If we have plenty of regs to pass the whole argument do it. 937 if (!UsesStack && (Size <= RegsLeft)) { 938 const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8; 939 940 for (unsigned j = 0; j != Size; ++j) { 941 unsigned Reg = CCInfo.AllocateReg( 942 ArrayRef<MCPhysReg>(RegList, array_lengthof(RegList8))); 943 CCInfo.addLoc( 944 CCValAssign::getReg(ValNo++, LocVT, Reg, LocVT, CCValAssign::Full)); 945 --RegsLeft; 946 } 947 948 // Reverse the order of the pieces to agree with the "big endian" format 949 // required in the calling convention ABI. 950 std::reverse(ArgLocs.begin() + pos, ArgLocs.begin() + pos + Size); 951 } else { 952 // Pass the rest of arguments using the stack. 953 UsesStack = true; 954 for (unsigned j = 0; j != Size; ++j) { 955 unsigned Offset = CCInfo.AllocateStack( 956 TD->getTypeAllocSize(EVT(LocVT).getTypeForEVT(CCInfo.getContext())), 957 TD->getABITypeAlignment( 958 EVT(LocVT).getTypeForEVT(CCInfo.getContext()))); 959 CCInfo.addLoc(CCValAssign::getMem(ValNo++, LocVT, Offset, LocVT, 960 CCValAssign::Full)); 961 } 962 } 963 pos += Size; 964 } 965 } 966 967 static void analyzeBuiltinArguments(TargetLowering::CallLoweringInfo &CLI, 968 const Function *F, const DataLayout *TD, 969 const SmallVectorImpl<ISD::OutputArg> *Outs, 970 const SmallVectorImpl<ISD::InputArg> *Ins, 971 CallingConv::ID CallConv, 972 SmallVectorImpl<CCValAssign> &ArgLocs, 973 CCState &CCInfo, bool IsCall, bool IsVarArg) { 974 StringRef FuncName = getFunctionName(CLI); 975 976 if (FuncName.startswith("__udivmod") || FuncName.startswith("__divmod")) { 977 CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_BUILTIN_DIV); 978 } else { 979 analyzeStandardArguments(&CLI, F, TD, Outs, Ins, 980 CallConv, ArgLocs, CCInfo, 981 IsCall, IsVarArg); 982 } 983 } 984 985 static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, 986 const Function *F, const DataLayout *TD, 987 const SmallVectorImpl<ISD::OutputArg> *Outs, 988 const SmallVectorImpl<ISD::InputArg> *Ins, 989 CallingConv::ID CallConv, 990 SmallVectorImpl<CCValAssign> &ArgLocs, 991 CCState &CCInfo, bool IsCall, bool IsVarArg) { 992 switch (CallConv) { 993 case CallingConv::AVR_BUILTIN: { 994 analyzeBuiltinArguments(*CLI, F, TD, Outs, Ins, 995 CallConv, ArgLocs, CCInfo, 996 IsCall, IsVarArg); 997 return; 998 } 999 default: { 1000 analyzeStandardArguments(CLI, F, TD, Outs, Ins, 1001 CallConv, ArgLocs, CCInfo, 1002 IsCall, IsVarArg); 1003 return; 1004 } 1005 } 1006 } 1007 1008 SDValue AVRTargetLowering::LowerFormalArguments( 1009 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1010 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, 1011 SmallVectorImpl<SDValue> &InVals) const { 1012 MachineFunction &MF = DAG.getMachineFunction(); 1013 MachineFrameInfo &MFI = MF.getFrameInfo(); 1014 auto DL = DAG.getDataLayout(); 1015 1016 // Assign locations to all of the incoming arguments. 1017 SmallVector<CCValAssign, 16> ArgLocs; 1018 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1019 *DAG.getContext()); 1020 1021 analyzeArguments(nullptr, MF.getFunction(), &DL, 0, &Ins, CallConv, ArgLocs, CCInfo, 1022 false, isVarArg); 1023 1024 SDValue ArgValue; 1025 for (CCValAssign &VA : ArgLocs) { 1026 1027 // Arguments stored on registers. 1028 if (VA.isRegLoc()) { 1029 EVT RegVT = VA.getLocVT(); 1030 const TargetRegisterClass *RC; 1031 if (RegVT == MVT::i8) { 1032 RC = &AVR::GPR8RegClass; 1033 } else if (RegVT == MVT::i16) { 1034 RC = &AVR::DREGSRegClass; 1035 } else { 1036 llvm_unreachable("Unknown argument type!"); 1037 } 1038 1039 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1040 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1041 1042 // :NOTE: Clang should not promote any i8 into i16 but for safety the 1043 // following code will handle zexts or sexts generated by other 1044 // front ends. Otherwise: 1045 // If this is an 8 bit value, it is really passed promoted 1046 // to 16 bits. Insert an assert[sz]ext to capture this, then 1047 // truncate to the right size. 1048 switch (VA.getLocInfo()) { 1049 default: 1050 llvm_unreachable("Unknown loc info!"); 1051 case CCValAssign::Full: 1052 break; 1053 case CCValAssign::BCvt: 1054 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1055 break; 1056 case CCValAssign::SExt: 1057 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1058 DAG.getValueType(VA.getValVT())); 1059 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1060 break; 1061 case CCValAssign::ZExt: 1062 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1063 DAG.getValueType(VA.getValVT())); 1064 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1065 break; 1066 } 1067 1068 InVals.push_back(ArgValue); 1069 } else { 1070 // Sanity check. 1071 assert(VA.isMemLoc()); 1072 1073 EVT LocVT = VA.getLocVT(); 1074 1075 // Create the frame index object for this incoming parameter. 1076 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 1077 VA.getLocMemOffset(), true); 1078 1079 // Create the SelectionDAG nodes corresponding to a load 1080 // from this parameter. 1081 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL)); 1082 InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN, 1083 MachinePointerInfo::getFixedStack(MF, FI), 1084 0)); 1085 } 1086 } 1087 1088 // If the function takes variable number of arguments, make a frame index for 1089 // the start of the first vararg value... for expansion of llvm.va_start. 1090 if (isVarArg) { 1091 unsigned StackSize = CCInfo.getNextStackOffset(); 1092 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); 1093 1094 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true)); 1095 } 1096 1097 return Chain; 1098 } 1099 1100 //===----------------------------------------------------------------------===// 1101 // Call Calling Convention Implementation 1102 //===----------------------------------------------------------------------===// 1103 1104 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 1105 SmallVectorImpl<SDValue> &InVals) const { 1106 SelectionDAG &DAG = CLI.DAG; 1107 SDLoc &DL = CLI.DL; 1108 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 1109 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 1110 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 1111 SDValue Chain = CLI.Chain; 1112 SDValue Callee = CLI.Callee; 1113 bool &isTailCall = CLI.IsTailCall; 1114 CallingConv::ID CallConv = CLI.CallConv; 1115 bool isVarArg = CLI.IsVarArg; 1116 1117 MachineFunction &MF = DAG.getMachineFunction(); 1118 1119 // AVR does not yet support tail call optimization. 1120 isTailCall = false; 1121 1122 // Analyze operands of the call, assigning locations to each operand. 1123 SmallVector<CCValAssign, 16> ArgLocs; 1124 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1125 *DAG.getContext()); 1126 1127 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1128 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1129 // node so that legalize doesn't hack it. 1130 const Function *F = nullptr; 1131 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1132 const GlobalValue *GV = G->getGlobal(); 1133 1134 F = cast<Function>(GV); 1135 Callee = 1136 DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout())); 1137 } else if (const ExternalSymbolSDNode *ES = 1138 dyn_cast<ExternalSymbolSDNode>(Callee)) { 1139 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), 1140 getPointerTy(DAG.getDataLayout())); 1141 } 1142 1143 analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo, 1144 true, isVarArg); 1145 1146 // Get a count of how many bytes are to be pushed on the stack. 1147 unsigned NumBytes = CCInfo.getNextStackOffset(); 1148 1149 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), 1150 DL); 1151 1152 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1153 1154 // First, walk the register assignments, inserting copies. 1155 unsigned AI, AE; 1156 bool HasStackArgs = false; 1157 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) { 1158 CCValAssign &VA = ArgLocs[AI]; 1159 EVT RegVT = VA.getLocVT(); 1160 SDValue Arg = OutVals[AI]; 1161 1162 // Promote the value if needed. With Clang this should not happen. 1163 switch (VA.getLocInfo()) { 1164 default: 1165 llvm_unreachable("Unknown loc info!"); 1166 case CCValAssign::Full: 1167 break; 1168 case CCValAssign::SExt: 1169 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); 1170 break; 1171 case CCValAssign::ZExt: 1172 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); 1173 break; 1174 case CCValAssign::AExt: 1175 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); 1176 break; 1177 case CCValAssign::BCvt: 1178 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg); 1179 break; 1180 } 1181 1182 // Stop when we encounter a stack argument, we need to process them 1183 // in reverse order in the loop below. 1184 if (VA.isMemLoc()) { 1185 HasStackArgs = true; 1186 break; 1187 } 1188 1189 // Arguments that can be passed on registers must be kept in the RegsToPass 1190 // vector. 1191 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1192 } 1193 1194 // Second, stack arguments have to walked in reverse order by inserting 1195 // chained stores, this ensures their order is not changed by the scheduler 1196 // and that the push instruction sequence generated is correct, otherwise they 1197 // can be freely intermixed. 1198 if (HasStackArgs) { 1199 for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) { 1200 unsigned Loc = AI - 1; 1201 CCValAssign &VA = ArgLocs[Loc]; 1202 SDValue Arg = OutVals[Loc]; 1203 1204 assert(VA.isMemLoc()); 1205 1206 // SP points to one stack slot further so add one to adjust it. 1207 SDValue PtrOff = DAG.getNode( 1208 ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), 1209 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())), 1210 DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL)); 1211 1212 Chain = 1213 DAG.getStore(Chain, DL, Arg, PtrOff, 1214 MachinePointerInfo::getStack(MF, VA.getLocMemOffset()), 1215 0); 1216 } 1217 } 1218 1219 // Build a sequence of copy-to-reg nodes chained together with token chain and 1220 // flag operands which copy the outgoing args into registers. The InFlag in 1221 // necessary since all emited instructions must be stuck together. 1222 SDValue InFlag; 1223 for (auto Reg : RegsToPass) { 1224 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag); 1225 InFlag = Chain.getValue(1); 1226 } 1227 1228 // Returns a chain & a flag for retval copy to use. 1229 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1230 SmallVector<SDValue, 8> Ops; 1231 Ops.push_back(Chain); 1232 Ops.push_back(Callee); 1233 1234 // Add argument registers to the end of the list so that they are known live 1235 // into the call. 1236 for (auto Reg : RegsToPass) { 1237 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); 1238 } 1239 1240 // Add a register mask operand representing the call-preserved registers. 1241 const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine(); 1242 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo(); 1243 const uint32_t *Mask = 1244 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv); 1245 assert(Mask && "Missing call preserved mask for calling convention"); 1246 Ops.push_back(DAG.getRegisterMask(Mask)); 1247 1248 if (InFlag.getNode()) { 1249 Ops.push_back(InFlag); 1250 } 1251 1252 Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops); 1253 InFlag = Chain.getValue(1); 1254 1255 // Create the CALLSEQ_END node. 1256 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), 1257 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 1258 1259 if (!Ins.empty()) { 1260 InFlag = Chain.getValue(1); 1261 } 1262 1263 // Handle result values, copying them out of physregs into vregs that we 1264 // return. 1265 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG, 1266 InVals); 1267 } 1268 1269 /// Lower the result values of a call into the 1270 /// appropriate copies out of appropriate physical registers. 1271 /// 1272 SDValue AVRTargetLowering::LowerCallResult( 1273 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, 1274 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, 1275 SmallVectorImpl<SDValue> &InVals) const { 1276 1277 // Assign locations to each value returned by this call. 1278 SmallVector<CCValAssign, 16> RVLocs; 1279 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1280 *DAG.getContext()); 1281 1282 // Handle runtime calling convs. 1283 auto CCFunction = CCAssignFnForReturn(CallConv); 1284 CCInfo.AnalyzeCallResult(Ins, CCFunction); 1285 1286 if (CallConv != CallingConv::AVR_BUILTIN && RVLocs.size() > 1) { 1287 // Reverse splitted return values to get the "big endian" format required 1288 // to agree with the calling convention ABI. 1289 std::reverse(RVLocs.begin(), RVLocs.end()); 1290 } 1291 1292 // Copy all of the result registers out of their specified physreg. 1293 for (CCValAssign const &RVLoc : RVLocs) { 1294 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(), 1295 InFlag) 1296 .getValue(1); 1297 InFlag = Chain.getValue(2); 1298 InVals.push_back(Chain.getValue(0)); 1299 } 1300 1301 return Chain; 1302 } 1303 1304 //===----------------------------------------------------------------------===// 1305 // Return Value Calling Convention Implementation 1306 //===----------------------------------------------------------------------===// 1307 1308 CCAssignFn *AVRTargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const { 1309 switch (CC) { 1310 case CallingConv::AVR_BUILTIN: 1311 return RetCC_AVR_BUILTIN; 1312 default: 1313 return RetCC_AVR; 1314 } 1315 } 1316 1317 bool 1318 AVRTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1319 MachineFunction &MF, bool isVarArg, 1320 const SmallVectorImpl<ISD::OutputArg> &Outs, 1321 LLVMContext &Context) const 1322 { 1323 SmallVector<CCValAssign, 16> RVLocs; 1324 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); 1325 1326 auto CCFunction = CCAssignFnForReturn(CallConv); 1327 return CCInfo.CheckReturn(Outs, CCFunction); 1328 } 1329 1330 SDValue 1331 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 1332 bool isVarArg, 1333 const SmallVectorImpl<ISD::OutputArg> &Outs, 1334 const SmallVectorImpl<SDValue> &OutVals, 1335 const SDLoc &dl, SelectionDAG &DAG) const { 1336 // CCValAssign - represent the assignment of the return value to locations. 1337 SmallVector<CCValAssign, 16> RVLocs; 1338 1339 // CCState - Info about the registers and stack slot. 1340 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1341 *DAG.getContext()); 1342 1343 // Analyze return values. 1344 auto CCFunction = CCAssignFnForReturn(CallConv); 1345 CCInfo.AnalyzeReturn(Outs, CCFunction); 1346 1347 // If this is the first return lowered for this function, add the regs to 1348 // the liveout set for the function. 1349 MachineFunction &MF = DAG.getMachineFunction(); 1350 unsigned e = RVLocs.size(); 1351 1352 // Reverse splitted return values to get the "big endian" format required 1353 // to agree with the calling convention ABI. 1354 if (e > 1) { 1355 std::reverse(RVLocs.begin(), RVLocs.end()); 1356 } 1357 1358 SDValue Flag; 1359 SmallVector<SDValue, 4> RetOps(1, Chain); 1360 // Copy the result values into the output registers. 1361 for (unsigned i = 0; i != e; ++i) { 1362 CCValAssign &VA = RVLocs[i]; 1363 assert(VA.isRegLoc() && "Can only return in registers!"); 1364 1365 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 1366 1367 // Guarantee that all emitted copies are stuck together with flags. 1368 Flag = Chain.getValue(1); 1369 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 1370 } 1371 1372 // Don't emit the ret/reti instruction when the naked attribute is present in 1373 // the function being compiled. 1374 if (MF.getFunction()->getAttributes().hasAttribute( 1375 AttributeSet::FunctionIndex, Attribute::Naked)) { 1376 return Chain; 1377 } 1378 1379 unsigned RetOpc = 1380 (CallConv == CallingConv::AVR_INTR || CallConv == CallingConv::AVR_SIGNAL) 1381 ? AVRISD::RETI_FLAG 1382 : AVRISD::RET_FLAG; 1383 1384 RetOps[0] = Chain; // Update chain. 1385 1386 if (Flag.getNode()) { 1387 RetOps.push_back(Flag); 1388 } 1389 1390 return DAG.getNode(RetOpc, dl, MVT::Other, RetOps); 1391 } 1392 1393 //===----------------------------------------------------------------------===// 1394 // Custom Inserters 1395 //===----------------------------------------------------------------------===// 1396 1397 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI, 1398 MachineBasicBlock *BB) const { 1399 unsigned Opc; 1400 const TargetRegisterClass *RC; 1401 MachineFunction *F = BB->getParent(); 1402 MachineRegisterInfo &RI = F->getRegInfo(); 1403 const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine(); 1404 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo(); 1405 DebugLoc dl = MI.getDebugLoc(); 1406 1407 switch (MI.getOpcode()) { 1408 default: 1409 llvm_unreachable("Invalid shift opcode!"); 1410 case AVR::Lsl8: 1411 Opc = AVR::LSLRd; 1412 RC = &AVR::GPR8RegClass; 1413 break; 1414 case AVR::Lsl16: 1415 Opc = AVR::LSLWRd; 1416 RC = &AVR::DREGSRegClass; 1417 break; 1418 case AVR::Asr8: 1419 Opc = AVR::ASRRd; 1420 RC = &AVR::GPR8RegClass; 1421 break; 1422 case AVR::Asr16: 1423 Opc = AVR::ASRWRd; 1424 RC = &AVR::DREGSRegClass; 1425 break; 1426 case AVR::Lsr8: 1427 Opc = AVR::LSRRd; 1428 RC = &AVR::GPR8RegClass; 1429 break; 1430 case AVR::Lsr16: 1431 Opc = AVR::LSRWRd; 1432 RC = &AVR::DREGSRegClass; 1433 break; 1434 } 1435 1436 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1437 MachineFunction::iterator I = BB->getParent()->begin(); 1438 ++I; 1439 1440 // Create loop block. 1441 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); 1442 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); 1443 1444 F->insert(I, LoopBB); 1445 F->insert(I, RemBB); 1446 1447 // Update machine-CFG edges by transferring all successors of the current 1448 // block to the block containing instructions after shift. 1449 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), 1450 BB->end()); 1451 RemBB->transferSuccessorsAndUpdatePHIs(BB); 1452 1453 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB. 1454 BB->addSuccessor(LoopBB); 1455 BB->addSuccessor(RemBB); 1456 LoopBB->addSuccessor(RemBB); 1457 LoopBB->addSuccessor(LoopBB); 1458 1459 unsigned ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass); 1460 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass); 1461 unsigned ShiftReg = RI.createVirtualRegister(RC); 1462 unsigned ShiftReg2 = RI.createVirtualRegister(RC); 1463 unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg(); 1464 unsigned SrcReg = MI.getOperand(1).getReg(); 1465 unsigned DstReg = MI.getOperand(0).getReg(); 1466 1467 // BB: 1468 // cp 0, N 1469 // breq RemBB 1470 BuildMI(BB, dl, TII.get(AVR::CPRdRr)).addReg(ShiftAmtSrcReg).addReg(AVR::R0); 1471 BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB); 1472 1473 // LoopBB: 1474 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB] 1475 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB] 1476 // ShiftReg2 = shift ShiftReg 1477 // ShiftAmt2 = ShiftAmt - 1; 1478 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg) 1479 .addReg(SrcReg) 1480 .addMBB(BB) 1481 .addReg(ShiftReg2) 1482 .addMBB(LoopBB); 1483 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg) 1484 .addReg(ShiftAmtSrcReg) 1485 .addMBB(BB) 1486 .addReg(ShiftAmtReg2) 1487 .addMBB(LoopBB); 1488 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg); 1489 BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2) 1490 .addReg(ShiftAmtReg) 1491 .addImm(1); 1492 BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB); 1493 1494 // RemBB: 1495 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB] 1496 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg) 1497 .addReg(SrcReg) 1498 .addMBB(BB) 1499 .addReg(ShiftReg2) 1500 .addMBB(LoopBB); 1501 1502 MI.eraseFromParent(); // The pseudo instruction is gone now. 1503 return RemBB; 1504 } 1505 1506 static bool isCopyMulResult(MachineBasicBlock::iterator const &I) { 1507 if (I->getOpcode() == AVR::COPY) { 1508 unsigned SrcReg = I->getOperand(1).getReg(); 1509 return (SrcReg == AVR::R0 || SrcReg == AVR::R1); 1510 } 1511 1512 return false; 1513 } 1514 1515 // The mul instructions wreak havock on our zero_reg R1. We need to clear it 1516 // after the result has been evacuated. This is probably not the best way to do 1517 // it, but it works for now. 1518 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI, 1519 MachineBasicBlock *BB) const { 1520 const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine(); 1521 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo(); 1522 MachineBasicBlock::iterator I(MI); 1523 ++I; // in any case insert *after* the mul instruction 1524 if (isCopyMulResult(I)) 1525 ++I; 1526 if (isCopyMulResult(I)) 1527 ++I; 1528 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1) 1529 .addReg(AVR::R1) 1530 .addReg(AVR::R1); 1531 return BB; 1532 } 1533 1534 MachineBasicBlock * 1535 AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1536 MachineBasicBlock *MBB) const { 1537 int Opc = MI.getOpcode(); 1538 1539 // Pseudo shift instructions with a non constant shift amount are expanded 1540 // into a loop. 1541 switch (Opc) { 1542 case AVR::Lsl8: 1543 case AVR::Lsl16: 1544 case AVR::Lsr8: 1545 case AVR::Lsr16: 1546 case AVR::Asr8: 1547 case AVR::Asr16: 1548 return insertShift(MI, MBB); 1549 case AVR::MULRdRr: 1550 case AVR::MULSRdRr: 1551 return insertMul(MI, MBB); 1552 } 1553 1554 assert((Opc == AVR::Select16 || Opc == AVR::Select8) && 1555 "Unexpected instr type to insert"); 1556 1557 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent() 1558 ->getParent() 1559 ->getSubtarget() 1560 .getInstrInfo(); 1561 DebugLoc dl = MI.getDebugLoc(); 1562 1563 // To "insert" a SELECT instruction, we insert the diamond 1564 // control-flow pattern. The incoming instruction knows the 1565 // destination vreg to set, the condition code register to branch 1566 // on, the true/false values to select between, and a branch opcode 1567 // to use. 1568 1569 MachineFunction *MF = MBB->getParent(); 1570 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 1571 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1572 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1573 1574 MachineFunction::iterator I = MBB->getParent()->begin(); 1575 ++I; 1576 MF->insert(I, trueMBB); 1577 MF->insert(I, falseMBB); 1578 1579 // Transfer remaining instructions and all successors of the current 1580 // block to the block which will contain the Phi node for the 1581 // select. 1582 trueMBB->splice(trueMBB->begin(), MBB, 1583 std::next(MachineBasicBlock::iterator(MI)), MBB->end()); 1584 trueMBB->transferSuccessorsAndUpdatePHIs(MBB); 1585 1586 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm(); 1587 BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB); 1588 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB); 1589 MBB->addSuccessor(falseMBB); 1590 MBB->addSuccessor(trueMBB); 1591 1592 // Unconditionally flow back to the true block 1593 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB); 1594 falseMBB->addSuccessor(trueMBB); 1595 1596 // Set up the Phi node to determine where we came from 1597 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg()) 1598 .addReg(MI.getOperand(1).getReg()) 1599 .addMBB(MBB) 1600 .addReg(MI.getOperand(2).getReg()) 1601 .addMBB(falseMBB) ; 1602 1603 MI.eraseFromParent(); // The pseudo instruction is gone now. 1604 return trueMBB; 1605 } 1606 1607 //===----------------------------------------------------------------------===// 1608 // Inline Asm Support 1609 //===----------------------------------------------------------------------===// 1610 1611 AVRTargetLowering::ConstraintType 1612 AVRTargetLowering::getConstraintType(StringRef Constraint) const { 1613 if (Constraint.size() == 1) { 1614 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html 1615 switch (Constraint[0]) { 1616 case 'a': // Simple upper registers 1617 case 'b': // Base pointer registers pairs 1618 case 'd': // Upper register 1619 case 'l': // Lower registers 1620 case 'e': // Pointer register pairs 1621 case 'q': // Stack pointer register 1622 case 'r': // Any register 1623 case 'w': // Special upper register pairs 1624 return C_RegisterClass; 1625 case 't': // Temporary register 1626 case 'x': case 'X': // Pointer register pair X 1627 case 'y': case 'Y': // Pointer register pair Y 1628 case 'z': case 'Z': // Pointer register pair Z 1629 return C_Register; 1630 case 'Q': // A memory address based on Y or Z pointer with displacement. 1631 return C_Memory; 1632 case 'G': // Floating point constant 1633 case 'I': // 6-bit positive integer constant 1634 case 'J': // 6-bit negative integer constant 1635 case 'K': // Integer constant (Range: 2) 1636 case 'L': // Integer constant (Range: 0) 1637 case 'M': // 8-bit integer constant 1638 case 'N': // Integer constant (Range: -1) 1639 case 'O': // Integer constant (Range: 8, 16, 24) 1640 case 'P': // Integer constant (Range: 1) 1641 case 'R': // Integer constant (Range: -6 to 5)x 1642 return C_Other; 1643 default: 1644 break; 1645 } 1646 } 1647 1648 return TargetLowering::getConstraintType(Constraint); 1649 } 1650 1651 unsigned 1652 AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const { 1653 // Not sure if this is actually the right thing to do, but we got to do 1654 // *something* [agnat] 1655 switch (ConstraintCode[0]) { 1656 case 'Q': 1657 return InlineAsm::Constraint_Q; 1658 } 1659 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 1660 } 1661 1662 AVRTargetLowering::ConstraintWeight 1663 AVRTargetLowering::getSingleConstraintMatchWeight( 1664 AsmOperandInfo &info, const char *constraint) const { 1665 ConstraintWeight weight = CW_Invalid; 1666 Value *CallOperandVal = info.CallOperandVal; 1667 1668 // If we don't have a value, we can't do a match, 1669 // but allow it at the lowest weight. 1670 // (this behaviour has been copied from the ARM backend) 1671 if (!CallOperandVal) { 1672 return CW_Default; 1673 } 1674 1675 // Look at the constraint type. 1676 switch (*constraint) { 1677 default: 1678 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 1679 break; 1680 case 'd': 1681 case 'r': 1682 case 'l': 1683 weight = CW_Register; 1684 break; 1685 case 'a': 1686 case 'b': 1687 case 'e': 1688 case 'q': 1689 case 't': 1690 case 'w': 1691 case 'x': case 'X': 1692 case 'y': case 'Y': 1693 case 'z': case 'Z': 1694 weight = CW_SpecificReg; 1695 break; 1696 case 'G': 1697 if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) { 1698 if (C->isZero()) { 1699 weight = CW_Constant; 1700 } 1701 } 1702 break; 1703 case 'I': 1704 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1705 if (isUInt<6>(C->getZExtValue())) { 1706 weight = CW_Constant; 1707 } 1708 } 1709 break; 1710 case 'J': 1711 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1712 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) { 1713 weight = CW_Constant; 1714 } 1715 } 1716 break; 1717 case 'K': 1718 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1719 if (C->getZExtValue() == 2) { 1720 weight = CW_Constant; 1721 } 1722 } 1723 break; 1724 case 'L': 1725 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1726 if (C->getZExtValue() == 0) { 1727 weight = CW_Constant; 1728 } 1729 } 1730 break; 1731 case 'M': 1732 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1733 if (isUInt<8>(C->getZExtValue())) { 1734 weight = CW_Constant; 1735 } 1736 } 1737 break; 1738 case 'N': 1739 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1740 if (C->getSExtValue() == -1) { 1741 weight = CW_Constant; 1742 } 1743 } 1744 break; 1745 case 'O': 1746 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1747 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) || 1748 (C->getZExtValue() == 24)) { 1749 weight = CW_Constant; 1750 } 1751 } 1752 break; 1753 case 'P': 1754 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1755 if (C->getZExtValue() == 1) { 1756 weight = CW_Constant; 1757 } 1758 } 1759 break; 1760 case 'R': 1761 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1762 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) { 1763 weight = CW_Constant; 1764 } 1765 } 1766 break; 1767 case 'Q': 1768 weight = CW_Memory; 1769 break; 1770 } 1771 1772 return weight; 1773 } 1774 1775 std::pair<unsigned, const TargetRegisterClass *> 1776 AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 1777 StringRef Constraint, 1778 MVT VT) const { 1779 auto STI = static_cast<const AVRTargetMachine &>(this->getTargetMachine()) 1780 .getSubtargetImpl(); 1781 1782 // We only support i8 and i16. 1783 // 1784 //:FIXME: remove this assert for now since it gets sometimes executed 1785 // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type."); 1786 1787 if (Constraint.size() == 1) { 1788 switch (Constraint[0]) { 1789 case 'a': // Simple upper registers r16..r23. 1790 return std::make_pair(0U, &AVR::LD8loRegClass); 1791 case 'b': // Base pointer registers: y, z. 1792 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass); 1793 case 'd': // Upper registers r16..r31. 1794 return std::make_pair(0U, &AVR::LD8RegClass); 1795 case 'l': // Lower registers r0..r15. 1796 return std::make_pair(0U, &AVR::GPR8loRegClass); 1797 case 'e': // Pointer register pairs: x, y, z. 1798 return std::make_pair(0U, &AVR::PTRREGSRegClass); 1799 case 'q': // Stack pointer register: SPH:SPL. 1800 return std::make_pair(0U, &AVR::GPRSPRegClass); 1801 case 'r': // Any register: r0..r31. 1802 if (VT == MVT::i8) 1803 return std::make_pair(0U, &AVR::GPR8RegClass); 1804 1805 assert(VT == MVT::i16 && "inline asm constraint too large"); 1806 return std::make_pair(0U, &AVR::DREGSRegClass); 1807 case 't': // Temporary register: r0. 1808 return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass); 1809 case 'w': // Special upper register pairs: r24, r26, r28, r30. 1810 return std::make_pair(0U, &AVR::IWREGSRegClass); 1811 case 'x': // Pointer register pair X: r27:r26. 1812 case 'X': 1813 return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass); 1814 case 'y': // Pointer register pair Y: r29:r28. 1815 case 'Y': 1816 return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass); 1817 case 'z': // Pointer register pair Z: r31:r30. 1818 case 'Z': 1819 return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass); 1820 default: 1821 break; 1822 } 1823 } 1824 1825 return TargetLowering::getRegForInlineAsmConstraint(STI->getRegisterInfo(), 1826 Constraint, VT); 1827 } 1828 1829 void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 1830 std::string &Constraint, 1831 std::vector<SDValue> &Ops, 1832 SelectionDAG &DAG) const { 1833 SDValue Result(0, 0); 1834 SDLoc DL(Op); 1835 EVT Ty = Op.getValueType(); 1836 1837 // Currently only support length 1 constraints. 1838 if (Constraint.length() != 1) { 1839 return; 1840 } 1841 1842 char ConstraintLetter = Constraint[0]; 1843 switch (ConstraintLetter) { 1844 default: 1845 break; 1846 // Deal with integers first: 1847 case 'I': 1848 case 'J': 1849 case 'K': 1850 case 'L': 1851 case 'M': 1852 case 'N': 1853 case 'O': 1854 case 'P': 1855 case 'R': { 1856 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1857 if (!C) { 1858 return; 1859 } 1860 1861 int64_t CVal64 = C->getSExtValue(); 1862 uint64_t CUVal64 = C->getZExtValue(); 1863 switch (ConstraintLetter) { 1864 case 'I': // 0..63 1865 if (!isUInt<6>(CUVal64)) 1866 return; 1867 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 1868 break; 1869 case 'J': // -63..0 1870 if (CVal64 < -63 || CVal64 > 0) 1871 return; 1872 Result = DAG.getTargetConstant(CVal64, DL, Ty); 1873 break; 1874 case 'K': // 2 1875 if (CUVal64 != 2) 1876 return; 1877 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 1878 break; 1879 case 'L': // 0 1880 if (CUVal64 != 0) 1881 return; 1882 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 1883 break; 1884 case 'M': // 0..255 1885 if (!isUInt<8>(CUVal64)) 1886 return; 1887 // i8 type may be printed as a negative number, 1888 // e.g. 254 would be printed as -2, 1889 // so we force it to i16 at least. 1890 if (Ty.getSimpleVT() == MVT::i8) { 1891 Ty = MVT::i16; 1892 } 1893 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 1894 break; 1895 case 'N': // -1 1896 if (CVal64 != -1) 1897 return; 1898 Result = DAG.getTargetConstant(CVal64, DL, Ty); 1899 break; 1900 case 'O': // 8, 16, 24 1901 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24) 1902 return; 1903 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 1904 break; 1905 case 'P': // 1 1906 if (CUVal64 != 1) 1907 return; 1908 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 1909 break; 1910 case 'R': // -6..5 1911 if (CVal64 < -6 || CVal64 > 5) 1912 return; 1913 Result = DAG.getTargetConstant(CVal64, DL, Ty); 1914 break; 1915 } 1916 1917 break; 1918 } 1919 case 'G': 1920 const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op); 1921 if (!FC || !FC->isZero()) 1922 return; 1923 // Soften float to i8 0 1924 Result = DAG.getTargetConstant(0, DL, MVT::i8); 1925 break; 1926 } 1927 1928 if (Result.getNode()) { 1929 Ops.push_back(Result); 1930 return; 1931 } 1932 1933 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 1934 } 1935 1936 } // end of namespace llvm 1937 1938