1 //===- ARMTargetStreamer.cpp - ARMTargetStreamer class --*- C++ -*---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARMTargetStreamer class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/ARMMCTargetDesc.h"
14 #include "llvm/MC/ConstantPools.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/ARMBuildAttributes.h"
21 #include "llvm/Support/TargetParser.h"
22 
23 using namespace llvm;
24 
25 //
26 // ARMTargetStreamer Implemenation
27 //
28 
29 ARMTargetStreamer::ARMTargetStreamer(MCStreamer &S)
30     : MCTargetStreamer(S), ConstantPools(new AssemblerConstantPools()) {}
31 
32 ARMTargetStreamer::~ARMTargetStreamer() = default;
33 
34 // The constant pool handling is shared by all ARMTargetStreamer
35 // implementations.
36 const MCExpr *ARMTargetStreamer::addConstantPoolEntry(const MCExpr *Expr, SMLoc Loc) {
37   return ConstantPools->addEntry(Streamer, Expr, 4, Loc);
38 }
39 
40 void ARMTargetStreamer::emitCurrentConstantPool() {
41   ConstantPools->emitForCurrentSection(Streamer);
42   ConstantPools->clearCacheForCurrentSection(Streamer);
43 }
44 
45 // finish() - write out any non-empty assembler constant pools.
46 void ARMTargetStreamer::emitConstantPools() {
47   ConstantPools->emitAll(Streamer);
48 }
49 
50 // reset() - Reset any state
51 void ARMTargetStreamer::reset() {}
52 
53 void ARMTargetStreamer::emitInst(uint32_t Inst, char Suffix) {
54   unsigned Size;
55   char Buffer[4];
56   const bool LittleEndian = getStreamer().getContext().getAsmInfo()->isLittleEndian();
57 
58   switch (Suffix) {
59   case '\0':
60     Size = 4;
61 
62     for (unsigned II = 0, IE = Size; II != IE; II++) {
63       const unsigned I = LittleEndian ? (Size - II - 1) : II;
64       Buffer[Size - II - 1] = uint8_t(Inst >> I * CHAR_BIT);
65     }
66 
67     break;
68   case 'n':
69   case 'w':
70     Size = (Suffix == 'n' ? 2 : 4);
71 
72     // Thumb wide instructions are emitted as a pair of 16-bit words of the
73     // appropriate endianness.
74     for (unsigned II = 0, IE = Size; II != IE; II = II + 2) {
75       const unsigned I0 = LittleEndian ? II + 0 : II + 1;
76       const unsigned I1 = LittleEndian ? II + 1 : II + 0;
77       Buffer[Size - II - 2] = uint8_t(Inst >> I0 * CHAR_BIT);
78       Buffer[Size - II - 1] = uint8_t(Inst >> I1 * CHAR_BIT);
79     }
80 
81     break;
82   default:
83     llvm_unreachable("Invalid Suffix");
84   }
85   getStreamer().emitBytes(StringRef(Buffer, Size));
86 }
87 
88 // The remaining callbacks should be handled separately by each
89 // streamer.
90 void ARMTargetStreamer::emitFnStart() {}
91 void ARMTargetStreamer::emitFnEnd() {}
92 void ARMTargetStreamer::emitCantUnwind() {}
93 void ARMTargetStreamer::emitPersonality(const MCSymbol *Personality) {}
94 void ARMTargetStreamer::emitPersonalityIndex(unsigned Index) {}
95 void ARMTargetStreamer::emitHandlerData() {}
96 void ARMTargetStreamer::emitSetFP(unsigned FpReg, unsigned SpReg,
97                                   int64_t Offset) {}
98 void ARMTargetStreamer::emitMovSP(unsigned Reg, int64_t Offset) {}
99 void ARMTargetStreamer::emitPad(int64_t Offset) {}
100 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
101                                     bool isVector) {}
102 void ARMTargetStreamer::emitUnwindRaw(int64_t StackOffset,
103                                       const SmallVectorImpl<uint8_t> &Opcodes) {
104 }
105 void ARMTargetStreamer::switchVendor(StringRef Vendor) {}
106 void ARMTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
107 void ARMTargetStreamer::emitTextAttribute(unsigned Attribute,
108                                           StringRef String) {}
109 void ARMTargetStreamer::emitIntTextAttribute(unsigned Attribute,
110                                              unsigned IntValue,
111                                              StringRef StringValue) {}
112 void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) {}
113 void ARMTargetStreamer::emitArchExtension(uint64_t ArchExt) {}
114 void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) {}
115 void ARMTargetStreamer::emitFPU(unsigned FPU) {}
116 void ARMTargetStreamer::finishAttributeSection() {}
117 void
118 ARMTargetStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) {}
119 void ARMTargetStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) {}
120 
121 static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) {
122   if (STI.getCPU() == "xscale")
123     return ARMBuildAttrs::v5TEJ;
124 
125   if (STI.hasFeature(ARM::HasV9_0aOps))
126     return ARMBuildAttrs::v9_A;
127   else if (STI.hasFeature(ARM::HasV8Ops)) {
128     if (STI.hasFeature(ARM::FeatureRClass))
129       return ARMBuildAttrs::v8_R;
130     return ARMBuildAttrs::v8_A;
131   } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps))
132     return ARMBuildAttrs::v8_1_M_Main;
133   else if (STI.hasFeature(ARM::HasV8MMainlineOps))
134     return ARMBuildAttrs::v8_M_Main;
135   else if (STI.hasFeature(ARM::HasV7Ops)) {
136     if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP))
137       return ARMBuildAttrs::v7E_M;
138     return ARMBuildAttrs::v7;
139   } else if (STI.hasFeature(ARM::HasV6T2Ops))
140     return ARMBuildAttrs::v6T2;
141   else if (STI.hasFeature(ARM::HasV8MBaselineOps))
142     return ARMBuildAttrs::v8_M_Base;
143   else if (STI.hasFeature(ARM::HasV6MOps))
144     return ARMBuildAttrs::v6S_M;
145   else if (STI.hasFeature(ARM::HasV6Ops))
146     return ARMBuildAttrs::v6;
147   else if (STI.hasFeature(ARM::HasV5TEOps))
148     return ARMBuildAttrs::v5TE;
149   else if (STI.hasFeature(ARM::HasV5TOps))
150     return ARMBuildAttrs::v5T;
151   else if (STI.hasFeature(ARM::HasV4TOps))
152     return ARMBuildAttrs::v4T;
153   else
154     return ARMBuildAttrs::v4;
155 }
156 
157 static bool isV8M(const MCSubtargetInfo &STI) {
158   // Note that v8M Baseline is a subset of v6T2!
159   return (STI.hasFeature(ARM::HasV8MBaselineOps) &&
160           !STI.hasFeature(ARM::HasV6T2Ops)) ||
161          STI.hasFeature(ARM::HasV8MMainlineOps);
162 }
163 
164 /// Emit the build attributes that only depend on the hardware that we expect
165 // /to be available, and not on the ABI, or any source-language choices.
166 void ARMTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
167   switchVendor("aeabi");
168 
169   const StringRef CPUString = STI.getCPU();
170   if (!CPUString.empty() && !CPUString.startswith("generic")) {
171     // FIXME: remove krait check when GNU tools support krait cpu
172     if (STI.hasFeature(ARM::ProcKrait)) {
173       emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
174       // We consider krait as a "cortex-a9" + hwdiv CPU
175       // Enable hwdiv through ".arch_extension idiv"
176       if (STI.hasFeature(ARM::FeatureHWDivThumb) ||
177           STI.hasFeature(ARM::FeatureHWDivARM))
178         emitArchExtension(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM);
179     } else {
180       emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
181     }
182   }
183 
184   emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(STI));
185 
186   if (STI.hasFeature(ARM::FeatureAClass)) {
187     emitAttribute(ARMBuildAttrs::CPU_arch_profile,
188                       ARMBuildAttrs::ApplicationProfile);
189   } else if (STI.hasFeature(ARM::FeatureRClass)) {
190     emitAttribute(ARMBuildAttrs::CPU_arch_profile,
191                       ARMBuildAttrs::RealTimeProfile);
192   } else if (STI.hasFeature(ARM::FeatureMClass)) {
193     emitAttribute(ARMBuildAttrs::CPU_arch_profile,
194                       ARMBuildAttrs::MicroControllerProfile);
195   }
196 
197   emitAttribute(ARMBuildAttrs::ARM_ISA_use, STI.hasFeature(ARM::FeatureNoARM)
198                                                 ? ARMBuildAttrs::Not_Allowed
199                                                 : ARMBuildAttrs::Allowed);
200 
201   if (isV8M(STI)) {
202     emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
203                       ARMBuildAttrs::AllowThumbDerived);
204   } else if (STI.hasFeature(ARM::FeatureThumb2)) {
205     emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
206                       ARMBuildAttrs::AllowThumb32);
207   } else if (STI.hasFeature(ARM::HasV4TOps)) {
208     emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
209   }
210 
211   if (STI.hasFeature(ARM::FeatureNEON)) {
212     /* NEON is not exactly a VFP architecture, but GAS emit one of
213      * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
214     if (STI.hasFeature(ARM::FeatureFPARMv8)) {
215       if (STI.hasFeature(ARM::FeatureCrypto))
216         emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
217       else
218         emitFPU(ARM::FK_NEON_FP_ARMV8);
219     } else if (STI.hasFeature(ARM::FeatureVFP4))
220       emitFPU(ARM::FK_NEON_VFPV4);
221     else
222       emitFPU(STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_NEON_FP16
223                                                : ARM::FK_NEON);
224     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
225     if (STI.hasFeature(ARM::HasV8Ops))
226       emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
227                     STI.hasFeature(ARM::HasV8_1aOps)
228                         ? ARMBuildAttrs::AllowNeonARMv8_1a
229                         : ARMBuildAttrs::AllowNeonARMv8);
230   } else {
231     if (STI.hasFeature(ARM::FeatureFPARMv8_D16_SP))
232       // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
233       // FPU, but there are two different names for it depending on the CPU.
234       emitFPU(STI.hasFeature(ARM::FeatureD32)
235                   ? ARM::FK_FP_ARMV8
236                   : (STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_FPV5_D16
237                                                       : ARM::FK_FPV5_SP_D16));
238     else if (STI.hasFeature(ARM::FeatureVFP4_D16_SP))
239       emitFPU(STI.hasFeature(ARM::FeatureD32)
240                   ? ARM::FK_VFPV4
241                   : (STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_VFPV4_D16
242                                                       : ARM::FK_FPV4_SP_D16));
243     else if (STI.hasFeature(ARM::FeatureVFP3_D16_SP))
244       emitFPU(
245           STI.hasFeature(ARM::FeatureD32)
246               // +d32
247               ? (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3_FP16
248                                                   : ARM::FK_VFPV3)
249               // -d32
250               : (STI.hasFeature(ARM::FeatureFP64)
251                      ? (STI.hasFeature(ARM::FeatureFP16)
252                             ? ARM::FK_VFPV3_D16_FP16
253                             : ARM::FK_VFPV3_D16)
254                      : (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3XD_FP16
255                                                          : ARM::FK_VFPV3XD)));
256     else if (STI.hasFeature(ARM::FeatureVFP2_SP))
257       emitFPU(ARM::FK_VFPV2);
258   }
259 
260   // ABI_HardFP_use attribute to indicate single precision FP.
261   if (STI.hasFeature(ARM::FeatureVFP2_SP) && !STI.hasFeature(ARM::FeatureFP64))
262     emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
263                   ARMBuildAttrs::HardFPSinglePrecision);
264 
265   if (STI.hasFeature(ARM::FeatureFP16))
266     emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
267 
268   if (STI.hasFeature(ARM::FeatureMP))
269     emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
270 
271   if (STI.hasFeature(ARM::HasMVEFloatOps))
272     emitAttribute(ARMBuildAttrs::MVE_arch, ARMBuildAttrs::AllowMVEIntegerAndFloat);
273   else if (STI.hasFeature(ARM::HasMVEIntegerOps))
274     emitAttribute(ARMBuildAttrs::MVE_arch, ARMBuildAttrs::AllowMVEInteger);
275 
276   // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
277   // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
278   // It is not possible to produce DisallowDIV: if hwdiv is present in the base
279   // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
280   // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
281   // otherwise, the default value (AllowDIVIfExists) applies.
282   if (STI.hasFeature(ARM::FeatureHWDivARM) && !STI.hasFeature(ARM::HasV8Ops))
283     emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
284 
285   if (STI.hasFeature(ARM::FeatureDSP) && isV8M(STI))
286     emitAttribute(ARMBuildAttrs::DSP_extension, ARMBuildAttrs::Allowed);
287 
288   if (STI.hasFeature(ARM::FeatureStrictAlign))
289     emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
290                   ARMBuildAttrs::Not_Allowed);
291   else
292     emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
293                   ARMBuildAttrs::Allowed);
294 
295   if (STI.hasFeature(ARM::FeatureTrustZone) &&
296       STI.hasFeature(ARM::FeatureVirtualization))
297     emitAttribute(ARMBuildAttrs::Virtualization_use,
298                   ARMBuildAttrs::AllowTZVirtualization);
299   else if (STI.hasFeature(ARM::FeatureTrustZone))
300     emitAttribute(ARMBuildAttrs::Virtualization_use, ARMBuildAttrs::AllowTZ);
301   else if (STI.hasFeature(ARM::FeatureVirtualization))
302     emitAttribute(ARMBuildAttrs::Virtualization_use,
303                   ARMBuildAttrs::AllowVirtualization);
304 
305   if (STI.hasFeature(ARM::FeaturePACBTI)) {
306     emitAttribute(ARMBuildAttrs::PAC_extension, ARMBuildAttrs::AllowPAC);
307     emitAttribute(ARMBuildAttrs::BTI_extension, ARMBuildAttrs::AllowBTI);
308   }
309 }
310