1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains a pass that expands pseudo instructions into target 10 // instructions to allow proper scheduling, if-conversion, and other late 11 // optimizations. This pass should be run after register allocation but before 12 // the post-regalloc scheduling pass. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "ARM.h" 17 #include "ARMBaseInstrInfo.h" 18 #include "ARMBaseRegisterInfo.h" 19 #include "ARMConstantPoolValue.h" 20 #include "ARMMachineFunctionInfo.h" 21 #include "ARMSubtarget.h" 22 #include "MCTargetDesc/ARMAddressingModes.h" 23 #include "llvm/CodeGen/LivePhysRegs.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunctionPass.h" 26 #include "llvm/Support/Debug.h" 27 28 using namespace llvm; 29 30 #define DEBUG_TYPE "arm-pseudo" 31 32 static cl::opt<bool> 33 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, 34 cl::desc("Verify machine code after expanding ARM pseudos")); 35 36 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass" 37 38 namespace { 39 class ARMExpandPseudo : public MachineFunctionPass { 40 public: 41 static char ID; 42 ARMExpandPseudo() : MachineFunctionPass(ID) {} 43 44 const ARMBaseInstrInfo *TII; 45 const TargetRegisterInfo *TRI; 46 const ARMSubtarget *STI; 47 ARMFunctionInfo *AFI; 48 49 bool runOnMachineFunction(MachineFunction &Fn) override; 50 51 MachineFunctionProperties getRequiredProperties() const override { 52 return MachineFunctionProperties().set( 53 MachineFunctionProperties::Property::NoVRegs); 54 } 55 56 StringRef getPassName() const override { 57 return ARM_EXPAND_PSEUDO_NAME; 58 } 59 60 private: 61 void TransferImpOps(MachineInstr &OldMI, 62 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 63 bool ExpandMI(MachineBasicBlock &MBB, 64 MachineBasicBlock::iterator MBBI, 65 MachineBasicBlock::iterator &NextMBBI); 66 bool ExpandMBB(MachineBasicBlock &MBB); 67 void ExpandVLD(MachineBasicBlock::iterator &MBBI); 68 void ExpandVST(MachineBasicBlock::iterator &MBBI); 69 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 70 void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 71 unsigned Opc, bool IsExt); 72 void ExpandMOV32BitImm(MachineBasicBlock &MBB, 73 MachineBasicBlock::iterator &MBBI); 74 void CMSEClearGPRegs(MachineBasicBlock &MBB, 75 MachineBasicBlock::iterator MBBI, const DebugLoc &DL, 76 const SmallVectorImpl<unsigned> &ClearRegs, 77 unsigned ClobberReg); 78 MachineBasicBlock &CMSEClearFPRegs(MachineBasicBlock &MBB, 79 MachineBasicBlock::iterator MBBI); 80 MachineBasicBlock &CMSEClearFPRegsV8(MachineBasicBlock &MBB, 81 MachineBasicBlock::iterator MBBI, 82 const BitVector &ClearRegs); 83 MachineBasicBlock &CMSEClearFPRegsV81(MachineBasicBlock &MBB, 84 MachineBasicBlock::iterator MBBI, 85 const BitVector &ClearRegs); 86 void CMSESaveClearFPRegs(MachineBasicBlock &MBB, 87 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 88 SmallVectorImpl<unsigned> &AvailableRegs); 89 void CMSESaveClearFPRegsV8(MachineBasicBlock &MBB, 90 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 91 SmallVectorImpl<unsigned> &ScratchRegs); 92 void CMSESaveClearFPRegsV81(MachineBasicBlock &MBB, 93 MachineBasicBlock::iterator MBBI, DebugLoc &DL); 94 void CMSERestoreFPRegs(MachineBasicBlock &MBB, 95 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 96 SmallVectorImpl<unsigned> &AvailableRegs); 97 void CMSERestoreFPRegsV8(MachineBasicBlock &MBB, 98 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 99 SmallVectorImpl<unsigned> &AvailableRegs); 100 void CMSERestoreFPRegsV81(MachineBasicBlock &MBB, 101 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 102 SmallVectorImpl<unsigned> &AvailableRegs); 103 bool ExpandCMP_SWAP(MachineBasicBlock &MBB, 104 MachineBasicBlock::iterator MBBI, unsigned LdrexOp, 105 unsigned StrexOp, unsigned UxtOp, 106 MachineBasicBlock::iterator &NextMBBI); 107 108 bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB, 109 MachineBasicBlock::iterator MBBI, 110 MachineBasicBlock::iterator &NextMBBI); 111 }; 112 char ARMExpandPseudo::ID = 0; 113 } 114 115 INITIALIZE_PASS(ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false, 116 false) 117 118 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to 119 /// the instructions created from the expansion. 120 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 121 MachineInstrBuilder &UseMI, 122 MachineInstrBuilder &DefMI) { 123 const MCInstrDesc &Desc = OldMI.getDesc(); 124 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); 125 i != e; ++i) { 126 const MachineOperand &MO = OldMI.getOperand(i); 127 assert(MO.isReg() && MO.getReg()); 128 if (MO.isUse()) 129 UseMI.add(MO); 130 else 131 DefMI.add(MO); 132 } 133 } 134 135 namespace { 136 // Constants for register spacing in NEON load/store instructions. 137 // For quad-register load-lane and store-lane pseudo instructors, the 138 // spacing is initially assumed to be EvenDblSpc, and that is changed to 139 // OddDblSpc depending on the lane number operand. 140 enum NEONRegSpacing { 141 SingleSpc, 142 SingleLowSpc , // Single spacing, low registers, three and four vectors. 143 SingleHighQSpc, // Single spacing, high registers, four vectors. 144 SingleHighTSpc, // Single spacing, high registers, three vectors. 145 EvenDblSpc, 146 OddDblSpc 147 }; 148 149 // Entries for NEON load/store information table. The table is sorted by 150 // PseudoOpc for fast binary-search lookups. 151 struct NEONLdStTableEntry { 152 uint16_t PseudoOpc; 153 uint16_t RealOpc; 154 bool IsLoad; 155 bool isUpdating; 156 bool hasWritebackOperand; 157 uint8_t RegSpacing; // One of type NEONRegSpacing 158 uint8_t NumRegs; // D registers loaded or stored 159 uint8_t RegElts; // elements per D register; used for lane ops 160 // FIXME: Temporary flag to denote whether the real instruction takes 161 // a single register (like the encoding) or all of the registers in 162 // the list (like the asm syntax and the isel DAG). When all definitions 163 // are converted to take only the single encoded register, this will 164 // go away. 165 bool copyAllListRegs; 166 167 // Comparison methods for binary search of the table. 168 bool operator<(const NEONLdStTableEntry &TE) const { 169 return PseudoOpc < TE.PseudoOpc; 170 } 171 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 172 return TE.PseudoOpc < PseudoOpc; 173 } 174 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 175 const NEONLdStTableEntry &TE) { 176 return PseudoOpc < TE.PseudoOpc; 177 } 178 }; 179 } 180 181 static const NEONLdStTableEntry NEONLdStTable[] = { 182 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true}, 183 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true}, 184 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}, 185 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true}, 186 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true}, 187 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true}, 188 189 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false}, 190 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false}, 191 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false}, 192 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false}, 193 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false}, 194 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false}, 195 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 ,false}, 196 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false}, 197 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false}, 198 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,false}, 199 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false}, 200 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false}, 201 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false}, 202 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false}, 203 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,false}, 204 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,false}, 205 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false}, 206 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false}, 207 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,false}, 208 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,false}, 209 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false}, 210 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false}, 211 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,false}, 212 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,false}, 213 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false}, 214 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false}, 215 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false}, 216 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false}, 217 218 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false}, 219 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false}, 220 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false}, 221 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false}, 222 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false}, 223 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false}, 224 225 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, 226 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true}, 227 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true}, 228 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true}, 229 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true}, 230 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true}, 231 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true}, 232 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true}, 233 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true}, 234 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true}, 235 236 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false}, 237 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false}, 238 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false}, 239 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false}, 240 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false}, 241 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false}, 242 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false}, 243 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false}, 244 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false}, 245 246 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true}, 247 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true}, 248 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true}, 249 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true}, 250 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true}, 251 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true}, 252 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 253 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true}, 254 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 255 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true}, 256 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true}, 257 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true}, 258 259 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true}, 260 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 261 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true}, 262 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 263 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true}, 264 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 265 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 266 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 267 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 268 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 269 270 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true}, 271 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 272 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true}, 273 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 274 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true}, 275 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 276 277 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 278 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true}, 279 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true}, 280 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 281 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true}, 282 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true}, 283 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true}, 284 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true}, 285 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true}, 286 287 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true}, 288 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true}, 289 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true}, 290 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true}, 291 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true}, 292 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true}, 293 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 294 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true}, 295 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 296 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true}, 297 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true}, 298 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true}, 299 300 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true}, 301 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 302 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true}, 303 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 304 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true}, 305 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 306 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 307 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 308 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 309 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 310 311 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true}, 312 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 313 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true}, 314 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 315 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true}, 316 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 317 318 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 319 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true}, 320 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true}, 321 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 322 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true}, 323 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true}, 324 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true}, 325 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true}, 326 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true}, 327 328 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true}, 329 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true}, 330 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true}, 331 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true}, 332 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true}, 333 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true}, 334 335 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false}, 336 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false}, 337 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false}, 338 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false}, 339 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false}, 340 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false}, 341 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false}, 342 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false}, 343 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false}, 344 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false}, 345 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false}, 346 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false}, 347 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false}, 348 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false}, 349 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,false}, 350 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,false}, 351 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false}, 352 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false}, 353 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,false}, 354 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,false}, 355 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false}, 356 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false}, 357 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,false}, 358 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,false}, 359 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false}, 360 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false}, 361 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,false}, 362 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,false}, 363 364 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true}, 365 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true}, 366 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true}, 367 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true}, 368 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true}, 369 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true}, 370 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true}, 371 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true}, 372 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true}, 373 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true}, 374 375 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false}, 376 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false}, 377 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false}, 378 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false}, 379 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false}, 380 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false}, 381 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false}, 382 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false}, 383 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false}, 384 385 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true}, 386 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 387 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true}, 388 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 389 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true}, 390 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 391 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true}, 392 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true}, 393 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true}, 394 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true}, 395 396 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true}, 397 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 398 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true}, 399 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 400 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true}, 401 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 402 403 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true}, 404 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true}, 405 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true}, 406 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true}, 407 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true}, 408 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true}, 409 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true}, 410 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true}, 411 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true}, 412 413 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true}, 414 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 415 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true}, 416 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 417 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true}, 418 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 419 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true}, 420 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true}, 421 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true}, 422 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true}, 423 424 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true}, 425 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 426 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true}, 427 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 428 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true}, 429 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 430 431 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true}, 432 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true}, 433 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true}, 434 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true}, 435 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true}, 436 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true}, 437 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true}, 438 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true}, 439 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true} 440 }; 441 442 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 443 /// load or store pseudo instruction. 444 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 445 #ifndef NDEBUG 446 // Make sure the table is sorted. 447 static std::atomic<bool> TableChecked(false); 448 if (!TableChecked.load(std::memory_order_relaxed)) { 449 assert(llvm::is_sorted(NEONLdStTable) && "NEONLdStTable is not sorted!"); 450 TableChecked.store(true, std::memory_order_relaxed); 451 } 452 #endif 453 454 auto I = llvm::lower_bound(NEONLdStTable, Opcode); 455 if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode) 456 return I; 457 return nullptr; 458 } 459 460 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 461 /// corresponding to the specified register spacing. Not all of the results 462 /// are necessarily valid, e.g., a Q register only has 2 D subregisters. 463 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 464 const TargetRegisterInfo *TRI, unsigned &D0, 465 unsigned &D1, unsigned &D2, unsigned &D3) { 466 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) { 467 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 468 D1 = TRI->getSubReg(Reg, ARM::dsub_1); 469 D2 = TRI->getSubReg(Reg, ARM::dsub_2); 470 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 471 } else if (RegSpc == SingleHighQSpc) { 472 D0 = TRI->getSubReg(Reg, ARM::dsub_4); 473 D1 = TRI->getSubReg(Reg, ARM::dsub_5); 474 D2 = TRI->getSubReg(Reg, ARM::dsub_6); 475 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 476 } else if (RegSpc == SingleHighTSpc) { 477 D0 = TRI->getSubReg(Reg, ARM::dsub_3); 478 D1 = TRI->getSubReg(Reg, ARM::dsub_4); 479 D2 = TRI->getSubReg(Reg, ARM::dsub_5); 480 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 481 } else if (RegSpc == EvenDblSpc) { 482 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 483 D1 = TRI->getSubReg(Reg, ARM::dsub_2); 484 D2 = TRI->getSubReg(Reg, ARM::dsub_4); 485 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 486 } else { 487 assert(RegSpc == OddDblSpc && "unknown register spacing"); 488 D0 = TRI->getSubReg(Reg, ARM::dsub_1); 489 D1 = TRI->getSubReg(Reg, ARM::dsub_3); 490 D2 = TRI->getSubReg(Reg, ARM::dsub_5); 491 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 492 } 493 } 494 495 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 496 /// operands to real VLD instructions with D register operands. 497 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 498 MachineInstr &MI = *MBBI; 499 MachineBasicBlock &MBB = *MI.getParent(); 500 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 501 502 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 503 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 504 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 505 unsigned NumRegs = TableEntry->NumRegs; 506 507 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 508 TII->get(TableEntry->RealOpc)); 509 unsigned OpIdx = 0; 510 511 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 512 Register DstReg = MI.getOperand(OpIdx++).getReg(); 513 if(TableEntry->RealOpc == ARM::VLD2DUPd8x2 || 514 TableEntry->RealOpc == ARM::VLD2DUPd16x2 || 515 TableEntry->RealOpc == ARM::VLD2DUPd32x2) { 516 unsigned SubRegIndex; 517 if (RegSpc == EvenDblSpc) { 518 SubRegIndex = ARM::dsub_0; 519 } else { 520 assert(RegSpc == OddDblSpc && "Unexpected spacing!"); 521 SubRegIndex = ARM::dsub_1; 522 } 523 Register SubReg = TRI->getSubReg(DstReg, SubRegIndex); 524 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0, 525 &ARM::DPairSpcRegClass); 526 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); 527 } else { 528 unsigned D0, D1, D2, D3; 529 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 530 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 531 if (NumRegs > 1 && TableEntry->copyAllListRegs) 532 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 533 if (NumRegs > 2 && TableEntry->copyAllListRegs) 534 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 535 if (NumRegs > 3 && TableEntry->copyAllListRegs) 536 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 537 } 538 539 if (TableEntry->isUpdating) 540 MIB.add(MI.getOperand(OpIdx++)); 541 542 // Copy the addrmode6 operands. 543 MIB.add(MI.getOperand(OpIdx++)); 544 MIB.add(MI.getOperand(OpIdx++)); 545 546 // Copy the am6offset operand. 547 if (TableEntry->hasWritebackOperand) { 548 // TODO: The writing-back pseudo instructions we translate here are all 549 // defined to take am6offset nodes that are capable to represent both fixed 550 // and register forms. Some real instructions, however, do not rely on 551 // am6offset and have separate definitions for such forms. When this is the 552 // case, fixed forms do not take any offset nodes, so here we skip them for 553 // such instructions. Once all real and pseudo writing-back instructions are 554 // rewritten without use of am6offset nodes, this code will go away. 555 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++); 556 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed || 557 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed || 558 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed || 559 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed || 560 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed || 561 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed || 562 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed || 563 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed) { 564 assert(AM6Offset.getReg() == 0 && 565 "A fixed writing-back pseudo instruction provides an offset " 566 "register!"); 567 } else { 568 MIB.add(AM6Offset); 569 } 570 } 571 572 // For an instruction writing double-spaced subregs, the pseudo instruction 573 // has an extra operand that is a use of the super-register. Record the 574 // operand index and skip over it. 575 unsigned SrcOpIdx = 0; 576 if(TableEntry->RealOpc != ARM::VLD2DUPd8x2 && 577 TableEntry->RealOpc != ARM::VLD2DUPd16x2 && 578 TableEntry->RealOpc != ARM::VLD2DUPd32x2) { 579 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc || 580 RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || 581 RegSpc == SingleHighTSpc) 582 SrcOpIdx = OpIdx++; 583 } 584 585 // Copy the predicate operands. 586 MIB.add(MI.getOperand(OpIdx++)); 587 MIB.add(MI.getOperand(OpIdx++)); 588 589 // Copy the super-register source operand used for double-spaced subregs over 590 // to the new instruction as an implicit operand. 591 if (SrcOpIdx != 0) { 592 MachineOperand MO = MI.getOperand(SrcOpIdx); 593 MO.setImplicit(true); 594 MIB.add(MO); 595 } 596 // Add an implicit def for the super-register. 597 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 598 TransferImpOps(MI, MIB, MIB); 599 600 // Transfer memoperands. 601 MIB.cloneMemRefs(MI); 602 MI.eraseFromParent(); 603 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 604 } 605 606 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 607 /// operands to real VST instructions with D register operands. 608 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 609 MachineInstr &MI = *MBBI; 610 MachineBasicBlock &MBB = *MI.getParent(); 611 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 612 613 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 614 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 615 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 616 unsigned NumRegs = TableEntry->NumRegs; 617 618 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 619 TII->get(TableEntry->RealOpc)); 620 unsigned OpIdx = 0; 621 if (TableEntry->isUpdating) 622 MIB.add(MI.getOperand(OpIdx++)); 623 624 // Copy the addrmode6 operands. 625 MIB.add(MI.getOperand(OpIdx++)); 626 MIB.add(MI.getOperand(OpIdx++)); 627 628 if (TableEntry->hasWritebackOperand) { 629 // TODO: The writing-back pseudo instructions we translate here are all 630 // defined to take am6offset nodes that are capable to represent both fixed 631 // and register forms. Some real instructions, however, do not rely on 632 // am6offset and have separate definitions for such forms. When this is the 633 // case, fixed forms do not take any offset nodes, so here we skip them for 634 // such instructions. Once all real and pseudo writing-back instructions are 635 // rewritten without use of am6offset nodes, this code will go away. 636 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++); 637 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed || 638 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed || 639 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed || 640 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed || 641 TableEntry->RealOpc == ARM::VST1d8Twb_fixed || 642 TableEntry->RealOpc == ARM::VST1d16Twb_fixed || 643 TableEntry->RealOpc == ARM::VST1d32Twb_fixed || 644 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) { 645 assert(AM6Offset.getReg() == 0 && 646 "A fixed writing-back pseudo instruction provides an offset " 647 "register!"); 648 } else { 649 MIB.add(AM6Offset); 650 } 651 } 652 653 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 654 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef(); 655 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 656 unsigned D0, D1, D2, D3; 657 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 658 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); 659 if (NumRegs > 1 && TableEntry->copyAllListRegs) 660 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); 661 if (NumRegs > 2 && TableEntry->copyAllListRegs) 662 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); 663 if (NumRegs > 3 && TableEntry->copyAllListRegs) 664 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); 665 666 // Copy the predicate operands. 667 MIB.add(MI.getOperand(OpIdx++)); 668 MIB.add(MI.getOperand(OpIdx++)); 669 670 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg. 671 MIB->addRegisterKilled(SrcReg, TRI, true); 672 else if (!SrcIsUndef) 673 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. 674 TransferImpOps(MI, MIB, MIB); 675 676 // Transfer memoperands. 677 MIB.cloneMemRefs(MI); 678 MI.eraseFromParent(); 679 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 680 } 681 682 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 683 /// register operands to real instructions with D register operands. 684 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 685 MachineInstr &MI = *MBBI; 686 MachineBasicBlock &MBB = *MI.getParent(); 687 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 688 689 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 690 assert(TableEntry && "NEONLdStTable lookup failed"); 691 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 692 unsigned NumRegs = TableEntry->NumRegs; 693 unsigned RegElts = TableEntry->RegElts; 694 695 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 696 TII->get(TableEntry->RealOpc)); 697 unsigned OpIdx = 0; 698 // The lane operand is always the 3rd from last operand, before the 2 699 // predicate operands. 700 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 701 702 // Adjust the lane and spacing as needed for Q registers. 703 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 704 if (RegSpc == EvenDblSpc && Lane >= RegElts) { 705 RegSpc = OddDblSpc; 706 Lane -= RegElts; 707 } 708 assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 709 710 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; 711 unsigned DstReg = 0; 712 bool DstIsDead = false; 713 if (TableEntry->IsLoad) { 714 DstIsDead = MI.getOperand(OpIdx).isDead(); 715 DstReg = MI.getOperand(OpIdx++).getReg(); 716 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 717 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 718 if (NumRegs > 1) 719 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 720 if (NumRegs > 2) 721 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 722 if (NumRegs > 3) 723 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 724 } 725 726 if (TableEntry->isUpdating) 727 MIB.add(MI.getOperand(OpIdx++)); 728 729 // Copy the addrmode6 operands. 730 MIB.add(MI.getOperand(OpIdx++)); 731 MIB.add(MI.getOperand(OpIdx++)); 732 // Copy the am6offset operand. 733 if (TableEntry->hasWritebackOperand) 734 MIB.add(MI.getOperand(OpIdx++)); 735 736 // Grab the super-register source. 737 MachineOperand MO = MI.getOperand(OpIdx++); 738 if (!TableEntry->IsLoad) 739 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 740 741 // Add the subregs as sources of the new instruction. 742 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 743 getKillRegState(MO.isKill())); 744 MIB.addReg(D0, SrcFlags); 745 if (NumRegs > 1) 746 MIB.addReg(D1, SrcFlags); 747 if (NumRegs > 2) 748 MIB.addReg(D2, SrcFlags); 749 if (NumRegs > 3) 750 MIB.addReg(D3, SrcFlags); 751 752 // Add the lane number operand. 753 MIB.addImm(Lane); 754 OpIdx += 1; 755 756 // Copy the predicate operands. 757 MIB.add(MI.getOperand(OpIdx++)); 758 MIB.add(MI.getOperand(OpIdx++)); 759 760 // Copy the super-register source to be an implicit source. 761 MO.setImplicit(true); 762 MIB.add(MO); 763 if (TableEntry->IsLoad) 764 // Add an implicit def for the super-register. 765 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 766 TransferImpOps(MI, MIB, MIB); 767 // Transfer memoperands. 768 MIB.cloneMemRefs(MI); 769 MI.eraseFromParent(); 770 } 771 772 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 773 /// register operands to real instructions with D register operands. 774 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 775 unsigned Opc, bool IsExt) { 776 MachineInstr &MI = *MBBI; 777 MachineBasicBlock &MBB = *MI.getParent(); 778 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 779 780 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 781 unsigned OpIdx = 0; 782 783 // Transfer the destination register operand. 784 MIB.add(MI.getOperand(OpIdx++)); 785 if (IsExt) { 786 MachineOperand VdSrc(MI.getOperand(OpIdx++)); 787 MIB.add(VdSrc); 788 } 789 790 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 791 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 792 unsigned D0, D1, D2, D3; 793 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 794 MIB.addReg(D0); 795 796 // Copy the other source register operand. 797 MachineOperand VmSrc(MI.getOperand(OpIdx++)); 798 MIB.add(VmSrc); 799 800 // Copy the predicate operands. 801 MIB.add(MI.getOperand(OpIdx++)); 802 MIB.add(MI.getOperand(OpIdx++)); 803 804 // Add an implicit kill and use for the super-reg. 805 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); 806 TransferImpOps(MI, MIB, MIB); 807 MI.eraseFromParent(); 808 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 809 } 810 811 static bool IsAnAddressOperand(const MachineOperand &MO) { 812 // This check is overly conservative. Unless we are certain that the machine 813 // operand is not a symbol reference, we return that it is a symbol reference. 814 // This is important as the load pair may not be split up Windows. 815 switch (MO.getType()) { 816 case MachineOperand::MO_Register: 817 case MachineOperand::MO_Immediate: 818 case MachineOperand::MO_CImmediate: 819 case MachineOperand::MO_FPImmediate: 820 case MachineOperand::MO_ShuffleMask: 821 return false; 822 case MachineOperand::MO_MachineBasicBlock: 823 return true; 824 case MachineOperand::MO_FrameIndex: 825 return false; 826 case MachineOperand::MO_ConstantPoolIndex: 827 case MachineOperand::MO_TargetIndex: 828 case MachineOperand::MO_JumpTableIndex: 829 case MachineOperand::MO_ExternalSymbol: 830 case MachineOperand::MO_GlobalAddress: 831 case MachineOperand::MO_BlockAddress: 832 return true; 833 case MachineOperand::MO_RegisterMask: 834 case MachineOperand::MO_RegisterLiveOut: 835 return false; 836 case MachineOperand::MO_Metadata: 837 case MachineOperand::MO_MCSymbol: 838 return true; 839 case MachineOperand::MO_CFIIndex: 840 return false; 841 case MachineOperand::MO_IntrinsicID: 842 case MachineOperand::MO_Predicate: 843 llvm_unreachable("should not exist post-isel"); 844 } 845 llvm_unreachable("unhandled machine operand type"); 846 } 847 848 static MachineOperand makeImplicit(const MachineOperand &MO) { 849 MachineOperand NewMO = MO; 850 NewMO.setImplicit(); 851 return NewMO; 852 } 853 854 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, 855 MachineBasicBlock::iterator &MBBI) { 856 MachineInstr &MI = *MBBI; 857 unsigned Opcode = MI.getOpcode(); 858 Register PredReg; 859 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 860 Register DstReg = MI.getOperand(0).getReg(); 861 bool DstIsDead = MI.getOperand(0).isDead(); 862 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; 863 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); 864 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO); 865 MachineInstrBuilder LO16, HI16; 866 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 867 868 if (!STI->hasV6T2Ops() && 869 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { 870 // FIXME Windows CE supports older ARM CPUs 871 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+"); 872 873 // Expand into a movi + orr. 874 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 875 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) 876 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 877 .addReg(DstReg); 878 879 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); 880 unsigned ImmVal = (unsigned)MO.getImm(); 881 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 882 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 883 unsigned MIFlags = MI.getFlags(); 884 LO16 = LO16.addImm(SOImmValV1); 885 HI16 = HI16.addImm(SOImmValV2); 886 LO16.cloneMemRefs(MI); 887 HI16.cloneMemRefs(MI); 888 LO16.setMIFlags(MIFlags); 889 HI16.setMIFlags(MIFlags); 890 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp()); 891 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp()); 892 if (isCC) 893 LO16.add(makeImplicit(MI.getOperand(1))); 894 TransferImpOps(MI, LO16, HI16); 895 MI.eraseFromParent(); 896 return; 897 } 898 899 unsigned LO16Opc = 0; 900 unsigned HI16Opc = 0; 901 unsigned MIFlags = MI.getFlags(); 902 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { 903 LO16Opc = ARM::t2MOVi16; 904 HI16Opc = ARM::t2MOVTi16; 905 } else { 906 LO16Opc = ARM::MOVi16; 907 HI16Opc = ARM::MOVTi16; 908 } 909 910 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); 911 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) 912 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 913 .addReg(DstReg); 914 915 LO16.setMIFlags(MIFlags); 916 HI16.setMIFlags(MIFlags); 917 918 switch (MO.getType()) { 919 case MachineOperand::MO_Immediate: { 920 unsigned Imm = MO.getImm(); 921 unsigned Lo16 = Imm & 0xffff; 922 unsigned Hi16 = (Imm >> 16) & 0xffff; 923 LO16 = LO16.addImm(Lo16); 924 HI16 = HI16.addImm(Hi16); 925 break; 926 } 927 case MachineOperand::MO_ExternalSymbol: { 928 const char *ES = MO.getSymbolName(); 929 unsigned TF = MO.getTargetFlags(); 930 LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16); 931 HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16); 932 break; 933 } 934 default: { 935 const GlobalValue *GV = MO.getGlobal(); 936 unsigned TF = MO.getTargetFlags(); 937 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 938 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 939 break; 940 } 941 } 942 943 LO16.cloneMemRefs(MI); 944 HI16.cloneMemRefs(MI); 945 LO16.addImm(Pred).addReg(PredReg); 946 HI16.addImm(Pred).addReg(PredReg); 947 948 if (RequiresBundling) 949 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator()); 950 951 if (isCC) 952 LO16.add(makeImplicit(MI.getOperand(1))); 953 TransferImpOps(MI, LO16, HI16); 954 MI.eraseFromParent(); 955 LLVM_DEBUG(dbgs() << "To: "; LO16.getInstr()->dump();); 956 LLVM_DEBUG(dbgs() << "And: "; HI16.getInstr()->dump();); 957 } 958 959 // The size of the area, accessed by that VLSTM/VLLDM 960 // S0-S31 + FPSCR + 8 more bytes (VPR + pad, or just pad) 961 static const int CMSE_FP_SAVE_SIZE = 136; 962 963 static void determineGPRegsToClear(const MachineInstr &MI, 964 const std::initializer_list<unsigned> &Regs, 965 SmallVectorImpl<unsigned> &ClearRegs) { 966 SmallVector<unsigned, 4> OpRegs; 967 for (const MachineOperand &Op : MI.operands()) { 968 if (!Op.isReg() || !Op.isUse()) 969 continue; 970 OpRegs.push_back(Op.getReg()); 971 } 972 llvm::sort(OpRegs); 973 974 std::set_difference(Regs.begin(), Regs.end(), OpRegs.begin(), OpRegs.end(), 975 std::back_inserter(ClearRegs)); 976 } 977 978 void ARMExpandPseudo::CMSEClearGPRegs( 979 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 980 const DebugLoc &DL, const SmallVectorImpl<unsigned> &ClearRegs, 981 unsigned ClobberReg) { 982 983 if (STI->hasV8_1MMainlineOps()) { 984 // Clear the registers using the CLRM instruction. 985 MachineInstrBuilder CLRM = 986 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2CLRM)).add(predOps(ARMCC::AL)); 987 for (unsigned R : ClearRegs) 988 CLRM.addReg(R, RegState::Define); 989 CLRM.addReg(ARM::APSR, RegState::Define); 990 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); 991 } else { 992 // Clear the registers and flags by copying ClobberReg into them. 993 // (Baseline can't do a high register clear in one instruction). 994 for (unsigned Reg : ClearRegs) { 995 if (Reg == ClobberReg) 996 continue; 997 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVr), Reg) 998 .addReg(ClobberReg) 999 .add(predOps(ARMCC::AL)); 1000 } 1001 1002 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2MSR_M)) 1003 .addImm(STI->hasDSP() ? 0xc00 : 0x800) 1004 .addReg(ClobberReg) 1005 .add(predOps(ARMCC::AL)); 1006 } 1007 } 1008 1009 // Find which FP registers need to be cleared. The parameter `ClearRegs` is 1010 // initialised with all elements set to true, and this function resets all the 1011 // bits, which correspond to register uses. Returns true if any floating point 1012 // register is defined, false otherwise. 1013 static bool determineFPRegsToClear(const MachineInstr &MI, 1014 BitVector &ClearRegs) { 1015 bool DefFP = false; 1016 for (const MachineOperand &Op : MI.operands()) { 1017 if (!Op.isReg()) 1018 continue; 1019 1020 unsigned Reg = Op.getReg(); 1021 if (Op.isDef()) { 1022 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || 1023 (Reg >= ARM::D0 && Reg <= ARM::D15) || 1024 (Reg >= ARM::S0 && Reg <= ARM::S31)) 1025 DefFP = true; 1026 continue; 1027 } 1028 1029 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) { 1030 int R = Reg - ARM::Q0; 1031 ClearRegs.reset(R * 4, (R + 1) * 4); 1032 } else if (Reg >= ARM::D0 && Reg <= ARM::D15) { 1033 int R = Reg - ARM::D0; 1034 ClearRegs.reset(R * 2, (R + 1) * 2); 1035 } else if (Reg >= ARM::S0 && Reg <= ARM::S31) { 1036 ClearRegs[Reg - ARM::S0] = false; 1037 } 1038 } 1039 return DefFP; 1040 } 1041 1042 MachineBasicBlock & 1043 ARMExpandPseudo::CMSEClearFPRegs(MachineBasicBlock &MBB, 1044 MachineBasicBlock::iterator MBBI) { 1045 BitVector ClearRegs(16, true); 1046 (void)determineFPRegsToClear(*MBBI, ClearRegs); 1047 1048 if (STI->hasV8_1MMainlineOps()) 1049 return CMSEClearFPRegsV81(MBB, MBBI, ClearRegs); 1050 else 1051 return CMSEClearFPRegsV8(MBB, MBBI, ClearRegs); 1052 } 1053 1054 // Clear the FP registers for v8.0-M, by copying over the content 1055 // of LR. Uses R12 as a scratch register. 1056 MachineBasicBlock & 1057 ARMExpandPseudo::CMSEClearFPRegsV8(MachineBasicBlock &MBB, 1058 MachineBasicBlock::iterator MBBI, 1059 const BitVector &ClearRegs) { 1060 if (!STI->hasFPRegs()) 1061 return MBB; 1062 1063 auto &RetI = *MBBI; 1064 const DebugLoc &DL = RetI.getDebugLoc(); 1065 1066 // If optimising for minimum size, clear FP registers unconditionally. 1067 // Otherwise, check the CONTROL.SFPA (Secure Floating-Point Active) bit and 1068 // don't clear them if they belong to the non-secure state. 1069 MachineBasicBlock *ClearBB, *DoneBB; 1070 if (STI->hasMinSize()) { 1071 ClearBB = DoneBB = &MBB; 1072 } else { 1073 MachineFunction *MF = MBB.getParent(); 1074 ClearBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1075 DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1076 1077 MF->insert(++MBB.getIterator(), ClearBB); 1078 MF->insert(++ClearBB->getIterator(), DoneBB); 1079 1080 DoneBB->splice(DoneBB->end(), &MBB, MBBI, MBB.end()); 1081 DoneBB->transferSuccessors(&MBB); 1082 MBB.addSuccessor(ClearBB); 1083 MBB.addSuccessor(DoneBB); 1084 ClearBB->addSuccessor(DoneBB); 1085 1086 // At the new basic blocks we need to have live-in the registers, used 1087 // for the return value as well as LR, used to clear registers. 1088 for (const MachineOperand &Op : RetI.operands()) { 1089 if (!Op.isReg()) 1090 continue; 1091 Register Reg = Op.getReg(); 1092 if (Reg == ARM::NoRegister || Reg == ARM::LR) 1093 continue; 1094 assert(Register::isPhysicalRegister(Reg) && "Unallocated register"); 1095 ClearBB->addLiveIn(Reg); 1096 DoneBB->addLiveIn(Reg); 1097 } 1098 ClearBB->addLiveIn(ARM::LR); 1099 DoneBB->addLiveIn(ARM::LR); 1100 1101 // Read the CONTROL register. 1102 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2MRS_M), ARM::R12) 1103 .addImm(20) 1104 .add(predOps(ARMCC::AL)); 1105 // Check bit 3 (SFPA). 1106 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2TSTri)) 1107 .addReg(ARM::R12) 1108 .addImm(8) 1109 .add(predOps(ARMCC::AL)); 1110 // If SFPA is clear, jump over ClearBB to DoneBB. 1111 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::tBcc)) 1112 .addMBB(DoneBB) 1113 .addImm(ARMCC::EQ) 1114 .addReg(ARM::CPSR, RegState::Kill); 1115 } 1116 1117 // Emit the clearing sequence 1118 for (unsigned D = 0; D < 8; D++) { 1119 // Attempt to clear as double 1120 if (ClearRegs[D * 2 + 0] && ClearRegs[D * 2 + 1]) { 1121 unsigned Reg = ARM::D0 + D; 1122 BuildMI(ClearBB, DL, TII->get(ARM::VMOVDRR), Reg) 1123 .addReg(ARM::LR) 1124 .addReg(ARM::LR) 1125 .add(predOps(ARMCC::AL)); 1126 } else { 1127 // Clear first part as single 1128 if (ClearRegs[D * 2 + 0]) { 1129 unsigned Reg = ARM::S0 + D * 2; 1130 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) 1131 .addReg(ARM::LR) 1132 .add(predOps(ARMCC::AL)); 1133 } 1134 // Clear second part as single 1135 if (ClearRegs[D * 2 + 1]) { 1136 unsigned Reg = ARM::S0 + D * 2 + 1; 1137 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) 1138 .addReg(ARM::LR) 1139 .add(predOps(ARMCC::AL)); 1140 } 1141 } 1142 } 1143 1144 // Clear FPSCR bits 0-4, 7, 28-31 1145 // The other bits are program global according to the AAPCS 1146 BuildMI(ClearBB, DL, TII->get(ARM::VMRS), ARM::R12) 1147 .add(predOps(ARMCC::AL)); 1148 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) 1149 .addReg(ARM::R12) 1150 .addImm(0x0000009F) 1151 .add(predOps(ARMCC::AL)) 1152 .add(condCodeOp()); 1153 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) 1154 .addReg(ARM::R12) 1155 .addImm(0xF0000000) 1156 .add(predOps(ARMCC::AL)) 1157 .add(condCodeOp()); 1158 BuildMI(ClearBB, DL, TII->get(ARM::VMSR)) 1159 .addReg(ARM::R12) 1160 .add(predOps(ARMCC::AL)); 1161 1162 return *DoneBB; 1163 } 1164 1165 MachineBasicBlock & 1166 ARMExpandPseudo::CMSEClearFPRegsV81(MachineBasicBlock &MBB, 1167 MachineBasicBlock::iterator MBBI, 1168 const BitVector &ClearRegs) { 1169 auto &RetI = *MBBI; 1170 1171 // Emit a sequence of VSCCLRM <sreglist> instructions, one instruction for 1172 // each contiguous sequence of S-registers. 1173 int Start = -1, End = -1; 1174 for (int S = 0, E = ClearRegs.size(); S != E; ++S) { 1175 if (ClearRegs[S] && S == End + 1) { 1176 End = S; // extend range 1177 continue; 1178 } 1179 // Emit current range. 1180 if (Start < End) { 1181 MachineInstrBuilder VSCCLRM = 1182 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) 1183 .add(predOps(ARMCC::AL)); 1184 while (++Start <= End) 1185 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); 1186 VSCCLRM.addReg(ARM::VPR, RegState::Define); 1187 } 1188 Start = End = S; 1189 } 1190 // Emit last range. 1191 if (Start < End) { 1192 MachineInstrBuilder VSCCLRM = 1193 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) 1194 .add(predOps(ARMCC::AL)); 1195 while (++Start <= End) 1196 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); 1197 VSCCLRM.addReg(ARM::VPR, RegState::Define); 1198 } 1199 1200 return MBB; 1201 } 1202 1203 void ARMExpandPseudo::CMSESaveClearFPRegs( 1204 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1205 SmallVectorImpl<unsigned> &ScratchRegs) { 1206 if (STI->hasV8_1MMainlineOps()) 1207 CMSESaveClearFPRegsV81(MBB, MBBI, DL); 1208 else 1209 CMSESaveClearFPRegsV8(MBB, MBBI, DL, ScratchRegs); 1210 } 1211 1212 // Save and clear FP registers if present 1213 void ARMExpandPseudo::CMSESaveClearFPRegsV8( 1214 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1215 SmallVectorImpl<unsigned> &ScratchRegs) { 1216 if (!STI->hasFPRegs()) 1217 return; 1218 1219 // Store an available register for FPSCR clearing 1220 assert(!ScratchRegs.empty()); 1221 unsigned SpareReg = ScratchRegs.front(); 1222 1223 // save space on stack for VLSTM 1224 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) 1225 .addReg(ARM::SP) 1226 .addImm(CMSE_FP_SAVE_SIZE >> 2) 1227 .add(predOps(ARMCC::AL)); 1228 1229 // Use ScratchRegs to store the fp regs 1230 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs; 1231 std::vector<unsigned> NonclearedFPRegs; 1232 for (const MachineOperand &Op : MBBI->operands()) { 1233 if (Op.isReg() && Op.isUse()) { 1234 unsigned Reg = Op.getReg(); 1235 assert(!ARM::DPRRegClass.contains(Reg) || 1236 ARM::DPR_VFP2RegClass.contains(Reg)); 1237 assert(!ARM::QPRRegClass.contains(Reg)); 1238 if (ARM::DPR_VFP2RegClass.contains(Reg)) { 1239 if (ScratchRegs.size() >= 2) { 1240 unsigned SaveReg2 = ScratchRegs.pop_back_val(); 1241 unsigned SaveReg1 = ScratchRegs.pop_back_val(); 1242 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2); 1243 1244 // Save the fp register to the normal registers 1245 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) 1246 .addReg(SaveReg1, RegState::Define) 1247 .addReg(SaveReg2, RegState::Define) 1248 .addReg(Reg) 1249 .add(predOps(ARMCC::AL)); 1250 } else { 1251 NonclearedFPRegs.push_back(Reg); 1252 } 1253 } else if (ARM::SPRRegClass.contains(Reg)) { 1254 if (ScratchRegs.size() >= 1) { 1255 unsigned SaveReg = ScratchRegs.pop_back_val(); 1256 ClearedFPRegs.emplace_back(Reg, SaveReg, 0); 1257 1258 // Save the fp register to the normal registers 1259 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) 1260 .addReg(Reg) 1261 .add(predOps(ARMCC::AL)); 1262 } else { 1263 NonclearedFPRegs.push_back(Reg); 1264 } 1265 } 1266 } 1267 } 1268 1269 bool passesFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty()); 1270 1271 // Lazy store all fp registers to the stack 1272 MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) 1273 .addReg(ARM::SP) 1274 .add(predOps(ARMCC::AL)); 1275 1276 // Restore all arguments 1277 for (const auto &Regs : ClearedFPRegs) { 1278 unsigned Reg, SaveReg1, SaveReg2; 1279 std::tie(Reg, SaveReg1, SaveReg2) = Regs; 1280 if (ARM::DPR_VFP2RegClass.contains(Reg)) 1281 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) 1282 .addReg(SaveReg1) 1283 .addReg(SaveReg2) 1284 .add(predOps(ARMCC::AL)); 1285 else if (ARM::SPRRegClass.contains(Reg)) 1286 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) 1287 .addReg(SaveReg1) 1288 .add(predOps(ARMCC::AL)); 1289 } 1290 1291 for (unsigned Reg : NonclearedFPRegs) { 1292 if (ARM::DPR_VFP2RegClass.contains(Reg)) { 1293 if (STI->isLittle()) { 1294 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRD), Reg) 1295 .addReg(ARM::SP) 1296 .addImm((Reg - ARM::D0) * 2) 1297 .add(predOps(ARMCC::AL)); 1298 } else { 1299 // For big-endian targets we need to load the two subregisters of Reg 1300 // manually because VLDRD would load them in wrong order 1301 unsigned SReg0 = TRI->getSubReg(Reg, ARM::ssub_0); 1302 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0) 1303 .addReg(ARM::SP) 1304 .addImm((Reg - ARM::D0) * 2) 1305 .add(predOps(ARMCC::AL)); 1306 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0 + 1) 1307 .addReg(ARM::SP) 1308 .addImm((Reg - ARM::D0) * 2 + 1) 1309 .add(predOps(ARMCC::AL)); 1310 } 1311 } else if (ARM::SPRRegClass.contains(Reg)) { 1312 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), Reg) 1313 .addReg(ARM::SP) 1314 .addImm(Reg - ARM::S0) 1315 .add(predOps(ARMCC::AL)); 1316 } 1317 } 1318 // restore FPSCR from stack and clear bits 0-4, 7, 28-31 1319 // The other bits are program global according to the AAPCS 1320 if (passesFPReg) { 1321 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2LDRi8), SpareReg) 1322 .addReg(ARM::SP) 1323 .addImm(0x40) 1324 .add(predOps(ARMCC::AL)); 1325 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) 1326 .addReg(SpareReg) 1327 .addImm(0x0000009F) 1328 .add(predOps(ARMCC::AL)) 1329 .add(condCodeOp()); 1330 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) 1331 .addReg(SpareReg) 1332 .addImm(0xF0000000) 1333 .add(predOps(ARMCC::AL)) 1334 .add(condCodeOp()); 1335 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMSR)) 1336 .addReg(SpareReg) 1337 .add(predOps(ARMCC::AL)); 1338 // The ldr must happen after a floating point instruction. To prevent the 1339 // post-ra scheduler to mess with the order, we create a bundle. 1340 finalizeBundle(MBB, VLSTM->getIterator(), MBBI->getIterator()); 1341 } 1342 } 1343 1344 void ARMExpandPseudo::CMSESaveClearFPRegsV81(MachineBasicBlock &MBB, 1345 MachineBasicBlock::iterator MBBI, 1346 DebugLoc &DL) { 1347 BitVector ClearRegs(32, true); 1348 bool DefFP = determineFPRegsToClear(*MBBI, ClearRegs); 1349 1350 // If the instruction does not write to a FP register and no elements were 1351 // removed from the set, then no FP registers were used to pass 1352 // arguments/returns. 1353 if (!DefFP && ClearRegs.count() == ClearRegs.size()) { 1354 // save space on stack for VLSTM 1355 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) 1356 .addReg(ARM::SP) 1357 .addImm(CMSE_FP_SAVE_SIZE >> 2) 1358 .add(predOps(ARMCC::AL)); 1359 1360 // Lazy store all FP registers to the stack 1361 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) 1362 .addReg(ARM::SP) 1363 .add(predOps(ARMCC::AL)); 1364 } else { 1365 // Push all the callee-saved registers (s16-s31). 1366 MachineInstrBuilder VPUSH = 1367 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP) 1368 .addReg(ARM::SP) 1369 .add(predOps(ARMCC::AL)); 1370 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) 1371 VPUSH.addReg(Reg); 1372 1373 // Clear FP registers with a VSCCLRM. 1374 (void)CMSEClearFPRegsV81(MBB, MBBI, ClearRegs); 1375 1376 // Save floating-point context. 1377 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTR_FPCXTS_pre), ARM::SP) 1378 .addReg(ARM::SP) 1379 .addImm(-8) 1380 .add(predOps(ARMCC::AL)); 1381 } 1382 } 1383 1384 // Restore FP registers if present 1385 void ARMExpandPseudo::CMSERestoreFPRegs( 1386 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1387 SmallVectorImpl<unsigned> &AvailableRegs) { 1388 if (STI->hasV8_1MMainlineOps()) 1389 CMSERestoreFPRegsV81(MBB, MBBI, DL, AvailableRegs); 1390 else 1391 CMSERestoreFPRegsV8(MBB, MBBI, DL, AvailableRegs); 1392 } 1393 1394 void ARMExpandPseudo::CMSERestoreFPRegsV8( 1395 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1396 SmallVectorImpl<unsigned> &AvailableRegs) { 1397 if (!STI->hasFPRegs()) 1398 return; 1399 1400 // Use AvailableRegs to store the fp regs 1401 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs; 1402 std::vector<unsigned> NonclearedFPRegs; 1403 for (const MachineOperand &Op : MBBI->operands()) { 1404 if (Op.isReg() && Op.isDef()) { 1405 unsigned Reg = Op.getReg(); 1406 assert(!ARM::DPRRegClass.contains(Reg) || 1407 ARM::DPR_VFP2RegClass.contains(Reg)); 1408 assert(!ARM::QPRRegClass.contains(Reg)); 1409 if (ARM::DPR_VFP2RegClass.contains(Reg)) { 1410 if (AvailableRegs.size() >= 2) { 1411 unsigned SaveReg2 = AvailableRegs.pop_back_val(); 1412 unsigned SaveReg1 = AvailableRegs.pop_back_val(); 1413 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2); 1414 1415 // Save the fp register to the normal registers 1416 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) 1417 .addReg(SaveReg1, RegState::Define) 1418 .addReg(SaveReg2, RegState::Define) 1419 .addReg(Reg) 1420 .add(predOps(ARMCC::AL)); 1421 } else { 1422 NonclearedFPRegs.push_back(Reg); 1423 } 1424 } else if (ARM::SPRRegClass.contains(Reg)) { 1425 if (AvailableRegs.size() >= 1) { 1426 unsigned SaveReg = AvailableRegs.pop_back_val(); 1427 ClearedFPRegs.emplace_back(Reg, SaveReg, 0); 1428 1429 // Save the fp register to the normal registers 1430 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) 1431 .addReg(Reg) 1432 .add(predOps(ARMCC::AL)); 1433 } else { 1434 NonclearedFPRegs.push_back(Reg); 1435 } 1436 } 1437 } 1438 } 1439 1440 // Push FP regs that cannot be restored via normal registers on the stack 1441 for (unsigned Reg : NonclearedFPRegs) { 1442 if (ARM::DPR_VFP2RegClass.contains(Reg)) 1443 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRD), Reg) 1444 .addReg(ARM::SP) 1445 .addImm((Reg - ARM::D0) * 2) 1446 .add(predOps(ARMCC::AL)); 1447 else if (ARM::SPRRegClass.contains(Reg)) 1448 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRS), Reg) 1449 .addReg(ARM::SP) 1450 .addImm(Reg - ARM::S0) 1451 .add(predOps(ARMCC::AL)); 1452 } 1453 1454 // Lazy load fp regs from stack 1455 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) 1456 .addReg(ARM::SP) 1457 .add(predOps(ARMCC::AL)); 1458 1459 // Restore all FP registers via normal registers 1460 for (const auto &Regs : ClearedFPRegs) { 1461 unsigned Reg, SaveReg1, SaveReg2; 1462 std::tie(Reg, SaveReg1, SaveReg2) = Regs; 1463 if (ARM::DPR_VFP2RegClass.contains(Reg)) 1464 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) 1465 .addReg(SaveReg1) 1466 .addReg(SaveReg2) 1467 .add(predOps(ARMCC::AL)); 1468 else if (ARM::SPRRegClass.contains(Reg)) 1469 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) 1470 .addReg(SaveReg1) 1471 .add(predOps(ARMCC::AL)); 1472 } 1473 1474 // Pop the stack space 1475 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) 1476 .addReg(ARM::SP) 1477 .addImm(CMSE_FP_SAVE_SIZE >> 2) 1478 .add(predOps(ARMCC::AL)); 1479 } 1480 1481 static bool definesOrUsesFPReg(const MachineInstr &MI) { 1482 for (const MachineOperand &Op : MI.operands()) { 1483 if (!Op.isReg()) 1484 continue; 1485 unsigned Reg = Op.getReg(); 1486 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || 1487 (Reg >= ARM::D0 && Reg <= ARM::D15) || 1488 (Reg >= ARM::S0 && Reg <= ARM::S31)) 1489 return true; 1490 } 1491 return false; 1492 } 1493 1494 void ARMExpandPseudo::CMSERestoreFPRegsV81( 1495 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1496 SmallVectorImpl<unsigned> &AvailableRegs) { 1497 if (!definesOrUsesFPReg(*MBBI)) { 1498 // Load FP registers from stack. 1499 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) 1500 .addReg(ARM::SP) 1501 .add(predOps(ARMCC::AL)); 1502 1503 // Pop the stack space 1504 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) 1505 .addReg(ARM::SP) 1506 .addImm(CMSE_FP_SAVE_SIZE >> 2) 1507 .add(predOps(ARMCC::AL)); 1508 } else { 1509 // Restore the floating point context. 1510 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::VLDR_FPCXTS_post), 1511 ARM::SP) 1512 .addReg(ARM::SP) 1513 .addImm(8) 1514 .add(predOps(ARMCC::AL)); 1515 1516 // Pop all the callee-saved registers (s16-s31). 1517 MachineInstrBuilder VPOP = 1518 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDMSIA_UPD), ARM::SP) 1519 .addReg(ARM::SP) 1520 .add(predOps(ARMCC::AL)); 1521 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) 1522 VPOP.addReg(Reg, RegState::Define); 1523 } 1524 } 1525 1526 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as 1527 /// possible. This only gets used at -O0 so we don't care about efficiency of 1528 /// the generated code. 1529 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB, 1530 MachineBasicBlock::iterator MBBI, 1531 unsigned LdrexOp, unsigned StrexOp, 1532 unsigned UxtOp, 1533 MachineBasicBlock::iterator &NextMBBI) { 1534 bool IsThumb = STI->isThumb(); 1535 MachineInstr &MI = *MBBI; 1536 DebugLoc DL = MI.getDebugLoc(); 1537 const MachineOperand &Dest = MI.getOperand(0); 1538 Register TempReg = MI.getOperand(1).getReg(); 1539 // Duplicating undef operands into 2 instructions does not guarantee the same 1540 // value on both; However undef should be replaced by xzr anyway. 1541 assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); 1542 Register AddrReg = MI.getOperand(2).getReg(); 1543 Register DesiredReg = MI.getOperand(3).getReg(); 1544 Register NewReg = MI.getOperand(4).getReg(); 1545 1546 MachineFunction *MF = MBB.getParent(); 1547 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1548 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1549 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1550 1551 MF->insert(++MBB.getIterator(), LoadCmpBB); 1552 MF->insert(++LoadCmpBB->getIterator(), StoreBB); 1553 MF->insert(++StoreBB->getIterator(), DoneBB); 1554 1555 if (UxtOp) { 1556 MachineInstrBuilder MIB = 1557 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg) 1558 .addReg(DesiredReg, RegState::Kill); 1559 if (!IsThumb) 1560 MIB.addImm(0); 1561 MIB.add(predOps(ARMCC::AL)); 1562 } 1563 1564 // .Lloadcmp: 1565 // ldrex rDest, [rAddr] 1566 // cmp rDest, rDesired 1567 // bne .Ldone 1568 1569 MachineInstrBuilder MIB; 1570 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg()); 1571 MIB.addReg(AddrReg); 1572 if (LdrexOp == ARM::t2LDREX) 1573 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset. 1574 MIB.add(predOps(ARMCC::AL)); 1575 1576 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; 1577 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 1578 .addReg(Dest.getReg(), getKillRegState(Dest.isDead())) 1579 .addReg(DesiredReg) 1580 .add(predOps(ARMCC::AL)); 1581 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; 1582 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) 1583 .addMBB(DoneBB) 1584 .addImm(ARMCC::NE) 1585 .addReg(ARM::CPSR, RegState::Kill); 1586 LoadCmpBB->addSuccessor(DoneBB); 1587 LoadCmpBB->addSuccessor(StoreBB); 1588 1589 // .Lstore: 1590 // strex rTempReg, rNew, [rAddr] 1591 // cmp rTempReg, #0 1592 // bne .Lloadcmp 1593 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg) 1594 .addReg(NewReg) 1595 .addReg(AddrReg); 1596 if (StrexOp == ARM::t2STREX) 1597 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset. 1598 MIB.add(predOps(ARMCC::AL)); 1599 1600 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; 1601 BuildMI(StoreBB, DL, TII->get(CMPri)) 1602 .addReg(TempReg, RegState::Kill) 1603 .addImm(0) 1604 .add(predOps(ARMCC::AL)); 1605 BuildMI(StoreBB, DL, TII->get(Bcc)) 1606 .addMBB(LoadCmpBB) 1607 .addImm(ARMCC::NE) 1608 .addReg(ARM::CPSR, RegState::Kill); 1609 StoreBB->addSuccessor(LoadCmpBB); 1610 StoreBB->addSuccessor(DoneBB); 1611 1612 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); 1613 DoneBB->transferSuccessors(&MBB); 1614 1615 MBB.addSuccessor(LoadCmpBB); 1616 1617 NextMBBI = MBB.end(); 1618 MI.eraseFromParent(); 1619 1620 // Recompute livein lists. 1621 LivePhysRegs LiveRegs; 1622 computeAndAddLiveIns(LiveRegs, *DoneBB); 1623 computeAndAddLiveIns(LiveRegs, *StoreBB); 1624 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1625 // Do an extra pass around the loop to get loop carried registers right. 1626 StoreBB->clearLiveIns(); 1627 computeAndAddLiveIns(LiveRegs, *StoreBB); 1628 LoadCmpBB->clearLiveIns(); 1629 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1630 1631 return true; 1632 } 1633 1634 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a 1635 /// single GPRPair register), Thumb's take two separate registers so we need to 1636 /// extract the subregs from the pair. 1637 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, 1638 unsigned Flags, bool IsThumb, 1639 const TargetRegisterInfo *TRI) { 1640 if (IsThumb) { 1641 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); 1642 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); 1643 MIB.addReg(RegLo, Flags); 1644 MIB.addReg(RegHi, Flags); 1645 } else 1646 MIB.addReg(Reg.getReg(), Flags); 1647 } 1648 1649 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop. 1650 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB, 1651 MachineBasicBlock::iterator MBBI, 1652 MachineBasicBlock::iterator &NextMBBI) { 1653 bool IsThumb = STI->isThumb(); 1654 MachineInstr &MI = *MBBI; 1655 DebugLoc DL = MI.getDebugLoc(); 1656 MachineOperand &Dest = MI.getOperand(0); 1657 Register TempReg = MI.getOperand(1).getReg(); 1658 // Duplicating undef operands into 2 instructions does not guarantee the same 1659 // value on both; However undef should be replaced by xzr anyway. 1660 assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); 1661 Register AddrReg = MI.getOperand(2).getReg(); 1662 Register DesiredReg = MI.getOperand(3).getReg(); 1663 MachineOperand New = MI.getOperand(4); 1664 New.setIsKill(false); 1665 1666 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); 1667 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); 1668 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); 1669 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); 1670 1671 MachineFunction *MF = MBB.getParent(); 1672 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1673 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1674 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1675 1676 MF->insert(++MBB.getIterator(), LoadCmpBB); 1677 MF->insert(++LoadCmpBB->getIterator(), StoreBB); 1678 MF->insert(++StoreBB->getIterator(), DoneBB); 1679 1680 // .Lloadcmp: 1681 // ldrexd rDestLo, rDestHi, [rAddr] 1682 // cmp rDestLo, rDesiredLo 1683 // sbcs dead rTempReg, rDestHi, rDesiredHi 1684 // bne .Ldone 1685 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD; 1686 MachineInstrBuilder MIB; 1687 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD)); 1688 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI); 1689 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); 1690 1691 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; 1692 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 1693 .addReg(DestLo, getKillRegState(Dest.isDead())) 1694 .addReg(DesiredLo) 1695 .add(predOps(ARMCC::AL)); 1696 1697 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 1698 .addReg(DestHi, getKillRegState(Dest.isDead())) 1699 .addReg(DesiredHi) 1700 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); 1701 1702 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; 1703 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) 1704 .addMBB(DoneBB) 1705 .addImm(ARMCC::NE) 1706 .addReg(ARM::CPSR, RegState::Kill); 1707 LoadCmpBB->addSuccessor(DoneBB); 1708 LoadCmpBB->addSuccessor(StoreBB); 1709 1710 // .Lstore: 1711 // strexd rTempReg, rNewLo, rNewHi, [rAddr] 1712 // cmp rTempReg, #0 1713 // bne .Lloadcmp 1714 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; 1715 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); 1716 unsigned Flags = getKillRegState(New.isDead()); 1717 addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI); 1718 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); 1719 1720 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; 1721 BuildMI(StoreBB, DL, TII->get(CMPri)) 1722 .addReg(TempReg, RegState::Kill) 1723 .addImm(0) 1724 .add(predOps(ARMCC::AL)); 1725 BuildMI(StoreBB, DL, TII->get(Bcc)) 1726 .addMBB(LoadCmpBB) 1727 .addImm(ARMCC::NE) 1728 .addReg(ARM::CPSR, RegState::Kill); 1729 StoreBB->addSuccessor(LoadCmpBB); 1730 StoreBB->addSuccessor(DoneBB); 1731 1732 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); 1733 DoneBB->transferSuccessors(&MBB); 1734 1735 MBB.addSuccessor(LoadCmpBB); 1736 1737 NextMBBI = MBB.end(); 1738 MI.eraseFromParent(); 1739 1740 // Recompute livein lists. 1741 LivePhysRegs LiveRegs; 1742 computeAndAddLiveIns(LiveRegs, *DoneBB); 1743 computeAndAddLiveIns(LiveRegs, *StoreBB); 1744 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1745 // Do an extra pass around the loop to get loop carried registers right. 1746 StoreBB->clearLiveIns(); 1747 computeAndAddLiveIns(LiveRegs, *StoreBB); 1748 LoadCmpBB->clearLiveIns(); 1749 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1750 1751 return true; 1752 } 1753 1754 static void CMSEPushCalleeSaves(const TargetInstrInfo &TII, 1755 MachineBasicBlock &MBB, 1756 MachineBasicBlock::iterator MBBI, int JumpReg, 1757 bool Thumb1Only) { 1758 const DebugLoc &DL = MBBI->getDebugLoc(); 1759 if (Thumb1Only) { // push Lo and Hi regs separately 1760 MachineInstrBuilder PushMIB = 1761 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); 1762 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) 1763 PushMIB.addReg(Reg, Reg != JumpReg ? RegState::Undef : 0); 1764 1765 // Thumb1 can only tPUSH low regs, so we copy the high regs to the low 1766 // regs that we just saved and push the low regs again, taking care to 1767 // not clobber JumpReg. If JumpReg is one of the low registers, push first 1768 // the values of r9-r11, and then r8. That would leave them ordered in 1769 // memory, and allow us to later pop them with a single instructions. 1770 // FIXME: Could also use any of r0-r3 that are free (including in the 1771 // first PUSH above). 1772 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { 1773 if (JumpReg == LoReg) 1774 continue; 1775 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) 1776 .addReg(HiReg, RegState::Undef) 1777 .add(predOps(ARMCC::AL)); 1778 --HiReg; 1779 } 1780 MachineInstrBuilder PushMIB2 = 1781 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); 1782 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) { 1783 if (Reg == JumpReg) 1784 continue; 1785 PushMIB2.addReg(Reg, RegState::Kill); 1786 } 1787 1788 // If we couldn't use a low register for temporary storage (because it was 1789 // the JumpReg), use r4 or r5, whichever is not JumpReg. It has already been 1790 // saved. 1791 if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) { 1792 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; 1793 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) 1794 .addReg(ARM::R8) 1795 .add(predOps(ARMCC::AL)); 1796 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)) 1797 .add(predOps(ARMCC::AL)) 1798 .addReg(LoReg); 1799 } 1800 } else { // push Lo and Hi registers with a single instruction 1801 MachineInstrBuilder PushMIB = 1802 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP) 1803 .addReg(ARM::SP) 1804 .add(predOps(ARMCC::AL)); 1805 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) 1806 PushMIB.addReg(Reg, Reg != JumpReg ? RegState::Undef : 0); 1807 } 1808 } 1809 1810 static void CMSEPopCalleeSaves(const TargetInstrInfo &TII, 1811 MachineBasicBlock &MBB, 1812 MachineBasicBlock::iterator MBBI, int JumpReg, 1813 bool Thumb1Only) { 1814 const DebugLoc &DL = MBBI->getDebugLoc(); 1815 if (Thumb1Only) { 1816 MachineInstrBuilder PopMIB = 1817 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); 1818 for (int R = 0; R < 4; ++R) { 1819 PopMIB.addReg(ARM::R4 + R, RegState::Define); 1820 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), ARM::R8 + R) 1821 .addReg(ARM::R4 + R, RegState::Kill) 1822 .add(predOps(ARMCC::AL)); 1823 } 1824 MachineInstrBuilder PopMIB2 = 1825 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); 1826 for (int R = 0; R < 4; ++R) 1827 PopMIB2.addReg(ARM::R4 + R, RegState::Define); 1828 } else { // pop Lo and Hi registers with a single instruction 1829 MachineInstrBuilder PopMIB = 1830 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2LDMIA_UPD), ARM::SP) 1831 .addReg(ARM::SP) 1832 .add(predOps(ARMCC::AL)); 1833 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) 1834 PopMIB.addReg(Reg, RegState::Define); 1835 } 1836 } 1837 1838 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, 1839 MachineBasicBlock::iterator MBBI, 1840 MachineBasicBlock::iterator &NextMBBI) { 1841 MachineInstr &MI = *MBBI; 1842 unsigned Opcode = MI.getOpcode(); 1843 switch (Opcode) { 1844 default: 1845 return false; 1846 1847 case ARM::TCRETURNdi: 1848 case ARM::TCRETURNri: { 1849 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 1850 assert(MBBI->isReturn() && 1851 "Can only insert epilog into returning blocks"); 1852 unsigned RetOpcode = MBBI->getOpcode(); 1853 DebugLoc dl = MBBI->getDebugLoc(); 1854 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>( 1855 MBB.getParent()->getSubtarget().getInstrInfo()); 1856 1857 // Tail call return: adjust the stack pointer and jump to callee. 1858 MBBI = MBB.getLastNonDebugInstr(); 1859 MachineOperand &JumpTarget = MBBI->getOperand(0); 1860 1861 // Jump to label or value in register. 1862 if (RetOpcode == ARM::TCRETURNdi) { 1863 unsigned TCOpcode = 1864 STI->isThumb() 1865 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) 1866 : ARM::TAILJMPd; 1867 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); 1868 if (JumpTarget.isGlobal()) 1869 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 1870 JumpTarget.getTargetFlags()); 1871 else { 1872 assert(JumpTarget.isSymbol()); 1873 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 1874 JumpTarget.getTargetFlags()); 1875 } 1876 1877 // Add the default predicate in Thumb mode. 1878 if (STI->isThumb()) 1879 MIB.add(predOps(ARMCC::AL)); 1880 } else if (RetOpcode == ARM::TCRETURNri) { 1881 unsigned Opcode = 1882 STI->isThumb() ? ARM::tTAILJMPr 1883 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4); 1884 BuildMI(MBB, MBBI, dl, 1885 TII.get(Opcode)) 1886 .addReg(JumpTarget.getReg(), RegState::Kill); 1887 } 1888 1889 auto NewMI = std::prev(MBBI); 1890 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) 1891 NewMI->addOperand(MBBI->getOperand(i)); 1892 1893 1894 // Update call site info and delete the pseudo instruction TCRETURN. 1895 if (MI.isCandidateForCallSiteEntry()) 1896 MI.getMF()->moveCallSiteInfo(&MI, &*NewMI); 1897 MBB.erase(MBBI); 1898 1899 MBBI = NewMI; 1900 return true; 1901 } 1902 case ARM::tBXNS_RET: { 1903 MachineBasicBlock &AfterBB = CMSEClearFPRegs(MBB, MBBI); 1904 1905 if (STI->hasV8_1MMainlineOps()) { 1906 // Restore the non-secure floating point context. 1907 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), 1908 TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP) 1909 .addReg(ARM::SP) 1910 .addImm(4) 1911 .add(predOps(ARMCC::AL)); 1912 } 1913 1914 // Clear all GPR that are not a use of the return instruction. 1915 assert(llvm::all_of(MBBI->operands(), [](const MachineOperand &Op) { 1916 return !Op.isReg() || Op.getReg() != ARM::R12; 1917 })); 1918 SmallVector<unsigned, 5> ClearRegs; 1919 determineGPRegsToClear( 1920 *MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs); 1921 CMSEClearGPRegs(AfterBB, AfterBB.end(), MBBI->getDebugLoc(), ClearRegs, 1922 ARM::LR); 1923 1924 MachineInstrBuilder NewMI = 1925 BuildMI(AfterBB, AfterBB.end(), MBBI->getDebugLoc(), 1926 TII->get(ARM::tBXNS)) 1927 .addReg(ARM::LR) 1928 .add(predOps(ARMCC::AL)); 1929 for (const MachineOperand &Op : MI.operands()) 1930 NewMI->addOperand(Op); 1931 MI.eraseFromParent(); 1932 return true; 1933 } 1934 case ARM::tBLXNS_CALL: { 1935 DebugLoc DL = MBBI->getDebugLoc(); 1936 unsigned JumpReg = MBBI->getOperand(0).getReg(); 1937 CMSEPushCalleeSaves(*TII, MBB, MBBI, JumpReg, 1938 AFI->isThumb1OnlyFunction()); 1939 1940 SmallVector<unsigned, 16> ClearRegs; 1941 determineGPRegsToClear(*MBBI, 1942 {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, 1943 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, 1944 ARM::R10, ARM::R11, ARM::R12}, 1945 ClearRegs); 1946 auto OriginalClearRegs = ClearRegs; 1947 1948 // Get the first cleared register as a scratch (to use later with tBIC). 1949 // We need to use the first so we can ensure it is a low register. 1950 unsigned ScratchReg = ClearRegs.front(); 1951 1952 // Clear LSB of JumpReg 1953 if (AFI->isThumb2Function()) { 1954 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), JumpReg) 1955 .addReg(JumpReg) 1956 .addImm(1) 1957 .add(predOps(ARMCC::AL)) 1958 .add(condCodeOp()); 1959 } else { 1960 // We need to use an extra register to cope with 8M Baseline, 1961 // since we have saved all of the registers we are ok to trash a non 1962 // argument register here. 1963 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVi8), ScratchReg) 1964 .add(condCodeOp()) 1965 .addImm(1) 1966 .add(predOps(ARMCC::AL)); 1967 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBIC), JumpReg) 1968 .addReg(ARM::CPSR, RegState::Define) 1969 .addReg(JumpReg) 1970 .addReg(ScratchReg) 1971 .add(predOps(ARMCC::AL)); 1972 } 1973 1974 CMSESaveClearFPRegs(MBB, MBBI, DL, 1975 ClearRegs); // save+clear FP regs with ClearRegs 1976 CMSEClearGPRegs(MBB, MBBI, DL, ClearRegs, JumpReg); 1977 1978 const MachineInstrBuilder NewCall = 1979 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBLXNSr)) 1980 .add(predOps(ARMCC::AL)) 1981 .addReg(JumpReg, RegState::Kill); 1982 1983 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) 1984 NewCall->addOperand(MI.getOperand(I)); 1985 if (MI.isCandidateForCallSiteEntry()) 1986 MI.getMF()->moveCallSiteInfo(&MI, NewCall.getInstr()); 1987 1988 CMSERestoreFPRegs(MBB, MBBI, DL, OriginalClearRegs); // restore FP registers 1989 1990 CMSEPopCalleeSaves(*TII, MBB, MBBI, JumpReg, AFI->isThumb1OnlyFunction()); 1991 1992 MI.eraseFromParent(); 1993 return true; 1994 } 1995 case ARM::VMOVHcc: 1996 case ARM::VMOVScc: 1997 case ARM::VMOVDcc: { 1998 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD; 1999 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), 2000 MI.getOperand(1).getReg()) 2001 .add(MI.getOperand(2)) 2002 .addImm(MI.getOperand(3).getImm()) // 'pred' 2003 .add(MI.getOperand(4)) 2004 .add(makeImplicit(MI.getOperand(1))); 2005 2006 MI.eraseFromParent(); 2007 return true; 2008 } 2009 case ARM::t2MOVCCr: 2010 case ARM::MOVCCr: { 2011 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; 2012 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 2013 MI.getOperand(1).getReg()) 2014 .add(MI.getOperand(2)) 2015 .addImm(MI.getOperand(3).getImm()) // 'pred' 2016 .add(MI.getOperand(4)) 2017 .add(condCodeOp()) // 's' bit 2018 .add(makeImplicit(MI.getOperand(1))); 2019 2020 MI.eraseFromParent(); 2021 return true; 2022 } 2023 case ARM::MOVCCsi: { 2024 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 2025 (MI.getOperand(1).getReg())) 2026 .add(MI.getOperand(2)) 2027 .addImm(MI.getOperand(3).getImm()) 2028 .addImm(MI.getOperand(4).getImm()) // 'pred' 2029 .add(MI.getOperand(5)) 2030 .add(condCodeOp()) // 's' bit 2031 .add(makeImplicit(MI.getOperand(1))); 2032 2033 MI.eraseFromParent(); 2034 return true; 2035 } 2036 case ARM::MOVCCsr: { 2037 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), 2038 (MI.getOperand(1).getReg())) 2039 .add(MI.getOperand(2)) 2040 .add(MI.getOperand(3)) 2041 .addImm(MI.getOperand(4).getImm()) 2042 .addImm(MI.getOperand(5).getImm()) // 'pred' 2043 .add(MI.getOperand(6)) 2044 .add(condCodeOp()) // 's' bit 2045 .add(makeImplicit(MI.getOperand(1))); 2046 2047 MI.eraseFromParent(); 2048 return true; 2049 } 2050 case ARM::t2MOVCCi16: 2051 case ARM::MOVCCi16: { 2052 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; 2053 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 2054 MI.getOperand(1).getReg()) 2055 .addImm(MI.getOperand(2).getImm()) 2056 .addImm(MI.getOperand(3).getImm()) // 'pred' 2057 .add(MI.getOperand(4)) 2058 .add(makeImplicit(MI.getOperand(1))); 2059 MI.eraseFromParent(); 2060 return true; 2061 } 2062 case ARM::t2MOVCCi: 2063 case ARM::MOVCCi: { 2064 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; 2065 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 2066 MI.getOperand(1).getReg()) 2067 .addImm(MI.getOperand(2).getImm()) 2068 .addImm(MI.getOperand(3).getImm()) // 'pred' 2069 .add(MI.getOperand(4)) 2070 .add(condCodeOp()) // 's' bit 2071 .add(makeImplicit(MI.getOperand(1))); 2072 2073 MI.eraseFromParent(); 2074 return true; 2075 } 2076 case ARM::t2MVNCCi: 2077 case ARM::MVNCCi: { 2078 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; 2079 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 2080 MI.getOperand(1).getReg()) 2081 .addImm(MI.getOperand(2).getImm()) 2082 .addImm(MI.getOperand(3).getImm()) // 'pred' 2083 .add(MI.getOperand(4)) 2084 .add(condCodeOp()) // 's' bit 2085 .add(makeImplicit(MI.getOperand(1))); 2086 2087 MI.eraseFromParent(); 2088 return true; 2089 } 2090 case ARM::t2MOVCClsl: 2091 case ARM::t2MOVCClsr: 2092 case ARM::t2MOVCCasr: 2093 case ARM::t2MOVCCror: { 2094 unsigned NewOpc; 2095 switch (Opcode) { 2096 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; 2097 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; 2098 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; 2099 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; 2100 default: llvm_unreachable("unexpeced conditional move"); 2101 } 2102 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 2103 MI.getOperand(1).getReg()) 2104 .add(MI.getOperand(2)) 2105 .addImm(MI.getOperand(3).getImm()) 2106 .addImm(MI.getOperand(4).getImm()) // 'pred' 2107 .add(MI.getOperand(5)) 2108 .add(condCodeOp()) // 's' bit 2109 .add(makeImplicit(MI.getOperand(1))); 2110 MI.eraseFromParent(); 2111 return true; 2112 } 2113 case ARM::Int_eh_sjlj_dispatchsetup: { 2114 MachineFunction &MF = *MI.getParent()->getParent(); 2115 const ARMBaseInstrInfo *AII = 2116 static_cast<const ARMBaseInstrInfo*>(TII); 2117 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 2118 // For functions using a base pointer, we rematerialize it (via the frame 2119 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it 2120 // for us. Otherwise, expand to nothing. 2121 if (RI.hasBasePointer(MF)) { 2122 int32_t NumBytes = AFI->getFramePtrSpillOffset(); 2123 Register FramePtr = RI.getFrameRegister(MF); 2124 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) && 2125 "base pointer without frame pointer?"); 2126 2127 if (AFI->isThumb2Function()) { 2128 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 2129 FramePtr, -NumBytes, ARMCC::AL, 0, *TII); 2130 } else if (AFI->isThumbFunction()) { 2131 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 2132 FramePtr, -NumBytes, *TII, RI); 2133 } else { 2134 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 2135 FramePtr, -NumBytes, ARMCC::AL, 0, 2136 *TII); 2137 } 2138 // If there's dynamic realignment, adjust for it. 2139 if (RI.needsStackRealignment(MF)) { 2140 MachineFrameInfo &MFI = MF.getFrameInfo(); 2141 Align MaxAlign = MFI.getMaxAlign(); 2142 assert (!AFI->isThumb1OnlyFunction()); 2143 // Emit bic r6, r6, MaxAlign 2144 assert(MaxAlign <= Align(256) && 2145 "The BIC instruction cannot encode " 2146 "immediates larger than 256 with all lower " 2147 "bits set."); 2148 unsigned bicOpc = AFI->isThumbFunction() ? 2149 ARM::t2BICri : ARM::BICri; 2150 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6) 2151 .addReg(ARM::R6, RegState::Kill) 2152 .addImm(MaxAlign.value() - 1) 2153 .add(predOps(ARMCC::AL)) 2154 .add(condCodeOp()); 2155 } 2156 2157 } 2158 MI.eraseFromParent(); 2159 return true; 2160 } 2161 2162 case ARM::MOVsrl_flag: 2163 case ARM::MOVsra_flag: { 2164 // These are just fancy MOVs instructions. 2165 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 2166 MI.getOperand(0).getReg()) 2167 .add(MI.getOperand(1)) 2168 .addImm(ARM_AM::getSORegOpc( 2169 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1)) 2170 .add(predOps(ARMCC::AL)) 2171 .addReg(ARM::CPSR, RegState::Define); 2172 MI.eraseFromParent(); 2173 return true; 2174 } 2175 case ARM::RRX: { 2176 // This encodes as "MOVs Rd, Rm, rrx 2177 MachineInstrBuilder MIB = 2178 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 2179 MI.getOperand(0).getReg()) 2180 .add(MI.getOperand(1)) 2181 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)) 2182 .add(predOps(ARMCC::AL)) 2183 .add(condCodeOp()); 2184 TransferImpOps(MI, MIB, MIB); 2185 MI.eraseFromParent(); 2186 return true; 2187 } 2188 case ARM::tTPsoft: 2189 case ARM::TPsoft: { 2190 const bool Thumb = Opcode == ARM::tTPsoft; 2191 2192 MachineInstrBuilder MIB; 2193 MachineFunction *MF = MBB.getParent(); 2194 if (STI->genLongCalls()) { 2195 MachineConstantPool *MCP = MF->getConstantPool(); 2196 unsigned PCLabelID = AFI->createPICLabelUId(); 2197 MachineConstantPoolValue *CPV = 2198 ARMConstantPoolSymbol::Create(MF->getFunction().getContext(), 2199 "__aeabi_read_tp", PCLabelID, 0); 2200 Register Reg = MI.getOperand(0).getReg(); 2201 MIB = 2202 BuildMI(MBB, MBBI, MI.getDebugLoc(), 2203 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg) 2204 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, Align(4))); 2205 if (!Thumb) 2206 MIB.addImm(0); 2207 MIB.add(predOps(ARMCC::AL)); 2208 2209 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 2210 TII->get(Thumb ? ARM::tBLXr : ARM::BLX)); 2211 if (Thumb) 2212 MIB.add(predOps(ARMCC::AL)); 2213 MIB.addReg(Reg, RegState::Kill); 2214 } else { 2215 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 2216 TII->get(Thumb ? ARM::tBL : ARM::BL)); 2217 if (Thumb) 2218 MIB.add(predOps(ARMCC::AL)); 2219 MIB.addExternalSymbol("__aeabi_read_tp", 0); 2220 } 2221 2222 MIB.cloneMemRefs(MI); 2223 TransferImpOps(MI, MIB, MIB); 2224 // Update the call site info. 2225 if (MI.isCandidateForCallSiteEntry()) 2226 MF->moveCallSiteInfo(&MI, &*MIB); 2227 MI.eraseFromParent(); 2228 return true; 2229 } 2230 case ARM::tLDRpci_pic: 2231 case ARM::t2LDRpci_pic: { 2232 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 2233 ? ARM::tLDRpci : ARM::t2LDRpci; 2234 Register DstReg = MI.getOperand(0).getReg(); 2235 bool DstIsDead = MI.getOperand(0).isDead(); 2236 MachineInstrBuilder MIB1 = 2237 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg) 2238 .add(MI.getOperand(1)) 2239 .add(predOps(ARMCC::AL)); 2240 MIB1.cloneMemRefs(MI); 2241 MachineInstrBuilder MIB2 = 2242 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) 2243 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 2244 .addReg(DstReg) 2245 .add(MI.getOperand(2)); 2246 TransferImpOps(MI, MIB1, MIB2); 2247 MI.eraseFromParent(); 2248 return true; 2249 } 2250 2251 case ARM::LDRLIT_ga_abs: 2252 case ARM::LDRLIT_ga_pcrel: 2253 case ARM::LDRLIT_ga_pcrel_ldr: 2254 case ARM::tLDRLIT_ga_abs: 2255 case ARM::tLDRLIT_ga_pcrel: { 2256 Register DstReg = MI.getOperand(0).getReg(); 2257 bool DstIsDead = MI.getOperand(0).isDead(); 2258 const MachineOperand &MO1 = MI.getOperand(1); 2259 auto Flags = MO1.getTargetFlags(); 2260 const GlobalValue *GV = MO1.getGlobal(); 2261 bool IsARM = 2262 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs; 2263 bool IsPIC = 2264 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; 2265 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; 2266 unsigned PICAddOpc = 2267 IsARM 2268 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 2269 : ARM::tPICADD; 2270 2271 // We need a new const-pool entry to load from. 2272 MachineConstantPool *MCP = MBB.getParent()->getConstantPool(); 2273 unsigned ARMPCLabelIndex = 0; 2274 MachineConstantPoolValue *CPV; 2275 2276 if (IsPIC) { 2277 unsigned PCAdj = IsARM ? 8 : 4; 2278 auto Modifier = (Flags & ARMII::MO_GOT) 2279 ? ARMCP::GOT_PREL 2280 : ARMCP::no_modifier; 2281 ARMPCLabelIndex = AFI->createPICLabelUId(); 2282 CPV = ARMConstantPoolConstant::Create( 2283 GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj, Modifier, 2284 /*AddCurrentAddr*/ Modifier == ARMCP::GOT_PREL); 2285 } else 2286 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier); 2287 2288 MachineInstrBuilder MIB = 2289 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg) 2290 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, Align(4))); 2291 if (IsARM) 2292 MIB.addImm(0); 2293 MIB.add(predOps(ARMCC::AL)); 2294 2295 if (IsPIC) { 2296 MachineInstrBuilder MIB = 2297 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc)) 2298 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 2299 .addReg(DstReg) 2300 .addImm(ARMPCLabelIndex); 2301 2302 if (IsARM) 2303 MIB.add(predOps(ARMCC::AL)); 2304 } 2305 2306 MI.eraseFromParent(); 2307 return true; 2308 } 2309 case ARM::MOV_ga_pcrel: 2310 case ARM::MOV_ga_pcrel_ldr: 2311 case ARM::t2MOV_ga_pcrel: { 2312 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode. 2313 unsigned LabelId = AFI->createPICLabelUId(); 2314 Register DstReg = MI.getOperand(0).getReg(); 2315 bool DstIsDead = MI.getOperand(0).isDead(); 2316 const MachineOperand &MO1 = MI.getOperand(1); 2317 const GlobalValue *GV = MO1.getGlobal(); 2318 unsigned TF = MO1.getTargetFlags(); 2319 bool isARM = Opcode != ARM::t2MOV_ga_pcrel; 2320 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; 2321 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; 2322 unsigned LO16TF = TF | ARMII::MO_LO16; 2323 unsigned HI16TF = TF | ARMII::MO_HI16; 2324 unsigned PICAddOpc = isARM 2325 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 2326 : ARM::tPICADD; 2327 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 2328 TII->get(LO16Opc), DstReg) 2329 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) 2330 .addImm(LabelId); 2331 2332 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg) 2333 .addReg(DstReg) 2334 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) 2335 .addImm(LabelId); 2336 2337 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 2338 TII->get(PICAddOpc)) 2339 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 2340 .addReg(DstReg).addImm(LabelId); 2341 if (isARM) { 2342 MIB3.add(predOps(ARMCC::AL)); 2343 if (Opcode == ARM::MOV_ga_pcrel_ldr) 2344 MIB3.cloneMemRefs(MI); 2345 } 2346 TransferImpOps(MI, MIB1, MIB3); 2347 MI.eraseFromParent(); 2348 return true; 2349 } 2350 2351 case ARM::MOVi32imm: 2352 case ARM::MOVCCi32imm: 2353 case ARM::t2MOVi32imm: 2354 case ARM::t2MOVCCi32imm: 2355 ExpandMOV32BitImm(MBB, MBBI); 2356 return true; 2357 2358 case ARM::SUBS_PC_LR: { 2359 MachineInstrBuilder MIB = 2360 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) 2361 .addReg(ARM::LR) 2362 .add(MI.getOperand(0)) 2363 .add(MI.getOperand(1)) 2364 .add(MI.getOperand(2)) 2365 .addReg(ARM::CPSR, RegState::Undef); 2366 TransferImpOps(MI, MIB, MIB); 2367 MI.eraseFromParent(); 2368 return true; 2369 } 2370 case ARM::VLDMQIA: { 2371 unsigned NewOpc = ARM::VLDMDIA; 2372 MachineInstrBuilder MIB = 2373 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 2374 unsigned OpIdx = 0; 2375 2376 // Grab the Q register destination. 2377 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 2378 Register DstReg = MI.getOperand(OpIdx++).getReg(); 2379 2380 // Copy the source register. 2381 MIB.add(MI.getOperand(OpIdx++)); 2382 2383 // Copy the predicate operands. 2384 MIB.add(MI.getOperand(OpIdx++)); 2385 MIB.add(MI.getOperand(OpIdx++)); 2386 2387 // Add the destination operands (D subregs). 2388 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0); 2389 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1); 2390 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 2391 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 2392 2393 // Add an implicit def for the super-register. 2394 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 2395 TransferImpOps(MI, MIB, MIB); 2396 MIB.cloneMemRefs(MI); 2397 MI.eraseFromParent(); 2398 return true; 2399 } 2400 2401 case ARM::VSTMQIA: { 2402 unsigned NewOpc = ARM::VSTMDIA; 2403 MachineInstrBuilder MIB = 2404 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 2405 unsigned OpIdx = 0; 2406 2407 // Grab the Q register source. 2408 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 2409 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 2410 2411 // Copy the destination register. 2412 MachineOperand Dst(MI.getOperand(OpIdx++)); 2413 MIB.add(Dst); 2414 2415 // Copy the predicate operands. 2416 MIB.add(MI.getOperand(OpIdx++)); 2417 MIB.add(MI.getOperand(OpIdx++)); 2418 2419 // Add the source operands (D subregs). 2420 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); 2421 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); 2422 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) 2423 .addReg(D1, SrcIsKill ? RegState::Kill : 0); 2424 2425 if (SrcIsKill) // Add an implicit kill for the Q register. 2426 MIB->addRegisterKilled(SrcReg, TRI, true); 2427 2428 TransferImpOps(MI, MIB, MIB); 2429 MIB.cloneMemRefs(MI); 2430 MI.eraseFromParent(); 2431 return true; 2432 } 2433 2434 case ARM::VLD2q8Pseudo: 2435 case ARM::VLD2q16Pseudo: 2436 case ARM::VLD2q32Pseudo: 2437 case ARM::VLD2q8PseudoWB_fixed: 2438 case ARM::VLD2q16PseudoWB_fixed: 2439 case ARM::VLD2q32PseudoWB_fixed: 2440 case ARM::VLD2q8PseudoWB_register: 2441 case ARM::VLD2q16PseudoWB_register: 2442 case ARM::VLD2q32PseudoWB_register: 2443 case ARM::VLD3d8Pseudo: 2444 case ARM::VLD3d16Pseudo: 2445 case ARM::VLD3d32Pseudo: 2446 case ARM::VLD1d8TPseudo: 2447 case ARM::VLD1d16TPseudo: 2448 case ARM::VLD1d32TPseudo: 2449 case ARM::VLD1d64TPseudo: 2450 case ARM::VLD1d64TPseudoWB_fixed: 2451 case ARM::VLD1d64TPseudoWB_register: 2452 case ARM::VLD3d8Pseudo_UPD: 2453 case ARM::VLD3d16Pseudo_UPD: 2454 case ARM::VLD3d32Pseudo_UPD: 2455 case ARM::VLD3q8Pseudo_UPD: 2456 case ARM::VLD3q16Pseudo_UPD: 2457 case ARM::VLD3q32Pseudo_UPD: 2458 case ARM::VLD3q8oddPseudo: 2459 case ARM::VLD3q16oddPseudo: 2460 case ARM::VLD3q32oddPseudo: 2461 case ARM::VLD3q8oddPseudo_UPD: 2462 case ARM::VLD3q16oddPseudo_UPD: 2463 case ARM::VLD3q32oddPseudo_UPD: 2464 case ARM::VLD4d8Pseudo: 2465 case ARM::VLD4d16Pseudo: 2466 case ARM::VLD4d32Pseudo: 2467 case ARM::VLD1d8QPseudo: 2468 case ARM::VLD1d16QPseudo: 2469 case ARM::VLD1d32QPseudo: 2470 case ARM::VLD1d64QPseudo: 2471 case ARM::VLD1d64QPseudoWB_fixed: 2472 case ARM::VLD1d64QPseudoWB_register: 2473 case ARM::VLD1q8HighQPseudo: 2474 case ARM::VLD1q8LowQPseudo_UPD: 2475 case ARM::VLD1q8HighTPseudo: 2476 case ARM::VLD1q8LowTPseudo_UPD: 2477 case ARM::VLD1q16HighQPseudo: 2478 case ARM::VLD1q16LowQPseudo_UPD: 2479 case ARM::VLD1q16HighTPseudo: 2480 case ARM::VLD1q16LowTPseudo_UPD: 2481 case ARM::VLD1q32HighQPseudo: 2482 case ARM::VLD1q32LowQPseudo_UPD: 2483 case ARM::VLD1q32HighTPseudo: 2484 case ARM::VLD1q32LowTPseudo_UPD: 2485 case ARM::VLD1q64HighQPseudo: 2486 case ARM::VLD1q64LowQPseudo_UPD: 2487 case ARM::VLD1q64HighTPseudo: 2488 case ARM::VLD1q64LowTPseudo_UPD: 2489 case ARM::VLD4d8Pseudo_UPD: 2490 case ARM::VLD4d16Pseudo_UPD: 2491 case ARM::VLD4d32Pseudo_UPD: 2492 case ARM::VLD4q8Pseudo_UPD: 2493 case ARM::VLD4q16Pseudo_UPD: 2494 case ARM::VLD4q32Pseudo_UPD: 2495 case ARM::VLD4q8oddPseudo: 2496 case ARM::VLD4q16oddPseudo: 2497 case ARM::VLD4q32oddPseudo: 2498 case ARM::VLD4q8oddPseudo_UPD: 2499 case ARM::VLD4q16oddPseudo_UPD: 2500 case ARM::VLD4q32oddPseudo_UPD: 2501 case ARM::VLD3DUPd8Pseudo: 2502 case ARM::VLD3DUPd16Pseudo: 2503 case ARM::VLD3DUPd32Pseudo: 2504 case ARM::VLD3DUPd8Pseudo_UPD: 2505 case ARM::VLD3DUPd16Pseudo_UPD: 2506 case ARM::VLD3DUPd32Pseudo_UPD: 2507 case ARM::VLD4DUPd8Pseudo: 2508 case ARM::VLD4DUPd16Pseudo: 2509 case ARM::VLD4DUPd32Pseudo: 2510 case ARM::VLD4DUPd8Pseudo_UPD: 2511 case ARM::VLD4DUPd16Pseudo_UPD: 2512 case ARM::VLD4DUPd32Pseudo_UPD: 2513 case ARM::VLD2DUPq8EvenPseudo: 2514 case ARM::VLD2DUPq8OddPseudo: 2515 case ARM::VLD2DUPq16EvenPseudo: 2516 case ARM::VLD2DUPq16OddPseudo: 2517 case ARM::VLD2DUPq32EvenPseudo: 2518 case ARM::VLD2DUPq32OddPseudo: 2519 case ARM::VLD3DUPq8EvenPseudo: 2520 case ARM::VLD3DUPq8OddPseudo: 2521 case ARM::VLD3DUPq16EvenPseudo: 2522 case ARM::VLD3DUPq16OddPseudo: 2523 case ARM::VLD3DUPq32EvenPseudo: 2524 case ARM::VLD3DUPq32OddPseudo: 2525 case ARM::VLD4DUPq8EvenPseudo: 2526 case ARM::VLD4DUPq8OddPseudo: 2527 case ARM::VLD4DUPq16EvenPseudo: 2528 case ARM::VLD4DUPq16OddPseudo: 2529 case ARM::VLD4DUPq32EvenPseudo: 2530 case ARM::VLD4DUPq32OddPseudo: 2531 ExpandVLD(MBBI); 2532 return true; 2533 2534 case ARM::VST2q8Pseudo: 2535 case ARM::VST2q16Pseudo: 2536 case ARM::VST2q32Pseudo: 2537 case ARM::VST2q8PseudoWB_fixed: 2538 case ARM::VST2q16PseudoWB_fixed: 2539 case ARM::VST2q32PseudoWB_fixed: 2540 case ARM::VST2q8PseudoWB_register: 2541 case ARM::VST2q16PseudoWB_register: 2542 case ARM::VST2q32PseudoWB_register: 2543 case ARM::VST3d8Pseudo: 2544 case ARM::VST3d16Pseudo: 2545 case ARM::VST3d32Pseudo: 2546 case ARM::VST1d8TPseudo: 2547 case ARM::VST1d16TPseudo: 2548 case ARM::VST1d32TPseudo: 2549 case ARM::VST1d64TPseudo: 2550 case ARM::VST3d8Pseudo_UPD: 2551 case ARM::VST3d16Pseudo_UPD: 2552 case ARM::VST3d32Pseudo_UPD: 2553 case ARM::VST1d64TPseudoWB_fixed: 2554 case ARM::VST1d64TPseudoWB_register: 2555 case ARM::VST3q8Pseudo_UPD: 2556 case ARM::VST3q16Pseudo_UPD: 2557 case ARM::VST3q32Pseudo_UPD: 2558 case ARM::VST3q8oddPseudo: 2559 case ARM::VST3q16oddPseudo: 2560 case ARM::VST3q32oddPseudo: 2561 case ARM::VST3q8oddPseudo_UPD: 2562 case ARM::VST3q16oddPseudo_UPD: 2563 case ARM::VST3q32oddPseudo_UPD: 2564 case ARM::VST4d8Pseudo: 2565 case ARM::VST4d16Pseudo: 2566 case ARM::VST4d32Pseudo: 2567 case ARM::VST1d8QPseudo: 2568 case ARM::VST1d16QPseudo: 2569 case ARM::VST1d32QPseudo: 2570 case ARM::VST1d64QPseudo: 2571 case ARM::VST4d8Pseudo_UPD: 2572 case ARM::VST4d16Pseudo_UPD: 2573 case ARM::VST4d32Pseudo_UPD: 2574 case ARM::VST1d64QPseudoWB_fixed: 2575 case ARM::VST1d64QPseudoWB_register: 2576 case ARM::VST1q8HighQPseudo: 2577 case ARM::VST1q8LowQPseudo_UPD: 2578 case ARM::VST1q8HighTPseudo: 2579 case ARM::VST1q8LowTPseudo_UPD: 2580 case ARM::VST1q16HighQPseudo: 2581 case ARM::VST1q16LowQPseudo_UPD: 2582 case ARM::VST1q16HighTPseudo: 2583 case ARM::VST1q16LowTPseudo_UPD: 2584 case ARM::VST1q32HighQPseudo: 2585 case ARM::VST1q32LowQPseudo_UPD: 2586 case ARM::VST1q32HighTPseudo: 2587 case ARM::VST1q32LowTPseudo_UPD: 2588 case ARM::VST1q64HighQPseudo: 2589 case ARM::VST1q64LowQPseudo_UPD: 2590 case ARM::VST1q64HighTPseudo: 2591 case ARM::VST1q64LowTPseudo_UPD: 2592 case ARM::VST4q8Pseudo_UPD: 2593 case ARM::VST4q16Pseudo_UPD: 2594 case ARM::VST4q32Pseudo_UPD: 2595 case ARM::VST4q8oddPseudo: 2596 case ARM::VST4q16oddPseudo: 2597 case ARM::VST4q32oddPseudo: 2598 case ARM::VST4q8oddPseudo_UPD: 2599 case ARM::VST4q16oddPseudo_UPD: 2600 case ARM::VST4q32oddPseudo_UPD: 2601 ExpandVST(MBBI); 2602 return true; 2603 2604 case ARM::VLD1LNq8Pseudo: 2605 case ARM::VLD1LNq16Pseudo: 2606 case ARM::VLD1LNq32Pseudo: 2607 case ARM::VLD1LNq8Pseudo_UPD: 2608 case ARM::VLD1LNq16Pseudo_UPD: 2609 case ARM::VLD1LNq32Pseudo_UPD: 2610 case ARM::VLD2LNd8Pseudo: 2611 case ARM::VLD2LNd16Pseudo: 2612 case ARM::VLD2LNd32Pseudo: 2613 case ARM::VLD2LNq16Pseudo: 2614 case ARM::VLD2LNq32Pseudo: 2615 case ARM::VLD2LNd8Pseudo_UPD: 2616 case ARM::VLD2LNd16Pseudo_UPD: 2617 case ARM::VLD2LNd32Pseudo_UPD: 2618 case ARM::VLD2LNq16Pseudo_UPD: 2619 case ARM::VLD2LNq32Pseudo_UPD: 2620 case ARM::VLD3LNd8Pseudo: 2621 case ARM::VLD3LNd16Pseudo: 2622 case ARM::VLD3LNd32Pseudo: 2623 case ARM::VLD3LNq16Pseudo: 2624 case ARM::VLD3LNq32Pseudo: 2625 case ARM::VLD3LNd8Pseudo_UPD: 2626 case ARM::VLD3LNd16Pseudo_UPD: 2627 case ARM::VLD3LNd32Pseudo_UPD: 2628 case ARM::VLD3LNq16Pseudo_UPD: 2629 case ARM::VLD3LNq32Pseudo_UPD: 2630 case ARM::VLD4LNd8Pseudo: 2631 case ARM::VLD4LNd16Pseudo: 2632 case ARM::VLD4LNd32Pseudo: 2633 case ARM::VLD4LNq16Pseudo: 2634 case ARM::VLD4LNq32Pseudo: 2635 case ARM::VLD4LNd8Pseudo_UPD: 2636 case ARM::VLD4LNd16Pseudo_UPD: 2637 case ARM::VLD4LNd32Pseudo_UPD: 2638 case ARM::VLD4LNq16Pseudo_UPD: 2639 case ARM::VLD4LNq32Pseudo_UPD: 2640 case ARM::VST1LNq8Pseudo: 2641 case ARM::VST1LNq16Pseudo: 2642 case ARM::VST1LNq32Pseudo: 2643 case ARM::VST1LNq8Pseudo_UPD: 2644 case ARM::VST1LNq16Pseudo_UPD: 2645 case ARM::VST1LNq32Pseudo_UPD: 2646 case ARM::VST2LNd8Pseudo: 2647 case ARM::VST2LNd16Pseudo: 2648 case ARM::VST2LNd32Pseudo: 2649 case ARM::VST2LNq16Pseudo: 2650 case ARM::VST2LNq32Pseudo: 2651 case ARM::VST2LNd8Pseudo_UPD: 2652 case ARM::VST2LNd16Pseudo_UPD: 2653 case ARM::VST2LNd32Pseudo_UPD: 2654 case ARM::VST2LNq16Pseudo_UPD: 2655 case ARM::VST2LNq32Pseudo_UPD: 2656 case ARM::VST3LNd8Pseudo: 2657 case ARM::VST3LNd16Pseudo: 2658 case ARM::VST3LNd32Pseudo: 2659 case ARM::VST3LNq16Pseudo: 2660 case ARM::VST3LNq32Pseudo: 2661 case ARM::VST3LNd8Pseudo_UPD: 2662 case ARM::VST3LNd16Pseudo_UPD: 2663 case ARM::VST3LNd32Pseudo_UPD: 2664 case ARM::VST3LNq16Pseudo_UPD: 2665 case ARM::VST3LNq32Pseudo_UPD: 2666 case ARM::VST4LNd8Pseudo: 2667 case ARM::VST4LNd16Pseudo: 2668 case ARM::VST4LNd32Pseudo: 2669 case ARM::VST4LNq16Pseudo: 2670 case ARM::VST4LNq32Pseudo: 2671 case ARM::VST4LNd8Pseudo_UPD: 2672 case ARM::VST4LNd16Pseudo_UPD: 2673 case ARM::VST4LNd32Pseudo_UPD: 2674 case ARM::VST4LNq16Pseudo_UPD: 2675 case ARM::VST4LNq32Pseudo_UPD: 2676 ExpandLaneOp(MBBI); 2677 return true; 2678 2679 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; 2680 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; 2681 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; 2682 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; 2683 2684 case ARM::CMP_SWAP_8: 2685 if (STI->isThumb()) 2686 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, 2687 ARM::tUXTB, NextMBBI); 2688 else 2689 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, 2690 ARM::UXTB, NextMBBI); 2691 case ARM::CMP_SWAP_16: 2692 if (STI->isThumb()) 2693 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, 2694 ARM::tUXTH, NextMBBI); 2695 else 2696 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, 2697 ARM::UXTH, NextMBBI); 2698 case ARM::CMP_SWAP_32: 2699 if (STI->isThumb()) 2700 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, 2701 NextMBBI); 2702 else 2703 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); 2704 2705 case ARM::CMP_SWAP_64: 2706 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI); 2707 2708 case ARM::tBL_PUSHLR: 2709 case ARM::BL_PUSHLR: { 2710 const bool Thumb = Opcode == ARM::tBL_PUSHLR; 2711 Register Reg = MI.getOperand(0).getReg(); 2712 assert(Reg == ARM::LR && "expect LR register!"); 2713 MachineInstrBuilder MIB; 2714 if (Thumb) { 2715 // push {lr} 2716 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH)) 2717 .add(predOps(ARMCC::AL)) 2718 .addReg(Reg); 2719 2720 // bl __gnu_mcount_nc 2721 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL)); 2722 } else { 2723 // stmdb sp!, {lr} 2724 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD)) 2725 .addReg(ARM::SP, RegState::Define) 2726 .addReg(ARM::SP) 2727 .add(predOps(ARMCC::AL)) 2728 .addReg(Reg); 2729 2730 // bl __gnu_mcount_nc 2731 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL)); 2732 } 2733 MIB.cloneMemRefs(MI); 2734 for (unsigned i = 1; i < MI.getNumOperands(); ++i) MIB.add(MI.getOperand(i)); 2735 MI.eraseFromParent(); 2736 return true; 2737 } 2738 } 2739 } 2740 2741 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 2742 bool Modified = false; 2743 2744 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 2745 while (MBBI != E) { 2746 MachineBasicBlock::iterator NMBBI = std::next(MBBI); 2747 Modified |= ExpandMI(MBB, MBBI, NMBBI); 2748 MBBI = NMBBI; 2749 } 2750 2751 return Modified; 2752 } 2753 2754 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 2755 STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget()); 2756 TII = STI->getInstrInfo(); 2757 TRI = STI->getRegisterInfo(); 2758 AFI = MF.getInfo<ARMFunctionInfo>(); 2759 2760 LLVM_DEBUG(dbgs() << "********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n" 2761 << "********** Function: " << MF.getName() << '\n'); 2762 2763 bool Modified = false; 2764 for (MachineBasicBlock &MBB : MF) 2765 Modified |= ExpandMBB(MBB); 2766 if (VerifyARMPseudo) 2767 MF.verify(this, "After expanding ARM pseudo instructions."); 2768 2769 LLVM_DEBUG(dbgs() << "***************************************************\n"); 2770 return Modified; 2771 } 2772 2773 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction 2774 /// expansion pass. 2775 FunctionPass *llvm::createARMExpandPseudoPass() { 2776 return new ARMExpandPseudo(); 2777 } 2778