1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #define DEBUG_TYPE "arm-pseudo"
18 #include "ARM.h"
19 #include "ARMBaseInstrInfo.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMRegisterInfo.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/Target/TargetFrameLowering.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
31 using namespace llvm;
32 
33 static cl::opt<bool>
34 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
35                 cl::desc("Verify machine code after expanding ARM pseudos"));
36 
37 namespace {
38   class ARMExpandPseudo : public MachineFunctionPass {
39   public:
40     static char ID;
41     ARMExpandPseudo() : MachineFunctionPass(ID) {}
42 
43     const ARMBaseInstrInfo *TII;
44     const TargetRegisterInfo *TRI;
45     const ARMSubtarget *STI;
46     ARMFunctionInfo *AFI;
47 
48     virtual bool runOnMachineFunction(MachineFunction &Fn);
49 
50     virtual const char *getPassName() const {
51       return "ARM pseudo instruction expansion pass";
52     }
53 
54   private:
55     void TransferImpOps(MachineInstr &OldMI,
56                         MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
57     bool ExpandMI(MachineBasicBlock &MBB,
58                   MachineBasicBlock::iterator MBBI);
59     bool ExpandMBB(MachineBasicBlock &MBB);
60     void ExpandVLD(MachineBasicBlock::iterator &MBBI);
61     void ExpandVST(MachineBasicBlock::iterator &MBBI);
62     void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
63     void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
64                     unsigned Opc, bool IsExt, unsigned NumRegs);
65     void ExpandMOV32BitImm(MachineBasicBlock &MBB,
66                            MachineBasicBlock::iterator &MBBI);
67   };
68   char ARMExpandPseudo::ID = 0;
69 }
70 
71 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
72 /// the instructions created from the expansion.
73 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
74                                      MachineInstrBuilder &UseMI,
75                                      MachineInstrBuilder &DefMI) {
76   const MCInstrDesc &Desc = OldMI.getDesc();
77   for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
78        i != e; ++i) {
79     const MachineOperand &MO = OldMI.getOperand(i);
80     assert(MO.isReg() && MO.getReg());
81     if (MO.isUse())
82       UseMI.addOperand(MO);
83     else
84       DefMI.addOperand(MO);
85   }
86 }
87 
88 namespace {
89   // Constants for register spacing in NEON load/store instructions.
90   // For quad-register load-lane and store-lane pseudo instructors, the
91   // spacing is initially assumed to be EvenDblSpc, and that is changed to
92   // OddDblSpc depending on the lane number operand.
93   enum NEONRegSpacing {
94     SingleSpc,
95     EvenDblSpc,
96     OddDblSpc
97   };
98 
99   // Entries for NEON load/store information table.  The table is sorted by
100   // PseudoOpc for fast binary-search lookups.
101   struct NEONLdStTableEntry {
102     unsigned PseudoOpc;
103     unsigned RealOpc;
104     bool IsLoad;
105     bool isUpdating;
106     bool hasWritebackOperand;
107     NEONRegSpacing RegSpacing;
108     unsigned char NumRegs; // D registers loaded or stored
109     unsigned char RegElts; // elements per D register; used for lane ops
110     // FIXME: Temporary flag to denote whether the real instruction takes
111     // a single register (like the encoding) or all of the registers in
112     // the list (like the asm syntax and the isel DAG). When all definitions
113     // are converted to take only the single encoded register, this will
114     // go away.
115     bool copyAllListRegs;
116 
117     // Comparison methods for binary search of the table.
118     bool operator<(const NEONLdStTableEntry &TE) const {
119       return PseudoOpc < TE.PseudoOpc;
120     }
121     friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
122       return TE.PseudoOpc < PseudoOpc;
123     }
124     friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
125                                                 const NEONLdStTableEntry &TE) {
126       return PseudoOpc < TE.PseudoOpc;
127     }
128   };
129 }
130 
131 static const NEONLdStTableEntry NEONLdStTable[] = {
132 { ARM::VLD1DUPq16Pseudo,     ARM::VLD1DUPq16,     true, false, false, SingleSpc, 2, 4,true},
133 { ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true, true,  SingleSpc, 2, 4,true},
134 { ARM::VLD1DUPq32Pseudo,     ARM::VLD1DUPq32,     true, false, false, SingleSpc, 2, 2,true},
135 { ARM::VLD1DUPq32Pseudo_UPD, ARM::VLD1DUPq32_UPD, true, true, true,  SingleSpc, 2, 2,true},
136 { ARM::VLD1DUPq8Pseudo,      ARM::VLD1DUPq8,      true, false, false, SingleSpc, 2, 8,true},
137 { ARM::VLD1DUPq8Pseudo_UPD,  ARM::VLD1DUPq8_UPD, true, true, true,  SingleSpc, 2, 8,true},
138 
139 { ARM::VLD1LNq16Pseudo,     ARM::VLD1LNd16,     true, false, false, EvenDblSpc, 1, 4 ,true},
140 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true,  EvenDblSpc, 1, 4 ,true},
141 { ARM::VLD1LNq32Pseudo,     ARM::VLD1LNd32,     true, false, false, EvenDblSpc, 1, 2 ,true},
142 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true,  EvenDblSpc, 1, 2 ,true},
143 { ARM::VLD1LNq8Pseudo,      ARM::VLD1LNd8,      true, false, false, EvenDblSpc, 1, 8 ,true},
144 { ARM::VLD1LNq8Pseudo_UPD,  ARM::VLD1LNd8_UPD, true, true, true,  EvenDblSpc, 1, 8 ,true},
145 
146 { ARM::VLD1d64QPseudo,      ARM::VLD1d64Q,     true,  false, false, SingleSpc,  4, 1 ,false},
147 { ARM::VLD1d64TPseudo,      ARM::VLD1d64T,     true,  false, false, SingleSpc,  3, 1 ,false},
148 { ARM::VLD1q16Pseudo,       ARM::VLD1q16,      true,  false, false, SingleSpc,  2, 4 ,false},
149 { ARM::VLD1q16PseudoWB_fixed, ARM::VLD1q16wb_fixed,true,false,false,SingleSpc, 2, 4 ,false},
150 { ARM::VLD1q16PseudoWB_register, ARM::VLD1q16wb_register, true, true, true, SingleSpc, 2, 4 ,false},
151 { ARM::VLD1q32Pseudo,       ARM::VLD1q32,      true,  false, false, SingleSpc,  2, 2 ,false},
152 { ARM::VLD1q32PseudoWB_fixed, ARM::VLD1q32wb_fixed,true,false, false,SingleSpc, 2, 2 ,false},
153 { ARM::VLD1q32PseudoWB_register, ARM::VLD1q32wb_register, true, true, true, SingleSpc, 2, 2 ,false},
154 { ARM::VLD1q64Pseudo,       ARM::VLD1q64,      true,  false, false, SingleSpc,  2, 1 ,false},
155 { ARM::VLD1q64PseudoWB_fixed, ARM::VLD1q64wb_fixed,true,false, false,SingleSpc, 2, 2 ,false},
156 { ARM::VLD1q64PseudoWB_register, ARM::VLD1q64wb_register, true, true, true, SingleSpc, 2, 1 ,false},
157 { ARM::VLD1q8Pseudo,        ARM::VLD1q8,       true,  false, false, SingleSpc,  2, 8 ,false},
158 { ARM::VLD1q8PseudoWB_fixed, ARM::VLD1q8wb_fixed,true,false, false, SingleSpc,  2, 8 ,false},
159 { ARM::VLD1q8PseudoWB_register, ARM::VLD1q8wb_register,true,true, true,SingleSpc,2,8,false},
160 
161 { ARM::VLD2DUPd16Pseudo,     ARM::VLD2DUPd16,     true, false, false, SingleSpc, 2, 4,true},
162 { ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true, true,  SingleSpc, 2, 4,true},
163 { ARM::VLD2DUPd32Pseudo,     ARM::VLD2DUPd32,     true, false, false, SingleSpc, 2, 2,true},
164 { ARM::VLD2DUPd32Pseudo_UPD, ARM::VLD2DUPd32_UPD, true, true, true,  SingleSpc, 2, 2,true},
165 { ARM::VLD2DUPd8Pseudo,      ARM::VLD2DUPd8,      true, false, false, SingleSpc, 2, 8,true},
166 { ARM::VLD2DUPd8Pseudo_UPD,  ARM::VLD2DUPd8_UPD, true, true, true,  SingleSpc, 2, 8,true},
167 
168 { ARM::VLD2LNd16Pseudo,     ARM::VLD2LNd16,     true, false, false, SingleSpc,  2, 4 ,true},
169 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true,  SingleSpc,  2, 4 ,true},
170 { ARM::VLD2LNd32Pseudo,     ARM::VLD2LNd32,     true, false, false, SingleSpc,  2, 2 ,true},
171 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true,  SingleSpc,  2, 2 ,true},
172 { ARM::VLD2LNd8Pseudo,      ARM::VLD2LNd8,      true, false, false, SingleSpc,  2, 8 ,true},
173 { ARM::VLD2LNd8Pseudo_UPD,  ARM::VLD2LNd8_UPD, true, true, true,  SingleSpc,  2, 8 ,true},
174 { ARM::VLD2LNq16Pseudo,     ARM::VLD2LNq16,     true, false, false, EvenDblSpc, 2, 4 ,true},
175 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true,  EvenDblSpc, 2, 4 ,true},
176 { ARM::VLD2LNq32Pseudo,     ARM::VLD2LNq32,     true, false, false, EvenDblSpc, 2, 2 ,true},
177 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true,  EvenDblSpc, 2, 2 ,true},
178 
179 { ARM::VLD2d16Pseudo,       ARM::VLD2d16,      true,  false, false, SingleSpc,  2, 4 ,false},
180 { ARM::VLD2d16Pseudo_UPD,   ARM::VLD2d16_UPD, true, true, true,  SingleSpc,  2, 4 ,false},
181 { ARM::VLD2d32Pseudo,       ARM::VLD2d32,      true,  false, false, SingleSpc,  2, 2 ,false},
182 { ARM::VLD2d32Pseudo_UPD,   ARM::VLD2d32_UPD, true, true, true,  SingleSpc,  2, 2 ,false},
183 { ARM::VLD2d8Pseudo,        ARM::VLD2d8,       true,  false, false, SingleSpc,  2, 8 ,false},
184 { ARM::VLD2d8Pseudo_UPD,    ARM::VLD2d8_UPD, true, true, true,  SingleSpc,  2, 8 ,false},
185 
186 { ARM::VLD2q16Pseudo,       ARM::VLD2q16,      true,  false, false, SingleSpc,  4, 4 ,false},
187 { ARM::VLD2q16Pseudo_UPD,   ARM::VLD2q16_UPD, true, true, true,  SingleSpc,  4, 4 ,false},
188 { ARM::VLD2q32Pseudo,       ARM::VLD2q32,      true,  false, false, SingleSpc,  4, 2 ,false},
189 { ARM::VLD2q32Pseudo_UPD,   ARM::VLD2q32_UPD, true, true, true,  SingleSpc,  4, 2 ,false},
190 { ARM::VLD2q8Pseudo,        ARM::VLD2q8,       true,  false, false, SingleSpc,  4, 8 ,false},
191 { ARM::VLD2q8Pseudo_UPD,    ARM::VLD2q8_UPD, true, true, true,  SingleSpc,  4, 8 ,false},
192 
193 { ARM::VLD3DUPd16Pseudo,     ARM::VLD3DUPd16,     true, false, false, SingleSpc, 3, 4,true},
194 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true,  SingleSpc, 3, 4,true},
195 { ARM::VLD3DUPd32Pseudo,     ARM::VLD3DUPd32,     true, false, false, SingleSpc, 3, 2,true},
196 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true,  SingleSpc, 3, 2,true},
197 { ARM::VLD3DUPd8Pseudo,      ARM::VLD3DUPd8,      true, false, false, SingleSpc, 3, 8,true},
198 { ARM::VLD3DUPd8Pseudo_UPD,  ARM::VLD3DUPd8_UPD, true, true, true,  SingleSpc, 3, 8,true},
199 
200 { ARM::VLD3LNd16Pseudo,     ARM::VLD3LNd16,     true, false, false, SingleSpc,  3, 4 ,true},
201 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true,  SingleSpc,  3, 4 ,true},
202 { ARM::VLD3LNd32Pseudo,     ARM::VLD3LNd32,     true, false, false, SingleSpc,  3, 2 ,true},
203 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true,  SingleSpc,  3, 2 ,true},
204 { ARM::VLD3LNd8Pseudo,      ARM::VLD3LNd8,      true, false, false, SingleSpc,  3, 8 ,true},
205 { ARM::VLD3LNd8Pseudo_UPD,  ARM::VLD3LNd8_UPD, true, true, true,  SingleSpc,  3, 8 ,true},
206 { ARM::VLD3LNq16Pseudo,     ARM::VLD3LNq16,     true, false, false, EvenDblSpc, 3, 4 ,true},
207 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true,  EvenDblSpc, 3, 4 ,true},
208 { ARM::VLD3LNq32Pseudo,     ARM::VLD3LNq32,     true, false, false, EvenDblSpc, 3, 2 ,true},
209 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true,  EvenDblSpc, 3, 2 ,true},
210 
211 { ARM::VLD3d16Pseudo,       ARM::VLD3d16,      true,  false, false, SingleSpc,  3, 4 ,true},
212 { ARM::VLD3d16Pseudo_UPD,   ARM::VLD3d16_UPD, true, true, true,  SingleSpc,  3, 4 ,true},
213 { ARM::VLD3d32Pseudo,       ARM::VLD3d32,      true,  false, false, SingleSpc,  3, 2 ,true},
214 { ARM::VLD3d32Pseudo_UPD,   ARM::VLD3d32_UPD, true, true, true,  SingleSpc,  3, 2 ,true},
215 { ARM::VLD3d8Pseudo,        ARM::VLD3d8,       true,  false, false, SingleSpc,  3, 8 ,true},
216 { ARM::VLD3d8Pseudo_UPD,    ARM::VLD3d8_UPD, true, true, true,  SingleSpc,  3, 8 ,true},
217 
218 { ARM::VLD3q16Pseudo_UPD,    ARM::VLD3q16_UPD, true, true, true,  EvenDblSpc, 3, 4 ,true},
219 { ARM::VLD3q16oddPseudo,     ARM::VLD3q16,     true,  false, false, OddDblSpc,  3, 4 ,true},
220 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true,  OddDblSpc,  3, 4 ,true},
221 { ARM::VLD3q32Pseudo_UPD,    ARM::VLD3q32_UPD, true, true, true,  EvenDblSpc, 3, 2 ,true},
222 { ARM::VLD3q32oddPseudo,     ARM::VLD3q32,     true,  false, false, OddDblSpc,  3, 2 ,true},
223 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true,  OddDblSpc,  3, 2 ,true},
224 { ARM::VLD3q8Pseudo_UPD,     ARM::VLD3q8_UPD, true, true, true,  EvenDblSpc, 3, 8 ,true},
225 { ARM::VLD3q8oddPseudo,      ARM::VLD3q8,      true,  false, false, OddDblSpc,  3, 8 ,true},
226 { ARM::VLD3q8oddPseudo_UPD,  ARM::VLD3q8_UPD, true, true, true,  OddDblSpc,  3, 8 ,true},
227 
228 { ARM::VLD4DUPd16Pseudo,     ARM::VLD4DUPd16,     true, false, false, SingleSpc, 4, 4,true},
229 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true,  SingleSpc, 4, 4,true},
230 { ARM::VLD4DUPd32Pseudo,     ARM::VLD4DUPd32,     true, false, false, SingleSpc, 4, 2,true},
231 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true,  SingleSpc, 4, 2,true},
232 { ARM::VLD4DUPd8Pseudo,      ARM::VLD4DUPd8,      true, false, false, SingleSpc, 4, 8,true},
233 { ARM::VLD4DUPd8Pseudo_UPD,  ARM::VLD4DUPd8_UPD, true, true, true,  SingleSpc, 4, 8,true},
234 
235 { ARM::VLD4LNd16Pseudo,     ARM::VLD4LNd16,     true, false, false, SingleSpc,  4, 4 ,true},
236 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true,  SingleSpc,  4, 4 ,true},
237 { ARM::VLD4LNd32Pseudo,     ARM::VLD4LNd32,     true, false, false, SingleSpc,  4, 2 ,true},
238 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true,  SingleSpc,  4, 2 ,true},
239 { ARM::VLD4LNd8Pseudo,      ARM::VLD4LNd8,      true, false, false, SingleSpc,  4, 8 ,true},
240 { ARM::VLD4LNd8Pseudo_UPD,  ARM::VLD4LNd8_UPD, true, true, true,  SingleSpc,  4, 8 ,true},
241 { ARM::VLD4LNq16Pseudo,     ARM::VLD4LNq16,     true, false, false, EvenDblSpc, 4, 4 ,true},
242 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true,  EvenDblSpc, 4, 4 ,true},
243 { ARM::VLD4LNq32Pseudo,     ARM::VLD4LNq32,     true, false, false, EvenDblSpc, 4, 2 ,true},
244 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true,  EvenDblSpc, 4, 2 ,true},
245 
246 { ARM::VLD4d16Pseudo,       ARM::VLD4d16,      true,  false, false, SingleSpc,  4, 4 ,true},
247 { ARM::VLD4d16Pseudo_UPD,   ARM::VLD4d16_UPD, true, true, true,  SingleSpc,  4, 4 ,true},
248 { ARM::VLD4d32Pseudo,       ARM::VLD4d32,      true,  false, false, SingleSpc,  4, 2 ,true},
249 { ARM::VLD4d32Pseudo_UPD,   ARM::VLD4d32_UPD, true, true, true,  SingleSpc,  4, 2 ,true},
250 { ARM::VLD4d8Pseudo,        ARM::VLD4d8,       true,  false, false, SingleSpc,  4, 8 ,true},
251 { ARM::VLD4d8Pseudo_UPD,    ARM::VLD4d8_UPD, true, true, true,  SingleSpc,  4, 8 ,true},
252 
253 { ARM::VLD4q16Pseudo_UPD,    ARM::VLD4q16_UPD, true, true, true,  EvenDblSpc, 4, 4 ,true},
254 { ARM::VLD4q16oddPseudo,     ARM::VLD4q16,     true,  false, false, OddDblSpc,  4, 4 ,true},
255 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true,  OddDblSpc,  4, 4 ,true},
256 { ARM::VLD4q32Pseudo_UPD,    ARM::VLD4q32_UPD, true, true, true,  EvenDblSpc, 4, 2 ,true},
257 { ARM::VLD4q32oddPseudo,     ARM::VLD4q32,     true,  false, false, OddDblSpc,  4, 2 ,true},
258 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true,  OddDblSpc,  4, 2 ,true},
259 { ARM::VLD4q8Pseudo_UPD,     ARM::VLD4q8_UPD, true, true, true,  EvenDblSpc, 4, 8 ,true},
260 { ARM::VLD4q8oddPseudo,      ARM::VLD4q8,      true,  false, false, OddDblSpc,  4, 8 ,true},
261 { ARM::VLD4q8oddPseudo_UPD,  ARM::VLD4q8_UPD, true, true, true,  OddDblSpc,  4, 8 ,true},
262 
263 { ARM::VST1LNq16Pseudo,     ARM::VST1LNd16,    false, false, false, EvenDblSpc, 1, 4 ,true},
264 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true,  EvenDblSpc, 1, 4 ,true},
265 { ARM::VST1LNq32Pseudo,     ARM::VST1LNd32,    false, false, false, EvenDblSpc, 1, 2 ,true},
266 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true,  EvenDblSpc, 1, 2 ,true},
267 { ARM::VST1LNq8Pseudo,      ARM::VST1LNd8,     false, false, false, EvenDblSpc, 1, 8 ,true},
268 { ARM::VST1LNq8Pseudo_UPD,  ARM::VST1LNd8_UPD, false, true, true,  EvenDblSpc, 1, 8 ,true},
269 
270 { ARM::VST1d64QPseudo,      ARM::VST1d64Q,     false, false, false, SingleSpc,  4, 1 ,true},
271 { ARM::VST1d64QPseudo_UPD,  ARM::VST1d64Q_UPD, false, true, true,  SingleSpc,  4, 1 ,true},
272 { ARM::VST1d64TPseudo,      ARM::VST1d64T,     false, false, false, SingleSpc,  3, 1 ,true},
273 { ARM::VST1d64TPseudo_UPD,  ARM::VST1d64T_UPD, false, true, true,  SingleSpc,  3, 1 ,true},
274 
275 { ARM::VST1q16Pseudo,       ARM::VST1q16,      false, false, false, SingleSpc,  2, 4 ,false},
276 { ARM::VST1q16PseudoWB_fixed,   ARM::VST1q16wb_fixed, false, true, false,  SingleSpc,  2, 4 ,false},
277 { ARM::VST1q16PseudoWB_register,   ARM::VST1q16wb_register, false, true, true,  SingleSpc,  2, 4 ,false},
278 { ARM::VST1q32Pseudo,       ARM::VST1q32,      false, false, false, SingleSpc,  2, 2 ,false},
279 { ARM::VST1q32PseudoWB_fixed,   ARM::VST1q32wb_fixed, false, true, false,  SingleSpc,  2, 2 ,false},
280 { ARM::VST1q32PseudoWB_register,   ARM::VST1q32wb_register, false, true, true,  SingleSpc,  2, 2 ,false},
281 { ARM::VST1q64Pseudo,       ARM::VST1q64,      false, false, false, SingleSpc,  2, 1 ,false},
282 { ARM::VST1q64PseudoWB_fixed,   ARM::VST1q64wb_fixed, false, true, false,  SingleSpc,  2, 1 ,false},
283 { ARM::VST1q64PseudoWB_register,   ARM::VST1q64wb_register, false, true, true,  SingleSpc,  2, 1 ,false},
284 { ARM::VST1q8Pseudo,        ARM::VST1q8,       false, false, false, SingleSpc,  2, 8 ,false},
285 { ARM::VST1q8PseudoWB_fixed,    ARM::VST1q8wb_fixed, false, true, false,  SingleSpc,  2, 8 ,false},
286 { ARM::VST1q8PseudoWB_register,    ARM::VST1q8wb_register, false, true, true,  SingleSpc,  2, 8 ,false},
287 
288 { ARM::VST2LNd16Pseudo,     ARM::VST2LNd16,     false, false, false, SingleSpc, 2, 4 ,true},
289 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true,  SingleSpc, 2, 4 ,true},
290 { ARM::VST2LNd32Pseudo,     ARM::VST2LNd32,     false, false, false, SingleSpc, 2, 2 ,true},
291 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true,  SingleSpc, 2, 2 ,true},
292 { ARM::VST2LNd8Pseudo,      ARM::VST2LNd8,      false, false, false, SingleSpc, 2, 8 ,true},
293 { ARM::VST2LNd8Pseudo_UPD,  ARM::VST2LNd8_UPD, false, true, true,  SingleSpc, 2, 8 ,true},
294 { ARM::VST2LNq16Pseudo,     ARM::VST2LNq16,     false, false, false, EvenDblSpc, 2, 4,true},
295 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true,  EvenDblSpc, 2, 4,true},
296 { ARM::VST2LNq32Pseudo,     ARM::VST2LNq32,     false, false, false, EvenDblSpc, 2, 2,true},
297 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true,  EvenDblSpc, 2, 2,true},
298 
299 { ARM::VST2d16Pseudo,       ARM::VST2d16,      false, false, false, SingleSpc,  2, 4 ,true},
300 { ARM::VST2d16Pseudo_UPD,   ARM::VST2d16_UPD, false, true, true,  SingleSpc,  2, 4 ,true},
301 { ARM::VST2d32Pseudo,       ARM::VST2d32,      false, false, false, SingleSpc,  2, 2 ,true},
302 { ARM::VST2d32Pseudo_UPD,   ARM::VST2d32_UPD, false, true, true,  SingleSpc,  2, 2 ,true},
303 { ARM::VST2d8Pseudo,        ARM::VST2d8,       false, false, false, SingleSpc,  2, 8 ,true},
304 { ARM::VST2d8Pseudo_UPD,    ARM::VST2d8_UPD, false, true, true,  SingleSpc,  2, 8 ,true},
305 
306 { ARM::VST2q16Pseudo,       ARM::VST2q16,      false, false, false, SingleSpc,  4, 4 ,true},
307 { ARM::VST2q16Pseudo_UPD,   ARM::VST2q16_UPD, false, true, true,  SingleSpc,  4, 4 ,true},
308 { ARM::VST2q32Pseudo,       ARM::VST2q32,      false, false, false, SingleSpc,  4, 2 ,true},
309 { ARM::VST2q32Pseudo_UPD,   ARM::VST2q32_UPD, false, true, true,  SingleSpc,  4, 2 ,true},
310 { ARM::VST2q8Pseudo,        ARM::VST2q8,       false, false, false, SingleSpc,  4, 8 ,true},
311 { ARM::VST2q8Pseudo_UPD,    ARM::VST2q8_UPD, false, true, true,  SingleSpc,  4, 8 ,true},
312 
313 { ARM::VST3LNd16Pseudo,     ARM::VST3LNd16,     false, false, false, SingleSpc, 3, 4 ,true},
314 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true,  SingleSpc, 3, 4 ,true},
315 { ARM::VST3LNd32Pseudo,     ARM::VST3LNd32,     false, false, false, SingleSpc, 3, 2 ,true},
316 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true,  SingleSpc, 3, 2 ,true},
317 { ARM::VST3LNd8Pseudo,      ARM::VST3LNd8,      false, false, false, SingleSpc, 3, 8 ,true},
318 { ARM::VST3LNd8Pseudo_UPD,  ARM::VST3LNd8_UPD, false, true, true,  SingleSpc, 3, 8 ,true},
319 { ARM::VST3LNq16Pseudo,     ARM::VST3LNq16,     false, false, false, EvenDblSpc, 3, 4,true},
320 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true,  EvenDblSpc, 3, 4,true},
321 { ARM::VST3LNq32Pseudo,     ARM::VST3LNq32,     false, false, false, EvenDblSpc, 3, 2,true},
322 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true,  EvenDblSpc, 3, 2,true},
323 
324 { ARM::VST3d16Pseudo,       ARM::VST3d16,      false, false, false, SingleSpc,  3, 4 ,true},
325 { ARM::VST3d16Pseudo_UPD,   ARM::VST3d16_UPD, false, true, true,  SingleSpc,  3, 4 ,true},
326 { ARM::VST3d32Pseudo,       ARM::VST3d32,      false, false, false, SingleSpc,  3, 2 ,true},
327 { ARM::VST3d32Pseudo_UPD,   ARM::VST3d32_UPD, false, true, true,  SingleSpc,  3, 2 ,true},
328 { ARM::VST3d8Pseudo,        ARM::VST3d8,       false, false, false, SingleSpc,  3, 8 ,true},
329 { ARM::VST3d8Pseudo_UPD,    ARM::VST3d8_UPD, false, true, true,  SingleSpc,  3, 8 ,true},
330 
331 { ARM::VST3q16Pseudo_UPD,    ARM::VST3q16_UPD, false, true, true,  EvenDblSpc, 3, 4 ,true},
332 { ARM::VST3q16oddPseudo,     ARM::VST3q16,     false, false, false, OddDblSpc,  3, 4 ,true},
333 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true,  OddDblSpc,  3, 4 ,true},
334 { ARM::VST3q32Pseudo_UPD,    ARM::VST3q32_UPD, false, true, true,  EvenDblSpc, 3, 2 ,true},
335 { ARM::VST3q32oddPseudo,     ARM::VST3q32,     false, false, false, OddDblSpc,  3, 2 ,true},
336 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true,  OddDblSpc,  3, 2 ,true},
337 { ARM::VST3q8Pseudo_UPD,     ARM::VST3q8_UPD, false, true, true,  EvenDblSpc, 3, 8 ,true},
338 { ARM::VST3q8oddPseudo,      ARM::VST3q8,      false, false, false, OddDblSpc,  3, 8 ,true},
339 { ARM::VST3q8oddPseudo_UPD,  ARM::VST3q8_UPD, false, true, true,  OddDblSpc,  3, 8 ,true},
340 
341 { ARM::VST4LNd16Pseudo,     ARM::VST4LNd16,     false, false, false, SingleSpc, 4, 4 ,true},
342 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true,  SingleSpc, 4, 4 ,true},
343 { ARM::VST4LNd32Pseudo,     ARM::VST4LNd32,     false, false, false, SingleSpc, 4, 2 ,true},
344 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true,  SingleSpc, 4, 2 ,true},
345 { ARM::VST4LNd8Pseudo,      ARM::VST4LNd8,      false, false, false, SingleSpc, 4, 8 ,true},
346 { ARM::VST4LNd8Pseudo_UPD,  ARM::VST4LNd8_UPD, false, true, true,  SingleSpc, 4, 8 ,true},
347 { ARM::VST4LNq16Pseudo,     ARM::VST4LNq16,     false, false, false, EvenDblSpc, 4, 4,true},
348 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true,  EvenDblSpc, 4, 4,true},
349 { ARM::VST4LNq32Pseudo,     ARM::VST4LNq32,     false, false, false, EvenDblSpc, 4, 2,true},
350 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true,  EvenDblSpc, 4, 2,true},
351 
352 { ARM::VST4d16Pseudo,       ARM::VST4d16,      false, false, false, SingleSpc,  4, 4 ,true},
353 { ARM::VST4d16Pseudo_UPD,   ARM::VST4d16_UPD, false, true, true,  SingleSpc,  4, 4 ,true},
354 { ARM::VST4d32Pseudo,       ARM::VST4d32,      false, false, false, SingleSpc,  4, 2 ,true},
355 { ARM::VST4d32Pseudo_UPD,   ARM::VST4d32_UPD, false, true, true,  SingleSpc,  4, 2 ,true},
356 { ARM::VST4d8Pseudo,        ARM::VST4d8,       false, false, false, SingleSpc,  4, 8 ,true},
357 { ARM::VST4d8Pseudo_UPD,    ARM::VST4d8_UPD, false, true, true,  SingleSpc,  4, 8 ,true},
358 
359 { ARM::VST4q16Pseudo_UPD,    ARM::VST4q16_UPD, false, true, true,  EvenDblSpc, 4, 4 ,true},
360 { ARM::VST4q16oddPseudo,     ARM::VST4q16,     false, false, false, OddDblSpc,  4, 4 ,true},
361 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true,  OddDblSpc,  4, 4 ,true},
362 { ARM::VST4q32Pseudo_UPD,    ARM::VST4q32_UPD, false, true, true,  EvenDblSpc, 4, 2 ,true},
363 { ARM::VST4q32oddPseudo,     ARM::VST4q32,     false, false, false, OddDblSpc,  4, 2 ,true},
364 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true,  OddDblSpc,  4, 2 ,true},
365 { ARM::VST4q8Pseudo_UPD,     ARM::VST4q8_UPD, false, true, true,  EvenDblSpc, 4, 8 ,true},
366 { ARM::VST4q8oddPseudo,      ARM::VST4q8,      false, false, false, OddDblSpc,  4, 8 ,true},
367 { ARM::VST4q8oddPseudo_UPD,  ARM::VST4q8_UPD, false, true, true,  OddDblSpc,  4, 8 ,true}
368 };
369 
370 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
371 /// load or store pseudo instruction.
372 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
373   unsigned NumEntries = array_lengthof(NEONLdStTable);
374 
375 #ifndef NDEBUG
376   // Make sure the table is sorted.
377   static bool TableChecked = false;
378   if (!TableChecked) {
379     for (unsigned i = 0; i != NumEntries-1; ++i)
380       assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
381              "NEONLdStTable is not sorted!");
382     TableChecked = true;
383   }
384 #endif
385 
386   const NEONLdStTableEntry *I =
387     std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
388   if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
389     return I;
390   return NULL;
391 }
392 
393 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
394 /// corresponding to the specified register spacing.  Not all of the results
395 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
396 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
397                         const TargetRegisterInfo *TRI, unsigned &D0,
398                         unsigned &D1, unsigned &D2, unsigned &D3) {
399   if (RegSpc == SingleSpc) {
400     D0 = TRI->getSubReg(Reg, ARM::dsub_0);
401     D1 = TRI->getSubReg(Reg, ARM::dsub_1);
402     D2 = TRI->getSubReg(Reg, ARM::dsub_2);
403     D3 = TRI->getSubReg(Reg, ARM::dsub_3);
404   } else if (RegSpc == EvenDblSpc) {
405     D0 = TRI->getSubReg(Reg, ARM::dsub_0);
406     D1 = TRI->getSubReg(Reg, ARM::dsub_2);
407     D2 = TRI->getSubReg(Reg, ARM::dsub_4);
408     D3 = TRI->getSubReg(Reg, ARM::dsub_6);
409   } else {
410     assert(RegSpc == OddDblSpc && "unknown register spacing");
411     D0 = TRI->getSubReg(Reg, ARM::dsub_1);
412     D1 = TRI->getSubReg(Reg, ARM::dsub_3);
413     D2 = TRI->getSubReg(Reg, ARM::dsub_5);
414     D3 = TRI->getSubReg(Reg, ARM::dsub_7);
415   }
416 }
417 
418 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
419 /// operands to real VLD instructions with D register operands.
420 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
421   MachineInstr &MI = *MBBI;
422   MachineBasicBlock &MBB = *MI.getParent();
423 
424   const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
425   assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
426   NEONRegSpacing RegSpc = TableEntry->RegSpacing;
427   unsigned NumRegs = TableEntry->NumRegs;
428 
429   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
430                                     TII->get(TableEntry->RealOpc));
431   unsigned OpIdx = 0;
432 
433   bool DstIsDead = MI.getOperand(OpIdx).isDead();
434   unsigned DstReg = MI.getOperand(OpIdx++).getReg();
435   unsigned D0, D1, D2, D3;
436   GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
437   MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
438   if (NumRegs > 1 && TableEntry->copyAllListRegs)
439     MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
440   if (NumRegs > 2 && TableEntry->copyAllListRegs)
441     MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
442   if (NumRegs > 3 && TableEntry->copyAllListRegs)
443     MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
444 
445   if (TableEntry->isUpdating)
446     MIB.addOperand(MI.getOperand(OpIdx++));
447 
448   // Copy the addrmode6 operands.
449   MIB.addOperand(MI.getOperand(OpIdx++));
450   MIB.addOperand(MI.getOperand(OpIdx++));
451   // Copy the am6offset operand.
452   if (TableEntry->hasWritebackOperand)
453     MIB.addOperand(MI.getOperand(OpIdx++));
454 
455   // For an instruction writing double-spaced subregs, the pseudo instruction
456   // has an extra operand that is a use of the super-register.  Record the
457   // operand index and skip over it.
458   unsigned SrcOpIdx = 0;
459   if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
460     SrcOpIdx = OpIdx++;
461 
462   // Copy the predicate operands.
463   MIB.addOperand(MI.getOperand(OpIdx++));
464   MIB.addOperand(MI.getOperand(OpIdx++));
465 
466   // Copy the super-register source operand used for double-spaced subregs over
467   // to the new instruction as an implicit operand.
468   if (SrcOpIdx != 0) {
469     MachineOperand MO = MI.getOperand(SrcOpIdx);
470     MO.setImplicit(true);
471     MIB.addOperand(MO);
472   }
473   // Add an implicit def for the super-register.
474   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
475   TransferImpOps(MI, MIB, MIB);
476 
477   // Transfer memoperands.
478   MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
479 
480   MI.eraseFromParent();
481 }
482 
483 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
484 /// operands to real VST instructions with D register operands.
485 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
486   MachineInstr &MI = *MBBI;
487   MachineBasicBlock &MBB = *MI.getParent();
488 
489   const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
490   assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
491   NEONRegSpacing RegSpc = TableEntry->RegSpacing;
492   unsigned NumRegs = TableEntry->NumRegs;
493 
494   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
495                                     TII->get(TableEntry->RealOpc));
496   unsigned OpIdx = 0;
497   if (TableEntry->isUpdating)
498     MIB.addOperand(MI.getOperand(OpIdx++));
499 
500   // Copy the addrmode6 operands.
501   MIB.addOperand(MI.getOperand(OpIdx++));
502   MIB.addOperand(MI.getOperand(OpIdx++));
503   // Copy the am6offset operand.
504   if (TableEntry->hasWritebackOperand)
505     MIB.addOperand(MI.getOperand(OpIdx++));
506 
507   bool SrcIsKill = MI.getOperand(OpIdx).isKill();
508   unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
509   unsigned D0, D1, D2, D3;
510   GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
511   MIB.addReg(D0);
512   if (NumRegs > 1 && TableEntry->copyAllListRegs)
513     MIB.addReg(D1);
514   if (NumRegs > 2 && TableEntry->copyAllListRegs)
515     MIB.addReg(D2);
516   if (NumRegs > 3 && TableEntry->copyAllListRegs)
517     MIB.addReg(D3);
518 
519   // Copy the predicate operands.
520   MIB.addOperand(MI.getOperand(OpIdx++));
521   MIB.addOperand(MI.getOperand(OpIdx++));
522 
523   if (SrcIsKill) // Add an implicit kill for the super-reg.
524     MIB->addRegisterKilled(SrcReg, TRI, true);
525   TransferImpOps(MI, MIB, MIB);
526 
527   // Transfer memoperands.
528   MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
529 
530   MI.eraseFromParent();
531 }
532 
533 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
534 /// register operands to real instructions with D register operands.
535 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
536   MachineInstr &MI = *MBBI;
537   MachineBasicBlock &MBB = *MI.getParent();
538 
539   const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
540   assert(TableEntry && "NEONLdStTable lookup failed");
541   NEONRegSpacing RegSpc = TableEntry->RegSpacing;
542   unsigned NumRegs = TableEntry->NumRegs;
543   unsigned RegElts = TableEntry->RegElts;
544 
545   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
546                                     TII->get(TableEntry->RealOpc));
547   unsigned OpIdx = 0;
548   // The lane operand is always the 3rd from last operand, before the 2
549   // predicate operands.
550   unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
551 
552   // Adjust the lane and spacing as needed for Q registers.
553   assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
554   if (RegSpc == EvenDblSpc && Lane >= RegElts) {
555     RegSpc = OddDblSpc;
556     Lane -= RegElts;
557   }
558   assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
559 
560   unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
561   unsigned DstReg = 0;
562   bool DstIsDead = false;
563   if (TableEntry->IsLoad) {
564     DstIsDead = MI.getOperand(OpIdx).isDead();
565     DstReg = MI.getOperand(OpIdx++).getReg();
566     GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
567     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
568     if (NumRegs > 1)
569       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
570     if (NumRegs > 2)
571       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
572     if (NumRegs > 3)
573       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
574   }
575 
576   if (TableEntry->isUpdating)
577     MIB.addOperand(MI.getOperand(OpIdx++));
578 
579   // Copy the addrmode6 operands.
580   MIB.addOperand(MI.getOperand(OpIdx++));
581   MIB.addOperand(MI.getOperand(OpIdx++));
582   // Copy the am6offset operand.
583   if (TableEntry->hasWritebackOperand)
584     MIB.addOperand(MI.getOperand(OpIdx++));
585 
586   // Grab the super-register source.
587   MachineOperand MO = MI.getOperand(OpIdx++);
588   if (!TableEntry->IsLoad)
589     GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
590 
591   // Add the subregs as sources of the new instruction.
592   unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
593                        getKillRegState(MO.isKill()));
594   MIB.addReg(D0, SrcFlags);
595   if (NumRegs > 1)
596     MIB.addReg(D1, SrcFlags);
597   if (NumRegs > 2)
598     MIB.addReg(D2, SrcFlags);
599   if (NumRegs > 3)
600     MIB.addReg(D3, SrcFlags);
601 
602   // Add the lane number operand.
603   MIB.addImm(Lane);
604   OpIdx += 1;
605 
606   // Copy the predicate operands.
607   MIB.addOperand(MI.getOperand(OpIdx++));
608   MIB.addOperand(MI.getOperand(OpIdx++));
609 
610   // Copy the super-register source to be an implicit source.
611   MO.setImplicit(true);
612   MIB.addOperand(MO);
613   if (TableEntry->IsLoad)
614     // Add an implicit def for the super-register.
615     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
616   TransferImpOps(MI, MIB, MIB);
617   MI.eraseFromParent();
618 }
619 
620 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
621 /// register operands to real instructions with D register operands.
622 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
623                                  unsigned Opc, bool IsExt, unsigned NumRegs) {
624   MachineInstr &MI = *MBBI;
625   MachineBasicBlock &MBB = *MI.getParent();
626 
627   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
628   unsigned OpIdx = 0;
629 
630   // Transfer the destination register operand.
631   MIB.addOperand(MI.getOperand(OpIdx++));
632   if (IsExt)
633     MIB.addOperand(MI.getOperand(OpIdx++));
634 
635   bool SrcIsKill = MI.getOperand(OpIdx).isKill();
636   unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
637   unsigned D0, D1, D2, D3;
638   GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
639   MIB.addReg(D0).addReg(D1);
640   if (NumRegs > 2)
641     MIB.addReg(D2);
642   if (NumRegs > 3)
643     MIB.addReg(D3);
644 
645   // Copy the other source register operand.
646   MIB.addOperand(MI.getOperand(OpIdx++));
647 
648   // Copy the predicate operands.
649   MIB.addOperand(MI.getOperand(OpIdx++));
650   MIB.addOperand(MI.getOperand(OpIdx++));
651 
652   if (SrcIsKill)  // Add an implicit kill for the super-reg.
653     MIB->addRegisterKilled(SrcReg, TRI, true);
654   TransferImpOps(MI, MIB, MIB);
655   MI.eraseFromParent();
656 }
657 
658 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
659                                         MachineBasicBlock::iterator &MBBI) {
660   MachineInstr &MI = *MBBI;
661   unsigned Opcode = MI.getOpcode();
662   unsigned PredReg = 0;
663   ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
664   unsigned DstReg = MI.getOperand(0).getReg();
665   bool DstIsDead = MI.getOperand(0).isDead();
666   bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
667   const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
668   MachineInstrBuilder LO16, HI16;
669 
670   if (!STI->hasV6T2Ops() &&
671       (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
672     // Expand into a movi + orr.
673     LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
674     HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
675       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
676       .addReg(DstReg);
677 
678     assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
679     unsigned ImmVal = (unsigned)MO.getImm();
680     unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
681     unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
682     LO16 = LO16.addImm(SOImmValV1);
683     HI16 = HI16.addImm(SOImmValV2);
684     LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
685     HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
686     LO16.addImm(Pred).addReg(PredReg).addReg(0);
687     HI16.addImm(Pred).addReg(PredReg).addReg(0);
688     TransferImpOps(MI, LO16, HI16);
689     MI.eraseFromParent();
690     return;
691   }
692 
693   unsigned LO16Opc = 0;
694   unsigned HI16Opc = 0;
695   if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
696     LO16Opc = ARM::t2MOVi16;
697     HI16Opc = ARM::t2MOVTi16;
698   } else {
699     LO16Opc = ARM::MOVi16;
700     HI16Opc = ARM::MOVTi16;
701   }
702 
703   LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
704   HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
705     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
706     .addReg(DstReg);
707 
708   if (MO.isImm()) {
709     unsigned Imm = MO.getImm();
710     unsigned Lo16 = Imm & 0xffff;
711     unsigned Hi16 = (Imm >> 16) & 0xffff;
712     LO16 = LO16.addImm(Lo16);
713     HI16 = HI16.addImm(Hi16);
714   } else {
715     const GlobalValue *GV = MO.getGlobal();
716     unsigned TF = MO.getTargetFlags();
717     LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
718     HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
719   }
720 
721   LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
722   HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
723   LO16.addImm(Pred).addReg(PredReg);
724   HI16.addImm(Pred).addReg(PredReg);
725 
726   TransferImpOps(MI, LO16, HI16);
727   MI.eraseFromParent();
728 }
729 
730 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
731                                MachineBasicBlock::iterator MBBI) {
732   MachineInstr &MI = *MBBI;
733   unsigned Opcode = MI.getOpcode();
734   switch (Opcode) {
735     default:
736       return false;
737     case ARM::VMOVScc:
738     case ARM::VMOVDcc: {
739       unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
740       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
741               MI.getOperand(1).getReg())
742         .addReg(MI.getOperand(2).getReg(),
743                 getKillRegState(MI.getOperand(2).isKill()))
744         .addImm(MI.getOperand(3).getImm()) // 'pred'
745         .addReg(MI.getOperand(4).getReg());
746 
747       MI.eraseFromParent();
748       return true;
749     }
750     case ARM::t2MOVCCr:
751     case ARM::MOVCCr: {
752       unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
753       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
754               MI.getOperand(1).getReg())
755         .addReg(MI.getOperand(2).getReg(),
756                 getKillRegState(MI.getOperand(2).isKill()))
757         .addImm(MI.getOperand(3).getImm()) // 'pred'
758         .addReg(MI.getOperand(4).getReg())
759         .addReg(0); // 's' bit
760 
761       MI.eraseFromParent();
762       return true;
763     }
764     case ARM::MOVCCsi: {
765       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
766               (MI.getOperand(1).getReg()))
767         .addReg(MI.getOperand(2).getReg(),
768                 getKillRegState(MI.getOperand(2).isKill()))
769         .addImm(MI.getOperand(3).getImm())
770         .addImm(MI.getOperand(4).getImm()) // 'pred'
771         .addReg(MI.getOperand(5).getReg())
772         .addReg(0); // 's' bit
773 
774       MI.eraseFromParent();
775       return true;
776     }
777 
778     case ARM::MOVCCsr: {
779       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
780               (MI.getOperand(1).getReg()))
781         .addReg(MI.getOperand(2).getReg(),
782                 getKillRegState(MI.getOperand(2).isKill()))
783         .addReg(MI.getOperand(3).getReg(),
784                 getKillRegState(MI.getOperand(3).isKill()))
785         .addImm(MI.getOperand(4).getImm())
786         .addImm(MI.getOperand(5).getImm()) // 'pred'
787         .addReg(MI.getOperand(6).getReg())
788         .addReg(0); // 's' bit
789 
790       MI.eraseFromParent();
791       return true;
792     }
793     case ARM::MOVCCi16: {
794       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi16),
795               MI.getOperand(1).getReg())
796         .addImm(MI.getOperand(2).getImm())
797         .addImm(MI.getOperand(3).getImm()) // 'pred'
798         .addReg(MI.getOperand(4).getReg());
799 
800       MI.eraseFromParent();
801       return true;
802     }
803     case ARM::t2MOVCCi:
804     case ARM::MOVCCi: {
805       unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
806       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
807               MI.getOperand(1).getReg())
808         .addImm(MI.getOperand(2).getImm())
809         .addImm(MI.getOperand(3).getImm()) // 'pred'
810         .addReg(MI.getOperand(4).getReg())
811         .addReg(0); // 's' bit
812 
813       MI.eraseFromParent();
814       return true;
815     }
816     case ARM::MVNCCi: {
817       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi),
818               MI.getOperand(1).getReg())
819         .addImm(MI.getOperand(2).getImm())
820         .addImm(MI.getOperand(3).getImm()) // 'pred'
821         .addReg(MI.getOperand(4).getReg())
822         .addReg(0); // 's' bit
823 
824       MI.eraseFromParent();
825       return true;
826     }
827     case ARM::eh_sjlj_dispatchsetup: {
828       MachineFunction &MF = *MI.getParent()->getParent();
829       const ARMBaseInstrInfo *AII =
830         static_cast<const ARMBaseInstrInfo*>(TII);
831       const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
832       // For functions using a base pointer, we rematerialize it (via the frame
833       // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
834       // for us. Otherwise, expand to nothing.
835       if (RI.hasBasePointer(MF)) {
836         int32_t NumBytes = AFI->getFramePtrSpillOffset();
837         unsigned FramePtr = RI.getFrameRegister(MF);
838         assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
839                "base pointer without frame pointer?");
840 
841         if (AFI->isThumb2Function()) {
842           llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
843                                        FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
844         } else if (AFI->isThumbFunction()) {
845           llvm::emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
846                                           FramePtr, -NumBytes, *TII, RI);
847         } else {
848           llvm::emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
849                                         FramePtr, -NumBytes, ARMCC::AL, 0,
850                                         *TII);
851         }
852         // If there's dynamic realignment, adjust for it.
853         if (RI.needsStackRealignment(MF)) {
854           MachineFrameInfo  *MFI = MF.getFrameInfo();
855           unsigned MaxAlign = MFI->getMaxAlignment();
856           assert (!AFI->isThumb1OnlyFunction());
857           // Emit bic r6, r6, MaxAlign
858           unsigned bicOpc = AFI->isThumbFunction() ?
859             ARM::t2BICri : ARM::BICri;
860           AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
861                                               TII->get(bicOpc), ARM::R6)
862                                       .addReg(ARM::R6, RegState::Kill)
863                                       .addImm(MaxAlign-1)));
864         }
865 
866       }
867       MI.eraseFromParent();
868       return true;
869     }
870 
871     case ARM::MOVsrl_flag:
872     case ARM::MOVsra_flag: {
873       // These are just fancy MOVs insructions.
874       AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
875                              MI.getOperand(0).getReg())
876                      .addOperand(MI.getOperand(1))
877                      .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ?
878                                                   ARM_AM::lsr : ARM_AM::asr),
879                                                  1)))
880         .addReg(ARM::CPSR, RegState::Define);
881       MI.eraseFromParent();
882       return true;
883     }
884     case ARM::RRX: {
885       // This encodes as "MOVs Rd, Rm, rrx
886       MachineInstrBuilder MIB =
887         AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
888                                MI.getOperand(0).getReg())
889                        .addOperand(MI.getOperand(1))
890                        .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
891         .addReg(0);
892       TransferImpOps(MI, MIB, MIB);
893       MI.eraseFromParent();
894       return true;
895     }
896     case ARM::tTPsoft:
897     case ARM::TPsoft: {
898       MachineInstrBuilder MIB =
899         BuildMI(MBB, MBBI, MI.getDebugLoc(),
900                 TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
901         .addExternalSymbol("__aeabi_read_tp", 0);
902 
903       MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
904       TransferImpOps(MI, MIB, MIB);
905       MI.eraseFromParent();
906       return true;
907     }
908     case ARM::tLDRpci_pic:
909     case ARM::t2LDRpci_pic: {
910       unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
911         ? ARM::tLDRpci : ARM::t2LDRpci;
912       unsigned DstReg = MI.getOperand(0).getReg();
913       bool DstIsDead = MI.getOperand(0).isDead();
914       MachineInstrBuilder MIB1 =
915         AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
916                                TII->get(NewLdOpc), DstReg)
917                        .addOperand(MI.getOperand(1)));
918       MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
919       MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
920                                          TII->get(ARM::tPICADD))
921         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
922         .addReg(DstReg)
923         .addOperand(MI.getOperand(2));
924       TransferImpOps(MI, MIB1, MIB2);
925       MI.eraseFromParent();
926       return true;
927     }
928 
929     case ARM::MOV_ga_dyn:
930     case ARM::MOV_ga_pcrel:
931     case ARM::MOV_ga_pcrel_ldr:
932     case ARM::t2MOV_ga_dyn:
933     case ARM::t2MOV_ga_pcrel: {
934       // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
935       unsigned LabelId = AFI->createPICLabelUId();
936       unsigned DstReg = MI.getOperand(0).getReg();
937       bool DstIsDead = MI.getOperand(0).isDead();
938       const MachineOperand &MO1 = MI.getOperand(1);
939       const GlobalValue *GV = MO1.getGlobal();
940       unsigned TF = MO1.getTargetFlags();
941       bool isARM = (Opcode != ARM::t2MOV_ga_pcrel && Opcode!=ARM::t2MOV_ga_dyn);
942       bool isPIC = (Opcode != ARM::MOV_ga_dyn && Opcode != ARM::t2MOV_ga_dyn);
943       unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
944       unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
945       unsigned LO16TF = isPIC
946         ? ARMII::MO_LO16_NONLAZY_PIC : ARMII::MO_LO16_NONLAZY;
947       unsigned HI16TF = isPIC
948         ? ARMII::MO_HI16_NONLAZY_PIC : ARMII::MO_HI16_NONLAZY;
949       unsigned PICAddOpc = isARM
950         ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
951         : ARM::tPICADD;
952       MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
953                                          TII->get(LO16Opc), DstReg)
954         .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
955         .addImm(LabelId);
956       MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
957                                          TII->get(HI16Opc), DstReg)
958         .addReg(DstReg)
959         .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
960         .addImm(LabelId);
961       if (!isPIC) {
962         TransferImpOps(MI, MIB1, MIB2);
963         MI.eraseFromParent();
964         return true;
965       }
966 
967       MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
968                                          TII->get(PICAddOpc))
969         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
970         .addReg(DstReg).addImm(LabelId);
971       if (isARM) {
972         AddDefaultPred(MIB3);
973         if (Opcode == ARM::MOV_ga_pcrel_ldr)
974           MIB2->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
975       }
976       TransferImpOps(MI, MIB1, MIB3);
977       MI.eraseFromParent();
978       return true;
979     }
980 
981     case ARM::MOVi32imm:
982     case ARM::MOVCCi32imm:
983     case ARM::t2MOVi32imm:
984     case ARM::t2MOVCCi32imm:
985       ExpandMOV32BitImm(MBB, MBBI);
986       return true;
987 
988     case ARM::VLDMQIA: {
989       unsigned NewOpc = ARM::VLDMDIA;
990       MachineInstrBuilder MIB =
991         BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
992       unsigned OpIdx = 0;
993 
994       // Grab the Q register destination.
995       bool DstIsDead = MI.getOperand(OpIdx).isDead();
996       unsigned DstReg = MI.getOperand(OpIdx++).getReg();
997 
998       // Copy the source register.
999       MIB.addOperand(MI.getOperand(OpIdx++));
1000 
1001       // Copy the predicate operands.
1002       MIB.addOperand(MI.getOperand(OpIdx++));
1003       MIB.addOperand(MI.getOperand(OpIdx++));
1004 
1005       // Add the destination operands (D subregs).
1006       unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1007       unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1008       MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1009         .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1010 
1011       // Add an implicit def for the super-register.
1012       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1013       TransferImpOps(MI, MIB, MIB);
1014       MI.eraseFromParent();
1015       return true;
1016     }
1017 
1018     case ARM::VSTMQIA: {
1019       unsigned NewOpc = ARM::VSTMDIA;
1020       MachineInstrBuilder MIB =
1021         BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1022       unsigned OpIdx = 0;
1023 
1024       // Grab the Q register source.
1025       bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1026       unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1027 
1028       // Copy the destination register.
1029       MIB.addOperand(MI.getOperand(OpIdx++));
1030 
1031       // Copy the predicate operands.
1032       MIB.addOperand(MI.getOperand(OpIdx++));
1033       MIB.addOperand(MI.getOperand(OpIdx++));
1034 
1035       // Add the source operands (D subregs).
1036       unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1037       unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1038       MIB.addReg(D0).addReg(D1);
1039 
1040       if (SrcIsKill)      // Add an implicit kill for the Q register.
1041         MIB->addRegisterKilled(SrcReg, TRI, true);
1042 
1043       TransferImpOps(MI, MIB, MIB);
1044       MI.eraseFromParent();
1045       return true;
1046     }
1047     case ARM::VDUPfqf:
1048     case ARM::VDUPfdf:{
1049       unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q :
1050         ARM::VDUPLN32d;
1051       MachineInstrBuilder MIB =
1052         BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1053       unsigned OpIdx = 0;
1054       unsigned SrcReg = MI.getOperand(1).getReg();
1055       unsigned Lane = getARMRegisterNumbering(SrcReg) & 1;
1056       unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
1057                             Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
1058                             &ARM::DPR_VFP2RegClass);
1059       // The lane is [0,1] for the containing DReg superregister.
1060       // Copy the dst/src register operands.
1061       MIB.addOperand(MI.getOperand(OpIdx++));
1062       MIB.addReg(DReg);
1063       ++OpIdx;
1064       // Add the lane select operand.
1065       MIB.addImm(Lane);
1066       // Add the predicate operands.
1067       MIB.addOperand(MI.getOperand(OpIdx++));
1068       MIB.addOperand(MI.getOperand(OpIdx++));
1069 
1070       TransferImpOps(MI, MIB, MIB);
1071       MI.eraseFromParent();
1072       return true;
1073     }
1074 
1075     case ARM::VLD1q8Pseudo:
1076     case ARM::VLD1q16Pseudo:
1077     case ARM::VLD1q32Pseudo:
1078     case ARM::VLD1q64Pseudo:
1079     case ARM::VLD1q8PseudoWB_register:
1080     case ARM::VLD1q16PseudoWB_register:
1081     case ARM::VLD1q32PseudoWB_register:
1082     case ARM::VLD1q64PseudoWB_register:
1083     case ARM::VLD1q8PseudoWB_fixed:
1084     case ARM::VLD1q16PseudoWB_fixed:
1085     case ARM::VLD1q32PseudoWB_fixed:
1086     case ARM::VLD1q64PseudoWB_fixed:
1087     case ARM::VLD2d8Pseudo:
1088     case ARM::VLD2d16Pseudo:
1089     case ARM::VLD2d32Pseudo:
1090     case ARM::VLD2q8Pseudo:
1091     case ARM::VLD2q16Pseudo:
1092     case ARM::VLD2q32Pseudo:
1093     case ARM::VLD2d8Pseudo_UPD:
1094     case ARM::VLD2d16Pseudo_UPD:
1095     case ARM::VLD2d32Pseudo_UPD:
1096     case ARM::VLD2q8Pseudo_UPD:
1097     case ARM::VLD2q16Pseudo_UPD:
1098     case ARM::VLD2q32Pseudo_UPD:
1099     case ARM::VLD3d8Pseudo:
1100     case ARM::VLD3d16Pseudo:
1101     case ARM::VLD3d32Pseudo:
1102     case ARM::VLD1d64TPseudo:
1103     case ARM::VLD3d8Pseudo_UPD:
1104     case ARM::VLD3d16Pseudo_UPD:
1105     case ARM::VLD3d32Pseudo_UPD:
1106     case ARM::VLD3q8Pseudo_UPD:
1107     case ARM::VLD3q16Pseudo_UPD:
1108     case ARM::VLD3q32Pseudo_UPD:
1109     case ARM::VLD3q8oddPseudo:
1110     case ARM::VLD3q16oddPseudo:
1111     case ARM::VLD3q32oddPseudo:
1112     case ARM::VLD3q8oddPseudo_UPD:
1113     case ARM::VLD3q16oddPseudo_UPD:
1114     case ARM::VLD3q32oddPseudo_UPD:
1115     case ARM::VLD4d8Pseudo:
1116     case ARM::VLD4d16Pseudo:
1117     case ARM::VLD4d32Pseudo:
1118     case ARM::VLD1d64QPseudo:
1119     case ARM::VLD4d8Pseudo_UPD:
1120     case ARM::VLD4d16Pseudo_UPD:
1121     case ARM::VLD4d32Pseudo_UPD:
1122     case ARM::VLD4q8Pseudo_UPD:
1123     case ARM::VLD4q16Pseudo_UPD:
1124     case ARM::VLD4q32Pseudo_UPD:
1125     case ARM::VLD4q8oddPseudo:
1126     case ARM::VLD4q16oddPseudo:
1127     case ARM::VLD4q32oddPseudo:
1128     case ARM::VLD4q8oddPseudo_UPD:
1129     case ARM::VLD4q16oddPseudo_UPD:
1130     case ARM::VLD4q32oddPseudo_UPD:
1131     case ARM::VLD1DUPq8Pseudo:
1132     case ARM::VLD1DUPq16Pseudo:
1133     case ARM::VLD1DUPq32Pseudo:
1134     case ARM::VLD1DUPq8Pseudo_UPD:
1135     case ARM::VLD1DUPq16Pseudo_UPD:
1136     case ARM::VLD1DUPq32Pseudo_UPD:
1137     case ARM::VLD2DUPd8Pseudo:
1138     case ARM::VLD2DUPd16Pseudo:
1139     case ARM::VLD2DUPd32Pseudo:
1140     case ARM::VLD2DUPd8Pseudo_UPD:
1141     case ARM::VLD2DUPd16Pseudo_UPD:
1142     case ARM::VLD2DUPd32Pseudo_UPD:
1143     case ARM::VLD3DUPd8Pseudo:
1144     case ARM::VLD3DUPd16Pseudo:
1145     case ARM::VLD3DUPd32Pseudo:
1146     case ARM::VLD3DUPd8Pseudo_UPD:
1147     case ARM::VLD3DUPd16Pseudo_UPD:
1148     case ARM::VLD3DUPd32Pseudo_UPD:
1149     case ARM::VLD4DUPd8Pseudo:
1150     case ARM::VLD4DUPd16Pseudo:
1151     case ARM::VLD4DUPd32Pseudo:
1152     case ARM::VLD4DUPd8Pseudo_UPD:
1153     case ARM::VLD4DUPd16Pseudo_UPD:
1154     case ARM::VLD4DUPd32Pseudo_UPD:
1155       ExpandVLD(MBBI);
1156       return true;
1157 
1158     case ARM::VST1q8Pseudo:
1159     case ARM::VST1q16Pseudo:
1160     case ARM::VST1q32Pseudo:
1161     case ARM::VST1q64Pseudo:
1162     case ARM::VST1q8PseudoWB_fixed:
1163     case ARM::VST1q16PseudoWB_fixed:
1164     case ARM::VST1q32PseudoWB_fixed:
1165     case ARM::VST1q64PseudoWB_fixed:
1166     case ARM::VST1q8PseudoWB_register:
1167     case ARM::VST1q16PseudoWB_register:
1168     case ARM::VST1q32PseudoWB_register:
1169     case ARM::VST1q64PseudoWB_register:
1170     case ARM::VST2d8Pseudo:
1171     case ARM::VST2d16Pseudo:
1172     case ARM::VST2d32Pseudo:
1173     case ARM::VST2q8Pseudo:
1174     case ARM::VST2q16Pseudo:
1175     case ARM::VST2q32Pseudo:
1176     case ARM::VST2d8Pseudo_UPD:
1177     case ARM::VST2d16Pseudo_UPD:
1178     case ARM::VST2d32Pseudo_UPD:
1179     case ARM::VST2q8Pseudo_UPD:
1180     case ARM::VST2q16Pseudo_UPD:
1181     case ARM::VST2q32Pseudo_UPD:
1182     case ARM::VST3d8Pseudo:
1183     case ARM::VST3d16Pseudo:
1184     case ARM::VST3d32Pseudo:
1185     case ARM::VST1d64TPseudo:
1186     case ARM::VST3d8Pseudo_UPD:
1187     case ARM::VST3d16Pseudo_UPD:
1188     case ARM::VST3d32Pseudo_UPD:
1189     case ARM::VST1d64TPseudo_UPD:
1190     case ARM::VST3q8Pseudo_UPD:
1191     case ARM::VST3q16Pseudo_UPD:
1192     case ARM::VST3q32Pseudo_UPD:
1193     case ARM::VST3q8oddPseudo:
1194     case ARM::VST3q16oddPseudo:
1195     case ARM::VST3q32oddPseudo:
1196     case ARM::VST3q8oddPseudo_UPD:
1197     case ARM::VST3q16oddPseudo_UPD:
1198     case ARM::VST3q32oddPseudo_UPD:
1199     case ARM::VST4d8Pseudo:
1200     case ARM::VST4d16Pseudo:
1201     case ARM::VST4d32Pseudo:
1202     case ARM::VST1d64QPseudo:
1203     case ARM::VST4d8Pseudo_UPD:
1204     case ARM::VST4d16Pseudo_UPD:
1205     case ARM::VST4d32Pseudo_UPD:
1206     case ARM::VST1d64QPseudo_UPD:
1207     case ARM::VST4q8Pseudo_UPD:
1208     case ARM::VST4q16Pseudo_UPD:
1209     case ARM::VST4q32Pseudo_UPD:
1210     case ARM::VST4q8oddPseudo:
1211     case ARM::VST4q16oddPseudo:
1212     case ARM::VST4q32oddPseudo:
1213     case ARM::VST4q8oddPseudo_UPD:
1214     case ARM::VST4q16oddPseudo_UPD:
1215     case ARM::VST4q32oddPseudo_UPD:
1216       ExpandVST(MBBI);
1217       return true;
1218 
1219     case ARM::VLD1LNq8Pseudo:
1220     case ARM::VLD1LNq16Pseudo:
1221     case ARM::VLD1LNq32Pseudo:
1222     case ARM::VLD1LNq8Pseudo_UPD:
1223     case ARM::VLD1LNq16Pseudo_UPD:
1224     case ARM::VLD1LNq32Pseudo_UPD:
1225     case ARM::VLD2LNd8Pseudo:
1226     case ARM::VLD2LNd16Pseudo:
1227     case ARM::VLD2LNd32Pseudo:
1228     case ARM::VLD2LNq16Pseudo:
1229     case ARM::VLD2LNq32Pseudo:
1230     case ARM::VLD2LNd8Pseudo_UPD:
1231     case ARM::VLD2LNd16Pseudo_UPD:
1232     case ARM::VLD2LNd32Pseudo_UPD:
1233     case ARM::VLD2LNq16Pseudo_UPD:
1234     case ARM::VLD2LNq32Pseudo_UPD:
1235     case ARM::VLD3LNd8Pseudo:
1236     case ARM::VLD3LNd16Pseudo:
1237     case ARM::VLD3LNd32Pseudo:
1238     case ARM::VLD3LNq16Pseudo:
1239     case ARM::VLD3LNq32Pseudo:
1240     case ARM::VLD3LNd8Pseudo_UPD:
1241     case ARM::VLD3LNd16Pseudo_UPD:
1242     case ARM::VLD3LNd32Pseudo_UPD:
1243     case ARM::VLD3LNq16Pseudo_UPD:
1244     case ARM::VLD3LNq32Pseudo_UPD:
1245     case ARM::VLD4LNd8Pseudo:
1246     case ARM::VLD4LNd16Pseudo:
1247     case ARM::VLD4LNd32Pseudo:
1248     case ARM::VLD4LNq16Pseudo:
1249     case ARM::VLD4LNq32Pseudo:
1250     case ARM::VLD4LNd8Pseudo_UPD:
1251     case ARM::VLD4LNd16Pseudo_UPD:
1252     case ARM::VLD4LNd32Pseudo_UPD:
1253     case ARM::VLD4LNq16Pseudo_UPD:
1254     case ARM::VLD4LNq32Pseudo_UPD:
1255     case ARM::VST1LNq8Pseudo:
1256     case ARM::VST1LNq16Pseudo:
1257     case ARM::VST1LNq32Pseudo:
1258     case ARM::VST1LNq8Pseudo_UPD:
1259     case ARM::VST1LNq16Pseudo_UPD:
1260     case ARM::VST1LNq32Pseudo_UPD:
1261     case ARM::VST2LNd8Pseudo:
1262     case ARM::VST2LNd16Pseudo:
1263     case ARM::VST2LNd32Pseudo:
1264     case ARM::VST2LNq16Pseudo:
1265     case ARM::VST2LNq32Pseudo:
1266     case ARM::VST2LNd8Pseudo_UPD:
1267     case ARM::VST2LNd16Pseudo_UPD:
1268     case ARM::VST2LNd32Pseudo_UPD:
1269     case ARM::VST2LNq16Pseudo_UPD:
1270     case ARM::VST2LNq32Pseudo_UPD:
1271     case ARM::VST3LNd8Pseudo:
1272     case ARM::VST3LNd16Pseudo:
1273     case ARM::VST3LNd32Pseudo:
1274     case ARM::VST3LNq16Pseudo:
1275     case ARM::VST3LNq32Pseudo:
1276     case ARM::VST3LNd8Pseudo_UPD:
1277     case ARM::VST3LNd16Pseudo_UPD:
1278     case ARM::VST3LNd32Pseudo_UPD:
1279     case ARM::VST3LNq16Pseudo_UPD:
1280     case ARM::VST3LNq32Pseudo_UPD:
1281     case ARM::VST4LNd8Pseudo:
1282     case ARM::VST4LNd16Pseudo:
1283     case ARM::VST4LNd32Pseudo:
1284     case ARM::VST4LNq16Pseudo:
1285     case ARM::VST4LNq32Pseudo:
1286     case ARM::VST4LNd8Pseudo_UPD:
1287     case ARM::VST4LNd16Pseudo_UPD:
1288     case ARM::VST4LNd32Pseudo_UPD:
1289     case ARM::VST4LNq16Pseudo_UPD:
1290     case ARM::VST4LNq32Pseudo_UPD:
1291       ExpandLaneOp(MBBI);
1292       return true;
1293 
1294     case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false, 2); return true;
1295     case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false, 3); return true;
1296     case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false, 4); return true;
1297     case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true, 2); return true;
1298     case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true, 3); return true;
1299     case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true, 4); return true;
1300   }
1301 
1302   return false;
1303 }
1304 
1305 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1306   bool Modified = false;
1307 
1308   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1309   while (MBBI != E) {
1310     MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
1311     Modified |= ExpandMI(MBB, MBBI);
1312     MBBI = NMBBI;
1313   }
1314 
1315   return Modified;
1316 }
1317 
1318 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1319   const TargetMachine &TM = MF.getTarget();
1320   TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
1321   TRI = TM.getRegisterInfo();
1322   STI = &TM.getSubtarget<ARMSubtarget>();
1323   AFI = MF.getInfo<ARMFunctionInfo>();
1324 
1325   bool Modified = false;
1326   for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1327        ++MFI)
1328     Modified |= ExpandMBB(*MFI);
1329   if (VerifyARMPseudo)
1330     MF.verify(this, "After expanding ARM pseudo instructions.");
1331   return Modified;
1332 }
1333 
1334 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1335 /// expansion pass.
1336 FunctionPass *llvm::createARMExpandPseudoPass() {
1337   return new ARMExpandPseudo();
1338 }
1339