1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "ARM.h"
18 #include "ARMBaseInstrInfo.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/CodeGen/LivePhysRegs.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineInstrBundle.h"
29 #include "llvm/IR/GlobalValue.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "arm-pseudo"
38 
39 static cl::opt<bool>
40 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
41                 cl::desc("Verify machine code after expanding ARM pseudos"));
42 
43 namespace {
44   class ARMExpandPseudo : public MachineFunctionPass {
45   public:
46     static char ID;
47     ARMExpandPseudo() : MachineFunctionPass(ID) {}
48 
49     const ARMBaseInstrInfo *TII;
50     const TargetRegisterInfo *TRI;
51     const ARMSubtarget *STI;
52     ARMFunctionInfo *AFI;
53 
54     bool runOnMachineFunction(MachineFunction &Fn) override;
55 
56     MachineFunctionProperties getRequiredProperties() const override {
57       return MachineFunctionProperties().set(
58           MachineFunctionProperties::Property::NoVRegs);
59     }
60 
61     StringRef getPassName() const override {
62       return "ARM pseudo instruction expansion pass";
63     }
64 
65   private:
66     void TransferImpOps(MachineInstr &OldMI,
67                         MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
68     bool ExpandMI(MachineBasicBlock &MBB,
69                   MachineBasicBlock::iterator MBBI,
70                   MachineBasicBlock::iterator &NextMBBI);
71     bool ExpandMBB(MachineBasicBlock &MBB);
72     void ExpandVLD(MachineBasicBlock::iterator &MBBI);
73     void ExpandVST(MachineBasicBlock::iterator &MBBI);
74     void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
75     void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
76                     unsigned Opc, bool IsExt);
77     void ExpandMOV32BitImm(MachineBasicBlock &MBB,
78                            MachineBasicBlock::iterator &MBBI);
79     bool ExpandCMP_SWAP(MachineBasicBlock &MBB,
80                         MachineBasicBlock::iterator MBBI, unsigned LdrexOp,
81                         unsigned StrexOp, unsigned UxtOp,
82                         MachineBasicBlock::iterator &NextMBBI);
83 
84     bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
85                            MachineBasicBlock::iterator MBBI,
86                            MachineBasicBlock::iterator &NextMBBI);
87   };
88   char ARMExpandPseudo::ID = 0;
89 }
90 
91 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
92 /// the instructions created from the expansion.
93 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
94                                      MachineInstrBuilder &UseMI,
95                                      MachineInstrBuilder &DefMI) {
96   const MCInstrDesc &Desc = OldMI.getDesc();
97   for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
98        i != e; ++i) {
99     const MachineOperand &MO = OldMI.getOperand(i);
100     assert(MO.isReg() && MO.getReg());
101     if (MO.isUse())
102       UseMI.add(MO);
103     else
104       DefMI.add(MO);
105   }
106 }
107 
108 namespace {
109   // Constants for register spacing in NEON load/store instructions.
110   // For quad-register load-lane and store-lane pseudo instructors, the
111   // spacing is initially assumed to be EvenDblSpc, and that is changed to
112   // OddDblSpc depending on the lane number operand.
113   enum NEONRegSpacing {
114     SingleSpc,
115     EvenDblSpc,
116     OddDblSpc
117   };
118 
119   // Entries for NEON load/store information table.  The table is sorted by
120   // PseudoOpc for fast binary-search lookups.
121   struct NEONLdStTableEntry {
122     uint16_t PseudoOpc;
123     uint16_t RealOpc;
124     bool IsLoad;
125     bool isUpdating;
126     bool hasWritebackOperand;
127     uint8_t RegSpacing; // One of type NEONRegSpacing
128     uint8_t NumRegs; // D registers loaded or stored
129     uint8_t RegElts; // elements per D register; used for lane ops
130     // FIXME: Temporary flag to denote whether the real instruction takes
131     // a single register (like the encoding) or all of the registers in
132     // the list (like the asm syntax and the isel DAG). When all definitions
133     // are converted to take only the single encoded register, this will
134     // go away.
135     bool copyAllListRegs;
136 
137     // Comparison methods for binary search of the table.
138     bool operator<(const NEONLdStTableEntry &TE) const {
139       return PseudoOpc < TE.PseudoOpc;
140     }
141     friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
142       return TE.PseudoOpc < PseudoOpc;
143     }
144     friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
145                                                 const NEONLdStTableEntry &TE) {
146       return PseudoOpc < TE.PseudoOpc;
147     }
148   };
149 }
150 
151 static const NEONLdStTableEntry NEONLdStTable[] = {
152 { ARM::VLD1LNq16Pseudo,     ARM::VLD1LNd16,     true, false, false, EvenDblSpc, 1, 4 ,true},
153 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true,  EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq32Pseudo,     ARM::VLD1LNd32,     true, false, false, EvenDblSpc, 1, 2 ,true},
155 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true,  EvenDblSpc, 1, 2 ,true},
156 { ARM::VLD1LNq8Pseudo,      ARM::VLD1LNd8,      true, false, false, EvenDblSpc, 1, 8 ,true},
157 { ARM::VLD1LNq8Pseudo_UPD,  ARM::VLD1LNd8_UPD, true, true, true,  EvenDblSpc, 1, 8 ,true},
158 
159 { ARM::VLD1d64QPseudo,      ARM::VLD1d64Q,     true,  false, false, SingleSpc,  4, 1 ,false},
160 { ARM::VLD1d64QPseudoWB_fixed,  ARM::VLD1d64Qwb_fixed,   true,  true, false, SingleSpc,  4, 1 ,false},
161 { ARM::VLD1d64TPseudo,      ARM::VLD1d64T,     true,  false, false, SingleSpc,  3, 1 ,false},
162 { ARM::VLD1d64TPseudoWB_fixed,  ARM::VLD1d64Twb_fixed,   true,  true, false, SingleSpc,  3, 1 ,false},
163 
164 { ARM::VLD2LNd16Pseudo,     ARM::VLD2LNd16,     true, false, false, SingleSpc,  2, 4 ,true},
165 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true,  SingleSpc,  2, 4 ,true},
166 { ARM::VLD2LNd32Pseudo,     ARM::VLD2LNd32,     true, false, false, SingleSpc,  2, 2 ,true},
167 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true,  SingleSpc,  2, 2 ,true},
168 { ARM::VLD2LNd8Pseudo,      ARM::VLD2LNd8,      true, false, false, SingleSpc,  2, 8 ,true},
169 { ARM::VLD2LNd8Pseudo_UPD,  ARM::VLD2LNd8_UPD, true, true, true,  SingleSpc,  2, 8 ,true},
170 { ARM::VLD2LNq16Pseudo,     ARM::VLD2LNq16,     true, false, false, EvenDblSpc, 2, 4 ,true},
171 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true,  EvenDblSpc, 2, 4 ,true},
172 { ARM::VLD2LNq32Pseudo,     ARM::VLD2LNq32,     true, false, false, EvenDblSpc, 2, 2 ,true},
173 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true,  EvenDblSpc, 2, 2 ,true},
174 
175 { ARM::VLD2q16Pseudo,       ARM::VLD2q16,      true,  false, false, SingleSpc,  4, 4 ,false},
176 { ARM::VLD2q16PseudoWB_fixed,   ARM::VLD2q16wb_fixed, true, true, false,  SingleSpc,  4, 4 ,false},
177 { ARM::VLD2q16PseudoWB_register,   ARM::VLD2q16wb_register, true, true, true,  SingleSpc,  4, 4 ,false},
178 { ARM::VLD2q32Pseudo,       ARM::VLD2q32,      true,  false, false, SingleSpc,  4, 2 ,false},
179 { ARM::VLD2q32PseudoWB_fixed,   ARM::VLD2q32wb_fixed, true, true, false,  SingleSpc,  4, 2 ,false},
180 { ARM::VLD2q32PseudoWB_register,   ARM::VLD2q32wb_register, true, true, true,  SingleSpc,  4, 2 ,false},
181 { ARM::VLD2q8Pseudo,        ARM::VLD2q8,       true,  false, false, SingleSpc,  4, 8 ,false},
182 { ARM::VLD2q8PseudoWB_fixed,    ARM::VLD2q8wb_fixed, true, true, false,  SingleSpc,  4, 8 ,false},
183 { ARM::VLD2q8PseudoWB_register,    ARM::VLD2q8wb_register, true, true, true,  SingleSpc,  4, 8 ,false},
184 
185 { ARM::VLD3DUPd16Pseudo,     ARM::VLD3DUPd16,     true, false, false, SingleSpc, 3, 4,true},
186 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true,  SingleSpc, 3, 4,true},
187 { ARM::VLD3DUPd32Pseudo,     ARM::VLD3DUPd32,     true, false, false, SingleSpc, 3, 2,true},
188 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true,  SingleSpc, 3, 2,true},
189 { ARM::VLD3DUPd8Pseudo,      ARM::VLD3DUPd8,      true, false, false, SingleSpc, 3, 8,true},
190 { ARM::VLD3DUPd8Pseudo_UPD,  ARM::VLD3DUPd8_UPD, true, true, true,  SingleSpc, 3, 8,true},
191 
192 { ARM::VLD3LNd16Pseudo,     ARM::VLD3LNd16,     true, false, false, SingleSpc,  3, 4 ,true},
193 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true,  SingleSpc,  3, 4 ,true},
194 { ARM::VLD3LNd32Pseudo,     ARM::VLD3LNd32,     true, false, false, SingleSpc,  3, 2 ,true},
195 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true,  SingleSpc,  3, 2 ,true},
196 { ARM::VLD3LNd8Pseudo,      ARM::VLD3LNd8,      true, false, false, SingleSpc,  3, 8 ,true},
197 { ARM::VLD3LNd8Pseudo_UPD,  ARM::VLD3LNd8_UPD, true, true, true,  SingleSpc,  3, 8 ,true},
198 { ARM::VLD3LNq16Pseudo,     ARM::VLD3LNq16,     true, false, false, EvenDblSpc, 3, 4 ,true},
199 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true,  EvenDblSpc, 3, 4 ,true},
200 { ARM::VLD3LNq32Pseudo,     ARM::VLD3LNq32,     true, false, false, EvenDblSpc, 3, 2 ,true},
201 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true,  EvenDblSpc, 3, 2 ,true},
202 
203 { ARM::VLD3d16Pseudo,       ARM::VLD3d16,      true,  false, false, SingleSpc,  3, 4 ,true},
204 { ARM::VLD3d16Pseudo_UPD,   ARM::VLD3d16_UPD, true, true, true,  SingleSpc,  3, 4 ,true},
205 { ARM::VLD3d32Pseudo,       ARM::VLD3d32,      true,  false, false, SingleSpc,  3, 2 ,true},
206 { ARM::VLD3d32Pseudo_UPD,   ARM::VLD3d32_UPD, true, true, true,  SingleSpc,  3, 2 ,true},
207 { ARM::VLD3d8Pseudo,        ARM::VLD3d8,       true,  false, false, SingleSpc,  3, 8 ,true},
208 { ARM::VLD3d8Pseudo_UPD,    ARM::VLD3d8_UPD, true, true, true,  SingleSpc,  3, 8 ,true},
209 
210 { ARM::VLD3q16Pseudo_UPD,    ARM::VLD3q16_UPD, true, true, true,  EvenDblSpc, 3, 4 ,true},
211 { ARM::VLD3q16oddPseudo,     ARM::VLD3q16,     true,  false, false, OddDblSpc,  3, 4 ,true},
212 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true,  OddDblSpc,  3, 4 ,true},
213 { ARM::VLD3q32Pseudo_UPD,    ARM::VLD3q32_UPD, true, true, true,  EvenDblSpc, 3, 2 ,true},
214 { ARM::VLD3q32oddPseudo,     ARM::VLD3q32,     true,  false, false, OddDblSpc,  3, 2 ,true},
215 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true,  OddDblSpc,  3, 2 ,true},
216 { ARM::VLD3q8Pseudo_UPD,     ARM::VLD3q8_UPD, true, true, true,  EvenDblSpc, 3, 8 ,true},
217 { ARM::VLD3q8oddPseudo,      ARM::VLD3q8,      true,  false, false, OddDblSpc,  3, 8 ,true},
218 { ARM::VLD3q8oddPseudo_UPD,  ARM::VLD3q8_UPD, true, true, true,  OddDblSpc,  3, 8 ,true},
219 
220 { ARM::VLD4DUPd16Pseudo,     ARM::VLD4DUPd16,     true, false, false, SingleSpc, 4, 4,true},
221 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true,  SingleSpc, 4, 4,true},
222 { ARM::VLD4DUPd32Pseudo,     ARM::VLD4DUPd32,     true, false, false, SingleSpc, 4, 2,true},
223 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true,  SingleSpc, 4, 2,true},
224 { ARM::VLD4DUPd8Pseudo,      ARM::VLD4DUPd8,      true, false, false, SingleSpc, 4, 8,true},
225 { ARM::VLD4DUPd8Pseudo_UPD,  ARM::VLD4DUPd8_UPD, true, true, true,  SingleSpc, 4, 8,true},
226 
227 { ARM::VLD4LNd16Pseudo,     ARM::VLD4LNd16,     true, false, false, SingleSpc,  4, 4 ,true},
228 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true,  SingleSpc,  4, 4 ,true},
229 { ARM::VLD4LNd32Pseudo,     ARM::VLD4LNd32,     true, false, false, SingleSpc,  4, 2 ,true},
230 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true,  SingleSpc,  4, 2 ,true},
231 { ARM::VLD4LNd8Pseudo,      ARM::VLD4LNd8,      true, false, false, SingleSpc,  4, 8 ,true},
232 { ARM::VLD4LNd8Pseudo_UPD,  ARM::VLD4LNd8_UPD, true, true, true,  SingleSpc,  4, 8 ,true},
233 { ARM::VLD4LNq16Pseudo,     ARM::VLD4LNq16,     true, false, false, EvenDblSpc, 4, 4 ,true},
234 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true,  EvenDblSpc, 4, 4 ,true},
235 { ARM::VLD4LNq32Pseudo,     ARM::VLD4LNq32,     true, false, false, EvenDblSpc, 4, 2 ,true},
236 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true,  EvenDblSpc, 4, 2 ,true},
237 
238 { ARM::VLD4d16Pseudo,       ARM::VLD4d16,      true,  false, false, SingleSpc,  4, 4 ,true},
239 { ARM::VLD4d16Pseudo_UPD,   ARM::VLD4d16_UPD, true, true, true,  SingleSpc,  4, 4 ,true},
240 { ARM::VLD4d32Pseudo,       ARM::VLD4d32,      true,  false, false, SingleSpc,  4, 2 ,true},
241 { ARM::VLD4d32Pseudo_UPD,   ARM::VLD4d32_UPD, true, true, true,  SingleSpc,  4, 2 ,true},
242 { ARM::VLD4d8Pseudo,        ARM::VLD4d8,       true,  false, false, SingleSpc,  4, 8 ,true},
243 { ARM::VLD4d8Pseudo_UPD,    ARM::VLD4d8_UPD, true, true, true,  SingleSpc,  4, 8 ,true},
244 
245 { ARM::VLD4q16Pseudo_UPD,    ARM::VLD4q16_UPD, true, true, true,  EvenDblSpc, 4, 4 ,true},
246 { ARM::VLD4q16oddPseudo,     ARM::VLD4q16,     true,  false, false, OddDblSpc,  4, 4 ,true},
247 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true,  OddDblSpc,  4, 4 ,true},
248 { ARM::VLD4q32Pseudo_UPD,    ARM::VLD4q32_UPD, true, true, true,  EvenDblSpc, 4, 2 ,true},
249 { ARM::VLD4q32oddPseudo,     ARM::VLD4q32,     true,  false, false, OddDblSpc,  4, 2 ,true},
250 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true,  OddDblSpc,  4, 2 ,true},
251 { ARM::VLD4q8Pseudo_UPD,     ARM::VLD4q8_UPD, true, true, true,  EvenDblSpc, 4, 8 ,true},
252 { ARM::VLD4q8oddPseudo,      ARM::VLD4q8,      true,  false, false, OddDblSpc,  4, 8 ,true},
253 { ARM::VLD4q8oddPseudo_UPD,  ARM::VLD4q8_UPD, true, true, true,  OddDblSpc,  4, 8 ,true},
254 
255 { ARM::VST1LNq16Pseudo,     ARM::VST1LNd16,    false, false, false, EvenDblSpc, 1, 4 ,true},
256 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true,  EvenDblSpc, 1, 4 ,true},
257 { ARM::VST1LNq32Pseudo,     ARM::VST1LNd32,    false, false, false, EvenDblSpc, 1, 2 ,true},
258 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true,  EvenDblSpc, 1, 2 ,true},
259 { ARM::VST1LNq8Pseudo,      ARM::VST1LNd8,     false, false, false, EvenDblSpc, 1, 8 ,true},
260 { ARM::VST1LNq8Pseudo_UPD,  ARM::VST1LNd8_UPD, false, true, true,  EvenDblSpc, 1, 8 ,true},
261 
262 { ARM::VST1d64QPseudo,      ARM::VST1d64Q,     false, false, false, SingleSpc,  4, 1 ,false},
263 { ARM::VST1d64QPseudoWB_fixed,  ARM::VST1d64Qwb_fixed, false, true, false,  SingleSpc,  4, 1 ,false},
264 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true,  SingleSpc,  4, 1 ,false},
265 { ARM::VST1d64TPseudo,      ARM::VST1d64T,     false, false, false, SingleSpc,  3, 1 ,false},
266 { ARM::VST1d64TPseudoWB_fixed,  ARM::VST1d64Twb_fixed, false, true, false,  SingleSpc,  3, 1 ,false},
267 { ARM::VST1d64TPseudoWB_register,  ARM::VST1d64Twb_register, false, true, true,  SingleSpc,  3, 1 ,false},
268 
269 { ARM::VST2LNd16Pseudo,     ARM::VST2LNd16,     false, false, false, SingleSpc, 2, 4 ,true},
270 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true,  SingleSpc, 2, 4 ,true},
271 { ARM::VST2LNd32Pseudo,     ARM::VST2LNd32,     false, false, false, SingleSpc, 2, 2 ,true},
272 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true,  SingleSpc, 2, 2 ,true},
273 { ARM::VST2LNd8Pseudo,      ARM::VST2LNd8,      false, false, false, SingleSpc, 2, 8 ,true},
274 { ARM::VST2LNd8Pseudo_UPD,  ARM::VST2LNd8_UPD, false, true, true,  SingleSpc, 2, 8 ,true},
275 { ARM::VST2LNq16Pseudo,     ARM::VST2LNq16,     false, false, false, EvenDblSpc, 2, 4,true},
276 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true,  EvenDblSpc, 2, 4,true},
277 { ARM::VST2LNq32Pseudo,     ARM::VST2LNq32,     false, false, false, EvenDblSpc, 2, 2,true},
278 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true,  EvenDblSpc, 2, 2,true},
279 
280 { ARM::VST2q16Pseudo,       ARM::VST2q16,      false, false, false, SingleSpc,  4, 4 ,false},
281 { ARM::VST2q16PseudoWB_fixed,   ARM::VST2q16wb_fixed, false, true, false,  SingleSpc,  4, 4 ,false},
282 { ARM::VST2q16PseudoWB_register,   ARM::VST2q16wb_register, false, true, true,  SingleSpc,  4, 4 ,false},
283 { ARM::VST2q32Pseudo,       ARM::VST2q32,      false, false, false, SingleSpc,  4, 2 ,false},
284 { ARM::VST2q32PseudoWB_fixed,   ARM::VST2q32wb_fixed, false, true, false,  SingleSpc,  4, 2 ,false},
285 { ARM::VST2q32PseudoWB_register,   ARM::VST2q32wb_register, false, true, true,  SingleSpc,  4, 2 ,false},
286 { ARM::VST2q8Pseudo,        ARM::VST2q8,       false, false, false, SingleSpc,  4, 8 ,false},
287 { ARM::VST2q8PseudoWB_fixed,    ARM::VST2q8wb_fixed, false, true, false,  SingleSpc,  4, 8 ,false},
288 { ARM::VST2q8PseudoWB_register,    ARM::VST2q8wb_register, false, true, true,  SingleSpc,  4, 8 ,false},
289 
290 { ARM::VST3LNd16Pseudo,     ARM::VST3LNd16,     false, false, false, SingleSpc, 3, 4 ,true},
291 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true,  SingleSpc, 3, 4 ,true},
292 { ARM::VST3LNd32Pseudo,     ARM::VST3LNd32,     false, false, false, SingleSpc, 3, 2 ,true},
293 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true,  SingleSpc, 3, 2 ,true},
294 { ARM::VST3LNd8Pseudo,      ARM::VST3LNd8,      false, false, false, SingleSpc, 3, 8 ,true},
295 { ARM::VST3LNd8Pseudo_UPD,  ARM::VST3LNd8_UPD, false, true, true,  SingleSpc, 3, 8 ,true},
296 { ARM::VST3LNq16Pseudo,     ARM::VST3LNq16,     false, false, false, EvenDblSpc, 3, 4,true},
297 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true,  EvenDblSpc, 3, 4,true},
298 { ARM::VST3LNq32Pseudo,     ARM::VST3LNq32,     false, false, false, EvenDblSpc, 3, 2,true},
299 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true,  EvenDblSpc, 3, 2,true},
300 
301 { ARM::VST3d16Pseudo,       ARM::VST3d16,      false, false, false, SingleSpc,  3, 4 ,true},
302 { ARM::VST3d16Pseudo_UPD,   ARM::VST3d16_UPD, false, true, true,  SingleSpc,  3, 4 ,true},
303 { ARM::VST3d32Pseudo,       ARM::VST3d32,      false, false, false, SingleSpc,  3, 2 ,true},
304 { ARM::VST3d32Pseudo_UPD,   ARM::VST3d32_UPD, false, true, true,  SingleSpc,  3, 2 ,true},
305 { ARM::VST3d8Pseudo,        ARM::VST3d8,       false, false, false, SingleSpc,  3, 8 ,true},
306 { ARM::VST3d8Pseudo_UPD,    ARM::VST3d8_UPD, false, true, true,  SingleSpc,  3, 8 ,true},
307 
308 { ARM::VST3q16Pseudo_UPD,    ARM::VST3q16_UPD, false, true, true,  EvenDblSpc, 3, 4 ,true},
309 { ARM::VST3q16oddPseudo,     ARM::VST3q16,     false, false, false, OddDblSpc,  3, 4 ,true},
310 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true,  OddDblSpc,  3, 4 ,true},
311 { ARM::VST3q32Pseudo_UPD,    ARM::VST3q32_UPD, false, true, true,  EvenDblSpc, 3, 2 ,true},
312 { ARM::VST3q32oddPseudo,     ARM::VST3q32,     false, false, false, OddDblSpc,  3, 2 ,true},
313 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true,  OddDblSpc,  3, 2 ,true},
314 { ARM::VST3q8Pseudo_UPD,     ARM::VST3q8_UPD, false, true, true,  EvenDblSpc, 3, 8 ,true},
315 { ARM::VST3q8oddPseudo,      ARM::VST3q8,      false, false, false, OddDblSpc,  3, 8 ,true},
316 { ARM::VST3q8oddPseudo_UPD,  ARM::VST3q8_UPD, false, true, true,  OddDblSpc,  3, 8 ,true},
317 
318 { ARM::VST4LNd16Pseudo,     ARM::VST4LNd16,     false, false, false, SingleSpc, 4, 4 ,true},
319 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true,  SingleSpc, 4, 4 ,true},
320 { ARM::VST4LNd32Pseudo,     ARM::VST4LNd32,     false, false, false, SingleSpc, 4, 2 ,true},
321 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true,  SingleSpc, 4, 2 ,true},
322 { ARM::VST4LNd8Pseudo,      ARM::VST4LNd8,      false, false, false, SingleSpc, 4, 8 ,true},
323 { ARM::VST4LNd8Pseudo_UPD,  ARM::VST4LNd8_UPD, false, true, true,  SingleSpc, 4, 8 ,true},
324 { ARM::VST4LNq16Pseudo,     ARM::VST4LNq16,     false, false, false, EvenDblSpc, 4, 4,true},
325 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true,  EvenDblSpc, 4, 4,true},
326 { ARM::VST4LNq32Pseudo,     ARM::VST4LNq32,     false, false, false, EvenDblSpc, 4, 2,true},
327 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true,  EvenDblSpc, 4, 2,true},
328 
329 { ARM::VST4d16Pseudo,       ARM::VST4d16,      false, false, false, SingleSpc,  4, 4 ,true},
330 { ARM::VST4d16Pseudo_UPD,   ARM::VST4d16_UPD, false, true, true,  SingleSpc,  4, 4 ,true},
331 { ARM::VST4d32Pseudo,       ARM::VST4d32,      false, false, false, SingleSpc,  4, 2 ,true},
332 { ARM::VST4d32Pseudo_UPD,   ARM::VST4d32_UPD, false, true, true,  SingleSpc,  4, 2 ,true},
333 { ARM::VST4d8Pseudo,        ARM::VST4d8,       false, false, false, SingleSpc,  4, 8 ,true},
334 { ARM::VST4d8Pseudo_UPD,    ARM::VST4d8_UPD, false, true, true,  SingleSpc,  4, 8 ,true},
335 
336 { ARM::VST4q16Pseudo_UPD,    ARM::VST4q16_UPD, false, true, true,  EvenDblSpc, 4, 4 ,true},
337 { ARM::VST4q16oddPseudo,     ARM::VST4q16,     false, false, false, OddDblSpc,  4, 4 ,true},
338 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true,  OddDblSpc,  4, 4 ,true},
339 { ARM::VST4q32Pseudo_UPD,    ARM::VST4q32_UPD, false, true, true,  EvenDblSpc, 4, 2 ,true},
340 { ARM::VST4q32oddPseudo,     ARM::VST4q32,     false, false, false, OddDblSpc,  4, 2 ,true},
341 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true,  OddDblSpc,  4, 2 ,true},
342 { ARM::VST4q8Pseudo_UPD,     ARM::VST4q8_UPD, false, true, true,  EvenDblSpc, 4, 8 ,true},
343 { ARM::VST4q8oddPseudo,      ARM::VST4q8,      false, false, false, OddDblSpc,  4, 8 ,true},
344 { ARM::VST4q8oddPseudo_UPD,  ARM::VST4q8_UPD, false, true, true,  OddDblSpc,  4, 8 ,true}
345 };
346 
347 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
348 /// load or store pseudo instruction.
349 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
350 #ifndef NDEBUG
351   // Make sure the table is sorted.
352   static bool TableChecked = false;
353   if (!TableChecked) {
354     assert(std::is_sorted(std::begin(NEONLdStTable), std::end(NEONLdStTable)) &&
355            "NEONLdStTable is not sorted!");
356     TableChecked = true;
357   }
358 #endif
359 
360   auto I = std::lower_bound(std::begin(NEONLdStTable),
361                             std::end(NEONLdStTable), Opcode);
362   if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode)
363     return I;
364   return nullptr;
365 }
366 
367 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
368 /// corresponding to the specified register spacing.  Not all of the results
369 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
370 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
371                         const TargetRegisterInfo *TRI, unsigned &D0,
372                         unsigned &D1, unsigned &D2, unsigned &D3) {
373   if (RegSpc == SingleSpc) {
374     D0 = TRI->getSubReg(Reg, ARM::dsub_0);
375     D1 = TRI->getSubReg(Reg, ARM::dsub_1);
376     D2 = TRI->getSubReg(Reg, ARM::dsub_2);
377     D3 = TRI->getSubReg(Reg, ARM::dsub_3);
378   } else if (RegSpc == EvenDblSpc) {
379     D0 = TRI->getSubReg(Reg, ARM::dsub_0);
380     D1 = TRI->getSubReg(Reg, ARM::dsub_2);
381     D2 = TRI->getSubReg(Reg, ARM::dsub_4);
382     D3 = TRI->getSubReg(Reg, ARM::dsub_6);
383   } else {
384     assert(RegSpc == OddDblSpc && "unknown register spacing");
385     D0 = TRI->getSubReg(Reg, ARM::dsub_1);
386     D1 = TRI->getSubReg(Reg, ARM::dsub_3);
387     D2 = TRI->getSubReg(Reg, ARM::dsub_5);
388     D3 = TRI->getSubReg(Reg, ARM::dsub_7);
389   }
390 }
391 
392 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
393 /// operands to real VLD instructions with D register operands.
394 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
395   MachineInstr &MI = *MBBI;
396   MachineBasicBlock &MBB = *MI.getParent();
397 
398   const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
399   assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
400   NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
401   unsigned NumRegs = TableEntry->NumRegs;
402 
403   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
404                                     TII->get(TableEntry->RealOpc));
405   unsigned OpIdx = 0;
406 
407   bool DstIsDead = MI.getOperand(OpIdx).isDead();
408   unsigned DstReg = MI.getOperand(OpIdx++).getReg();
409   unsigned D0, D1, D2, D3;
410   GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
411   MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
412   if (NumRegs > 1 && TableEntry->copyAllListRegs)
413     MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
414   if (NumRegs > 2 && TableEntry->copyAllListRegs)
415     MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
416   if (NumRegs > 3 && TableEntry->copyAllListRegs)
417     MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
418 
419   if (TableEntry->isUpdating)
420     MIB.add(MI.getOperand(OpIdx++));
421 
422   // Copy the addrmode6 operands.
423   MIB.add(MI.getOperand(OpIdx++));
424   MIB.add(MI.getOperand(OpIdx++));
425   // Copy the am6offset operand.
426   if (TableEntry->hasWritebackOperand)
427     MIB.add(MI.getOperand(OpIdx++));
428 
429   // For an instruction writing double-spaced subregs, the pseudo instruction
430   // has an extra operand that is a use of the super-register.  Record the
431   // operand index and skip over it.
432   unsigned SrcOpIdx = 0;
433   if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
434     SrcOpIdx = OpIdx++;
435 
436   // Copy the predicate operands.
437   MIB.add(MI.getOperand(OpIdx++));
438   MIB.add(MI.getOperand(OpIdx++));
439 
440   // Copy the super-register source operand used for double-spaced subregs over
441   // to the new instruction as an implicit operand.
442   if (SrcOpIdx != 0) {
443     MachineOperand MO = MI.getOperand(SrcOpIdx);
444     MO.setImplicit(true);
445     MIB.add(MO);
446   }
447   // Add an implicit def for the super-register.
448   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
449   TransferImpOps(MI, MIB, MIB);
450 
451   // Transfer memoperands.
452   MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
453 
454   MI.eraseFromParent();
455 }
456 
457 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
458 /// operands to real VST instructions with D register operands.
459 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
460   MachineInstr &MI = *MBBI;
461   MachineBasicBlock &MBB = *MI.getParent();
462 
463   const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
464   assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
465   NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
466   unsigned NumRegs = TableEntry->NumRegs;
467 
468   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
469                                     TII->get(TableEntry->RealOpc));
470   unsigned OpIdx = 0;
471   if (TableEntry->isUpdating)
472     MIB.add(MI.getOperand(OpIdx++));
473 
474   // Copy the addrmode6 operands.
475   MIB.add(MI.getOperand(OpIdx++));
476   MIB.add(MI.getOperand(OpIdx++));
477   // Copy the am6offset operand.
478   if (TableEntry->hasWritebackOperand)
479     MIB.add(MI.getOperand(OpIdx++));
480 
481   bool SrcIsKill = MI.getOperand(OpIdx).isKill();
482   bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
483   unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
484   unsigned D0, D1, D2, D3;
485   GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
486   MIB.addReg(D0, getUndefRegState(SrcIsUndef));
487   if (NumRegs > 1 && TableEntry->copyAllListRegs)
488     MIB.addReg(D1, getUndefRegState(SrcIsUndef));
489   if (NumRegs > 2 && TableEntry->copyAllListRegs)
490     MIB.addReg(D2, getUndefRegState(SrcIsUndef));
491   if (NumRegs > 3 && TableEntry->copyAllListRegs)
492     MIB.addReg(D3, getUndefRegState(SrcIsUndef));
493 
494   // Copy the predicate operands.
495   MIB.add(MI.getOperand(OpIdx++));
496   MIB.add(MI.getOperand(OpIdx++));
497 
498   if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
499     MIB->addRegisterKilled(SrcReg, TRI, true);
500   else if (!SrcIsUndef)
501     MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
502   TransferImpOps(MI, MIB, MIB);
503 
504   // Transfer memoperands.
505   MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
506 
507   MI.eraseFromParent();
508 }
509 
510 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
511 /// register operands to real instructions with D register operands.
512 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
513   MachineInstr &MI = *MBBI;
514   MachineBasicBlock &MBB = *MI.getParent();
515 
516   const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
517   assert(TableEntry && "NEONLdStTable lookup failed");
518   NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
519   unsigned NumRegs = TableEntry->NumRegs;
520   unsigned RegElts = TableEntry->RegElts;
521 
522   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
523                                     TII->get(TableEntry->RealOpc));
524   unsigned OpIdx = 0;
525   // The lane operand is always the 3rd from last operand, before the 2
526   // predicate operands.
527   unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
528 
529   // Adjust the lane and spacing as needed for Q registers.
530   assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
531   if (RegSpc == EvenDblSpc && Lane >= RegElts) {
532     RegSpc = OddDblSpc;
533     Lane -= RegElts;
534   }
535   assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
536 
537   unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
538   unsigned DstReg = 0;
539   bool DstIsDead = false;
540   if (TableEntry->IsLoad) {
541     DstIsDead = MI.getOperand(OpIdx).isDead();
542     DstReg = MI.getOperand(OpIdx++).getReg();
543     GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
544     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
545     if (NumRegs > 1)
546       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
547     if (NumRegs > 2)
548       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
549     if (NumRegs > 3)
550       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
551   }
552 
553   if (TableEntry->isUpdating)
554     MIB.add(MI.getOperand(OpIdx++));
555 
556   // Copy the addrmode6 operands.
557   MIB.add(MI.getOperand(OpIdx++));
558   MIB.add(MI.getOperand(OpIdx++));
559   // Copy the am6offset operand.
560   if (TableEntry->hasWritebackOperand)
561     MIB.add(MI.getOperand(OpIdx++));
562 
563   // Grab the super-register source.
564   MachineOperand MO = MI.getOperand(OpIdx++);
565   if (!TableEntry->IsLoad)
566     GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
567 
568   // Add the subregs as sources of the new instruction.
569   unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
570                        getKillRegState(MO.isKill()));
571   MIB.addReg(D0, SrcFlags);
572   if (NumRegs > 1)
573     MIB.addReg(D1, SrcFlags);
574   if (NumRegs > 2)
575     MIB.addReg(D2, SrcFlags);
576   if (NumRegs > 3)
577     MIB.addReg(D3, SrcFlags);
578 
579   // Add the lane number operand.
580   MIB.addImm(Lane);
581   OpIdx += 1;
582 
583   // Copy the predicate operands.
584   MIB.add(MI.getOperand(OpIdx++));
585   MIB.add(MI.getOperand(OpIdx++));
586 
587   // Copy the super-register source to be an implicit source.
588   MO.setImplicit(true);
589   MIB.add(MO);
590   if (TableEntry->IsLoad)
591     // Add an implicit def for the super-register.
592     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
593   TransferImpOps(MI, MIB, MIB);
594   // Transfer memoperands.
595   MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
596   MI.eraseFromParent();
597 }
598 
599 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
600 /// register operands to real instructions with D register operands.
601 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
602                                  unsigned Opc, bool IsExt) {
603   MachineInstr &MI = *MBBI;
604   MachineBasicBlock &MBB = *MI.getParent();
605 
606   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
607   unsigned OpIdx = 0;
608 
609   // Transfer the destination register operand.
610   MIB.add(MI.getOperand(OpIdx++));
611   if (IsExt)
612     MIB.add(MI.getOperand(OpIdx++));
613 
614   bool SrcIsKill = MI.getOperand(OpIdx).isKill();
615   unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
616   unsigned D0, D1, D2, D3;
617   GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
618   MIB.addReg(D0);
619 
620   // Copy the other source register operand.
621   MIB.add(MI.getOperand(OpIdx++));
622 
623   // Copy the predicate operands.
624   MIB.add(MI.getOperand(OpIdx++));
625   MIB.add(MI.getOperand(OpIdx++));
626 
627   // Add an implicit kill and use for the super-reg.
628   MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
629   TransferImpOps(MI, MIB, MIB);
630   MI.eraseFromParent();
631 }
632 
633 static bool IsAnAddressOperand(const MachineOperand &MO) {
634   // This check is overly conservative.  Unless we are certain that the machine
635   // operand is not a symbol reference, we return that it is a symbol reference.
636   // This is important as the load pair may not be split up Windows.
637   switch (MO.getType()) {
638   case MachineOperand::MO_Register:
639   case MachineOperand::MO_Immediate:
640   case MachineOperand::MO_CImmediate:
641   case MachineOperand::MO_FPImmediate:
642     return false;
643   case MachineOperand::MO_MachineBasicBlock:
644     return true;
645   case MachineOperand::MO_FrameIndex:
646     return false;
647   case MachineOperand::MO_ConstantPoolIndex:
648   case MachineOperand::MO_TargetIndex:
649   case MachineOperand::MO_JumpTableIndex:
650   case MachineOperand::MO_ExternalSymbol:
651   case MachineOperand::MO_GlobalAddress:
652   case MachineOperand::MO_BlockAddress:
653     return true;
654   case MachineOperand::MO_RegisterMask:
655   case MachineOperand::MO_RegisterLiveOut:
656     return false;
657   case MachineOperand::MO_Metadata:
658   case MachineOperand::MO_MCSymbol:
659     return true;
660   case MachineOperand::MO_CFIIndex:
661     return false;
662   case MachineOperand::MO_IntrinsicID:
663   case MachineOperand::MO_Predicate:
664     llvm_unreachable("should not exist post-isel");
665   }
666   llvm_unreachable("unhandled machine operand type");
667 }
668 
669 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
670                                         MachineBasicBlock::iterator &MBBI) {
671   MachineInstr &MI = *MBBI;
672   unsigned Opcode = MI.getOpcode();
673   unsigned PredReg = 0;
674   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
675   unsigned DstReg = MI.getOperand(0).getReg();
676   bool DstIsDead = MI.getOperand(0).isDead();
677   bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
678   const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
679   bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
680   MachineInstrBuilder LO16, HI16;
681 
682   if (!STI->hasV6T2Ops() &&
683       (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
684     // FIXME Windows CE supports older ARM CPUs
685     assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
686 
687     // Expand into a movi + orr.
688     LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
689     HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
690       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
691       .addReg(DstReg);
692 
693     assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
694     unsigned ImmVal = (unsigned)MO.getImm();
695     unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
696     unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
697     LO16 = LO16.addImm(SOImmValV1);
698     HI16 = HI16.addImm(SOImmValV2);
699     LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
700     HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
701     LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());
702     HI16.addImm(Pred).addReg(PredReg).add(condCodeOp());
703     TransferImpOps(MI, LO16, HI16);
704     MI.eraseFromParent();
705     return;
706   }
707 
708   unsigned LO16Opc = 0;
709   unsigned HI16Opc = 0;
710   if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
711     LO16Opc = ARM::t2MOVi16;
712     HI16Opc = ARM::t2MOVTi16;
713   } else {
714     LO16Opc = ARM::MOVi16;
715     HI16Opc = ARM::MOVTi16;
716   }
717 
718   LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
719   HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
720     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
721     .addReg(DstReg);
722 
723   switch (MO.getType()) {
724   case MachineOperand::MO_Immediate: {
725     unsigned Imm = MO.getImm();
726     unsigned Lo16 = Imm & 0xffff;
727     unsigned Hi16 = (Imm >> 16) & 0xffff;
728     LO16 = LO16.addImm(Lo16);
729     HI16 = HI16.addImm(Hi16);
730     break;
731   }
732   case MachineOperand::MO_ExternalSymbol: {
733     const char *ES = MO.getSymbolName();
734     unsigned TF = MO.getTargetFlags();
735     LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16);
736     HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16);
737     break;
738   }
739   default: {
740     const GlobalValue *GV = MO.getGlobal();
741     unsigned TF = MO.getTargetFlags();
742     LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
743     HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
744     break;
745   }
746   }
747 
748   LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
749   HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
750   LO16.addImm(Pred).addReg(PredReg);
751   HI16.addImm(Pred).addReg(PredReg);
752 
753   if (RequiresBundling)
754     finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
755 
756   TransferImpOps(MI, LO16, HI16);
757   MI.eraseFromParent();
758 }
759 
760 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as
761 /// possible. This only gets used at -O0 so we don't care about efficiency of
762 /// the generated code.
763 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
764                                      MachineBasicBlock::iterator MBBI,
765                                      unsigned LdrexOp, unsigned StrexOp,
766                                      unsigned UxtOp,
767                                      MachineBasicBlock::iterator &NextMBBI) {
768   bool IsThumb = STI->isThumb();
769   MachineInstr &MI = *MBBI;
770   DebugLoc DL = MI.getDebugLoc();
771   const MachineOperand &Dest = MI.getOperand(0);
772   unsigned StatusReg = MI.getOperand(1).getReg();
773   bool StatusDead = MI.getOperand(1).isDead();
774   // Duplicating undef operands into 2 instructions does not guarantee the same
775   // value on both; However undef should be replaced by xzr anyway.
776   assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
777   unsigned AddrReg = MI.getOperand(2).getReg();
778   unsigned DesiredReg = MI.getOperand(3).getReg();
779   unsigned NewReg = MI.getOperand(4).getReg();
780 
781   MachineFunction *MF = MBB.getParent();
782   auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
783   auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
784   auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
785 
786   MF->insert(++MBB.getIterator(), LoadCmpBB);
787   MF->insert(++LoadCmpBB->getIterator(), StoreBB);
788   MF->insert(++StoreBB->getIterator(), DoneBB);
789 
790   if (UxtOp) {
791     MachineInstrBuilder MIB =
792         BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
793             .addReg(DesiredReg, RegState::Kill);
794     if (!IsThumb)
795       MIB.addImm(0);
796     MIB.add(predOps(ARMCC::AL));
797   }
798 
799   // .Lloadcmp:
800   //     mov wStatus, #0
801   //     ldrex rDest, [rAddr]
802   //     cmp rDest, rDesired
803   //     bne .Ldone
804   if (!StatusDead) {
805     if (IsThumb) {
806       BuildMI(LoadCmpBB, DL, TII->get(ARM::tMOVi8), StatusReg)
807         .addDef(ARM::CPSR, RegState::Dead)
808         .addImm(0)
809         .add(predOps(ARMCC::AL));
810     } else {
811       BuildMI(LoadCmpBB, DL, TII->get(ARM::MOVi), StatusReg)
812         .addImm(0)
813         .add(predOps(ARMCC::AL))
814         .add(condCodeOp());
815     }
816   }
817 
818   MachineInstrBuilder MIB;
819   MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
820   MIB.addReg(AddrReg);
821   if (LdrexOp == ARM::t2LDREX)
822     MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset.
823   MIB.add(predOps(ARMCC::AL));
824 
825   unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
826   BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
827       .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
828       .addReg(DesiredReg)
829       .add(predOps(ARMCC::AL));
830   unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
831   BuildMI(LoadCmpBB, DL, TII->get(Bcc))
832       .addMBB(DoneBB)
833       .addImm(ARMCC::NE)
834       .addReg(ARM::CPSR, RegState::Kill);
835   LoadCmpBB->addSuccessor(DoneBB);
836   LoadCmpBB->addSuccessor(StoreBB);
837 
838   // .Lstore:
839   //     strex rStatus, rNew, [rAddr]
840   //     cmp rStatus, #0
841   //     bne .Lloadcmp
842   MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), StatusReg)
843     .addReg(NewReg)
844     .addReg(AddrReg);
845   if (StrexOp == ARM::t2STREX)
846     MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
847   MIB.add(predOps(ARMCC::AL));
848 
849   unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
850   BuildMI(StoreBB, DL, TII->get(CMPri))
851       .addReg(StatusReg, getKillRegState(StatusDead))
852       .addImm(0)
853       .add(predOps(ARMCC::AL));
854   BuildMI(StoreBB, DL, TII->get(Bcc))
855       .addMBB(LoadCmpBB)
856       .addImm(ARMCC::NE)
857       .addReg(ARM::CPSR, RegState::Kill);
858   StoreBB->addSuccessor(LoadCmpBB);
859   StoreBB->addSuccessor(DoneBB);
860 
861   DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
862   DoneBB->transferSuccessors(&MBB);
863 
864   MBB.addSuccessor(LoadCmpBB);
865 
866   NextMBBI = MBB.end();
867   MI.eraseFromParent();
868 
869   // Recompute livein lists.
870   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
871   LivePhysRegs LiveRegs;
872   computeLiveIns(LiveRegs, MRI, *DoneBB);
873   computeLiveIns(LiveRegs, MRI, *StoreBB);
874   computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
875   // Do an extra pass around the loop to get loop carried registers right.
876   StoreBB->clearLiveIns();
877   computeLiveIns(LiveRegs, MRI, *StoreBB);
878   LoadCmpBB->clearLiveIns();
879   computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
880 
881   return true;
882 }
883 
884 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a
885 /// single GPRPair register), Thumb's take two separate registers so we need to
886 /// extract the subregs from the pair.
887 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
888                                 unsigned Flags, bool IsThumb,
889                                 const TargetRegisterInfo *TRI) {
890   if (IsThumb) {
891     unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
892     unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
893     MIB.addReg(RegLo, Flags | getKillRegState(Reg.isDead()));
894     MIB.addReg(RegHi, Flags | getKillRegState(Reg.isDead()));
895   } else
896     MIB.addReg(Reg.getReg(), Flags | getKillRegState(Reg.isDead()));
897 }
898 
899 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop.
900 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
901                                         MachineBasicBlock::iterator MBBI,
902                                         MachineBasicBlock::iterator &NextMBBI) {
903   bool IsThumb = STI->isThumb();
904   MachineInstr &MI = *MBBI;
905   DebugLoc DL = MI.getDebugLoc();
906   MachineOperand &Dest = MI.getOperand(0);
907   unsigned StatusReg = MI.getOperand(1).getReg();
908   bool StatusDead = MI.getOperand(1).isDead();
909   // Duplicating undef operands into 2 instructions does not guarantee the same
910   // value on both; However undef should be replaced by xzr anyway.
911   assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
912   unsigned AddrReg = MI.getOperand(2).getReg();
913   unsigned DesiredReg = MI.getOperand(3).getReg();
914   MachineOperand New = MI.getOperand(4);
915   New.setIsKill(false);
916 
917   unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
918   unsigned DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
919   unsigned DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
920   unsigned DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
921 
922   MachineFunction *MF = MBB.getParent();
923   auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
924   auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
925   auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
926 
927   MF->insert(++MBB.getIterator(), LoadCmpBB);
928   MF->insert(++LoadCmpBB->getIterator(), StoreBB);
929   MF->insert(++StoreBB->getIterator(), DoneBB);
930 
931   // .Lloadcmp:
932   //     ldrexd rDestLo, rDestHi, [rAddr]
933   //     cmp rDestLo, rDesiredLo
934   //     sbcs rStatus<dead>, rDestHi, rDesiredHi
935   //     bne .Ldone
936   unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
937   MachineInstrBuilder MIB;
938   MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
939   addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);
940   MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
941 
942   unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
943   BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
944       .addReg(DestLo, getKillRegState(Dest.isDead()))
945       .addReg(DesiredLo)
946       .add(predOps(ARMCC::AL));
947 
948   BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
949       .addReg(DestHi, getKillRegState(Dest.isDead()))
950       .addReg(DesiredHi)
951       .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
952 
953   unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
954   BuildMI(LoadCmpBB, DL, TII->get(Bcc))
955       .addMBB(DoneBB)
956       .addImm(ARMCC::NE)
957       .addReg(ARM::CPSR, RegState::Kill);
958   LoadCmpBB->addSuccessor(DoneBB);
959   LoadCmpBB->addSuccessor(StoreBB);
960 
961   // .Lstore:
962   //     strexd rStatus, rNewLo, rNewHi, [rAddr]
963   //     cmp rStatus, #0
964   //     bne .Lloadcmp
965   unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
966   MIB = BuildMI(StoreBB, DL, TII->get(STREXD), StatusReg);
967   addExclusiveRegPair(MIB, New, 0, IsThumb, TRI);
968   MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
969 
970   unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
971   BuildMI(StoreBB, DL, TII->get(CMPri))
972       .addReg(StatusReg, getKillRegState(StatusDead))
973       .addImm(0)
974       .add(predOps(ARMCC::AL));
975   BuildMI(StoreBB, DL, TII->get(Bcc))
976       .addMBB(LoadCmpBB)
977       .addImm(ARMCC::NE)
978       .addReg(ARM::CPSR, RegState::Kill);
979   StoreBB->addSuccessor(LoadCmpBB);
980   StoreBB->addSuccessor(DoneBB);
981 
982   DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
983   DoneBB->transferSuccessors(&MBB);
984 
985   MBB.addSuccessor(LoadCmpBB);
986 
987   NextMBBI = MBB.end();
988   MI.eraseFromParent();
989 
990   // Recompute livein lists.
991   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
992   LivePhysRegs LiveRegs;
993   computeLiveIns(LiveRegs, MRI, *DoneBB);
994   computeLiveIns(LiveRegs, MRI, *StoreBB);
995   computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
996   // Do an extra pass around the loop to get loop carried registers right.
997   StoreBB->clearLiveIns();
998   computeLiveIns(LiveRegs, MRI, *StoreBB);
999   LoadCmpBB->clearLiveIns();
1000   computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
1001 
1002   return true;
1003 }
1004 
1005 
1006 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
1007                                MachineBasicBlock::iterator MBBI,
1008                                MachineBasicBlock::iterator &NextMBBI) {
1009   MachineInstr &MI = *MBBI;
1010   unsigned Opcode = MI.getOpcode();
1011   switch (Opcode) {
1012     default:
1013       return false;
1014 
1015     case ARM::TCRETURNdi:
1016     case ARM::TCRETURNri: {
1017       MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
1018       assert(MBBI->isReturn() &&
1019              "Can only insert epilog into returning blocks");
1020       unsigned RetOpcode = MBBI->getOpcode();
1021       DebugLoc dl = MBBI->getDebugLoc();
1022       const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
1023           MBB.getParent()->getSubtarget().getInstrInfo());
1024 
1025       // Tail call return: adjust the stack pointer and jump to callee.
1026       MBBI = MBB.getLastNonDebugInstr();
1027       MachineOperand &JumpTarget = MBBI->getOperand(0);
1028 
1029       // Jump to label or value in register.
1030       if (RetOpcode == ARM::TCRETURNdi) {
1031         unsigned TCOpcode =
1032             STI->isThumb()
1033                 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND)
1034                 : ARM::TAILJMPd;
1035         MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
1036         if (JumpTarget.isGlobal())
1037           MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1038                                JumpTarget.getTargetFlags());
1039         else {
1040           assert(JumpTarget.isSymbol());
1041           MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1042                                 JumpTarget.getTargetFlags());
1043         }
1044 
1045         // Add the default predicate in Thumb mode.
1046         if (STI->isThumb())
1047           MIB.add(predOps(ARMCC::AL));
1048       } else if (RetOpcode == ARM::TCRETURNri) {
1049         BuildMI(MBB, MBBI, dl,
1050                 TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr))
1051             .addReg(JumpTarget.getReg(), RegState::Kill);
1052       }
1053 
1054       auto NewMI = std::prev(MBBI);
1055       for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1056         NewMI->addOperand(MBBI->getOperand(i));
1057 
1058       // Delete the pseudo instruction TCRETURN.
1059       MBB.erase(MBBI);
1060       MBBI = NewMI;
1061       return true;
1062     }
1063     case ARM::VMOVScc:
1064     case ARM::VMOVDcc: {
1065       unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
1066       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
1067               MI.getOperand(1).getReg())
1068           .add(MI.getOperand(2))
1069           .addImm(MI.getOperand(3).getImm()) // 'pred'
1070           .add(MI.getOperand(4));
1071 
1072       MI.eraseFromParent();
1073       return true;
1074     }
1075     case ARM::t2MOVCCr:
1076     case ARM::MOVCCr: {
1077       unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
1078       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1079               MI.getOperand(1).getReg())
1080           .add(MI.getOperand(2))
1081           .addImm(MI.getOperand(3).getImm()) // 'pred'
1082           .add(MI.getOperand(4))
1083           .add(condCodeOp()); // 's' bit
1084 
1085       MI.eraseFromParent();
1086       return true;
1087     }
1088     case ARM::MOVCCsi: {
1089       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1090               (MI.getOperand(1).getReg()))
1091           .add(MI.getOperand(2))
1092           .addImm(MI.getOperand(3).getImm())
1093           .addImm(MI.getOperand(4).getImm()) // 'pred'
1094           .add(MI.getOperand(5))
1095           .add(condCodeOp()); // 's' bit
1096 
1097       MI.eraseFromParent();
1098       return true;
1099     }
1100     case ARM::MOVCCsr: {
1101       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
1102               (MI.getOperand(1).getReg()))
1103           .add(MI.getOperand(2))
1104           .add(MI.getOperand(3))
1105           .addImm(MI.getOperand(4).getImm())
1106           .addImm(MI.getOperand(5).getImm()) // 'pred'
1107           .add(MI.getOperand(6))
1108           .add(condCodeOp()); // 's' bit
1109 
1110       MI.eraseFromParent();
1111       return true;
1112     }
1113     case ARM::t2MOVCCi16:
1114     case ARM::MOVCCi16: {
1115       unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
1116       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1117               MI.getOperand(1).getReg())
1118           .addImm(MI.getOperand(2).getImm())
1119           .addImm(MI.getOperand(3).getImm()) // 'pred'
1120           .add(MI.getOperand(4));
1121       MI.eraseFromParent();
1122       return true;
1123     }
1124     case ARM::t2MOVCCi:
1125     case ARM::MOVCCi: {
1126       unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
1127       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1128               MI.getOperand(1).getReg())
1129           .addImm(MI.getOperand(2).getImm())
1130           .addImm(MI.getOperand(3).getImm()) // 'pred'
1131           .add(MI.getOperand(4))
1132           .add(condCodeOp()); // 's' bit
1133 
1134       MI.eraseFromParent();
1135       return true;
1136     }
1137     case ARM::t2MVNCCi:
1138     case ARM::MVNCCi: {
1139       unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
1140       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1141               MI.getOperand(1).getReg())
1142           .addImm(MI.getOperand(2).getImm())
1143           .addImm(MI.getOperand(3).getImm()) // 'pred'
1144           .add(MI.getOperand(4))
1145           .add(condCodeOp()); // 's' bit
1146 
1147       MI.eraseFromParent();
1148       return true;
1149     }
1150     case ARM::t2MOVCClsl:
1151     case ARM::t2MOVCClsr:
1152     case ARM::t2MOVCCasr:
1153     case ARM::t2MOVCCror: {
1154       unsigned NewOpc;
1155       switch (Opcode) {
1156       case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
1157       case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
1158       case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
1159       case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
1160       default: llvm_unreachable("unexpeced conditional move");
1161       }
1162       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1163               MI.getOperand(1).getReg())
1164           .add(MI.getOperand(2))
1165           .addImm(MI.getOperand(3).getImm())
1166           .addImm(MI.getOperand(4).getImm()) // 'pred'
1167           .add(MI.getOperand(5))
1168           .add(condCodeOp()); // 's' bit
1169       MI.eraseFromParent();
1170       return true;
1171     }
1172     case ARM::Int_eh_sjlj_dispatchsetup: {
1173       MachineFunction &MF = *MI.getParent()->getParent();
1174       const ARMBaseInstrInfo *AII =
1175         static_cast<const ARMBaseInstrInfo*>(TII);
1176       const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
1177       // For functions using a base pointer, we rematerialize it (via the frame
1178       // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
1179       // for us. Otherwise, expand to nothing.
1180       if (RI.hasBasePointer(MF)) {
1181         int32_t NumBytes = AFI->getFramePtrSpillOffset();
1182         unsigned FramePtr = RI.getFrameRegister(MF);
1183         assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
1184                "base pointer without frame pointer?");
1185 
1186         if (AFI->isThumb2Function()) {
1187           emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1188                                  FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
1189         } else if (AFI->isThumbFunction()) {
1190           emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1191                                     FramePtr, -NumBytes, *TII, RI);
1192         } else {
1193           emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1194                                   FramePtr, -NumBytes, ARMCC::AL, 0,
1195                                   *TII);
1196         }
1197         // If there's dynamic realignment, adjust for it.
1198         if (RI.needsStackRealignment(MF)) {
1199           MachineFrameInfo &MFI = MF.getFrameInfo();
1200           unsigned MaxAlign = MFI.getMaxAlignment();
1201           assert (!AFI->isThumb1OnlyFunction());
1202           // Emit bic r6, r6, MaxAlign
1203           assert(MaxAlign <= 256 && "The BIC instruction cannot encode "
1204                                     "immediates larger than 256 with all lower "
1205                                     "bits set.");
1206           unsigned bicOpc = AFI->isThumbFunction() ?
1207             ARM::t2BICri : ARM::BICri;
1208           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
1209               .addReg(ARM::R6, RegState::Kill)
1210               .addImm(MaxAlign - 1)
1211               .add(predOps(ARMCC::AL))
1212               .add(condCodeOp());
1213         }
1214 
1215       }
1216       MI.eraseFromParent();
1217       return true;
1218     }
1219 
1220     case ARM::MOVsrl_flag:
1221     case ARM::MOVsra_flag: {
1222       // These are just fancy MOVs instructions.
1223       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1224               MI.getOperand(0).getReg())
1225           .add(MI.getOperand(1))
1226           .addImm(ARM_AM::getSORegOpc(
1227               (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1))
1228           .add(predOps(ARMCC::AL))
1229           .addReg(ARM::CPSR, RegState::Define);
1230       MI.eraseFromParent();
1231       return true;
1232     }
1233     case ARM::RRX: {
1234       // This encodes as "MOVs Rd, Rm, rrx
1235       MachineInstrBuilder MIB =
1236           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1237                   MI.getOperand(0).getReg())
1238               .add(MI.getOperand(1))
1239               .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))
1240               .add(predOps(ARMCC::AL))
1241               .add(condCodeOp());
1242       TransferImpOps(MI, MIB, MIB);
1243       MI.eraseFromParent();
1244       return true;
1245     }
1246     case ARM::tTPsoft:
1247     case ARM::TPsoft: {
1248       const bool Thumb = Opcode == ARM::tTPsoft;
1249 
1250       MachineInstrBuilder MIB;
1251       if (STI->genLongCalls()) {
1252         MachineFunction *MF = MBB.getParent();
1253         MachineConstantPool *MCP = MF->getConstantPool();
1254         unsigned PCLabelID = AFI->createPICLabelUId();
1255         MachineConstantPoolValue *CPV =
1256             ARMConstantPoolSymbol::Create(MF->getFunction()->getContext(),
1257                                           "__aeabi_read_tp", PCLabelID, 0);
1258         unsigned Reg = MI.getOperand(0).getReg();
1259         MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1260                       TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
1261                   .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1262         if (!Thumb)
1263           MIB.addImm(0);
1264         MIB.add(predOps(ARMCC::AL));
1265 
1266         MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1267                       TII->get(Thumb ? ARM::tBLXr : ARM::BLX));
1268         if (Thumb)
1269           MIB.add(predOps(ARMCC::AL));
1270         MIB.addReg(Reg, RegState::Kill);
1271       } else {
1272         MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1273                       TII->get(Thumb ? ARM::tBL : ARM::BL));
1274         if (Thumb)
1275           MIB.add(predOps(ARMCC::AL));
1276         MIB.addExternalSymbol("__aeabi_read_tp", 0);
1277       }
1278 
1279       MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1280       TransferImpOps(MI, MIB, MIB);
1281       MI.eraseFromParent();
1282       return true;
1283     }
1284     case ARM::tLDRpci_pic:
1285     case ARM::t2LDRpci_pic: {
1286       unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
1287         ? ARM::tLDRpci : ARM::t2LDRpci;
1288       unsigned DstReg = MI.getOperand(0).getReg();
1289       bool DstIsDead = MI.getOperand(0).isDead();
1290       MachineInstrBuilder MIB1 =
1291           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg)
1292               .add(MI.getOperand(1))
1293               .add(predOps(ARMCC::AL));
1294       MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1295       MachineInstrBuilder MIB2 =
1296           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
1297               .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1298               .addReg(DstReg)
1299               .add(MI.getOperand(2));
1300       TransferImpOps(MI, MIB1, MIB2);
1301       MI.eraseFromParent();
1302       return true;
1303     }
1304 
1305     case ARM::LDRLIT_ga_abs:
1306     case ARM::LDRLIT_ga_pcrel:
1307     case ARM::LDRLIT_ga_pcrel_ldr:
1308     case ARM::tLDRLIT_ga_abs:
1309     case ARM::tLDRLIT_ga_pcrel: {
1310       unsigned DstReg = MI.getOperand(0).getReg();
1311       bool DstIsDead = MI.getOperand(0).isDead();
1312       const MachineOperand &MO1 = MI.getOperand(1);
1313       const GlobalValue *GV = MO1.getGlobal();
1314       bool IsARM =
1315           Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
1316       bool IsPIC =
1317           Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
1318       unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
1319       unsigned PICAddOpc =
1320           IsARM
1321               ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1322               : ARM::tPICADD;
1323 
1324       // We need a new const-pool entry to load from.
1325       MachineConstantPool *MCP = MBB.getParent()->getConstantPool();
1326       unsigned ARMPCLabelIndex = 0;
1327       MachineConstantPoolValue *CPV;
1328 
1329       if (IsPIC) {
1330         unsigned PCAdj = IsARM ? 8 : 4;
1331         ARMPCLabelIndex = AFI->createPICLabelUId();
1332         CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex,
1333                                               ARMCP::CPValue, PCAdj);
1334       } else
1335         CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier);
1336 
1337       MachineInstrBuilder MIB =
1338           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
1339             .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1340       if (IsARM)
1341         MIB.addImm(0);
1342       MIB.add(predOps(ARMCC::AL));
1343 
1344       if (IsPIC) {
1345         MachineInstrBuilder MIB =
1346           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
1347             .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1348             .addReg(DstReg)
1349             .addImm(ARMPCLabelIndex);
1350 
1351         if (IsARM)
1352           MIB.add(predOps(ARMCC::AL));
1353       }
1354 
1355       MI.eraseFromParent();
1356       return true;
1357     }
1358     case ARM::MOV_ga_pcrel:
1359     case ARM::MOV_ga_pcrel_ldr:
1360     case ARM::t2MOV_ga_pcrel: {
1361       // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
1362       unsigned LabelId = AFI->createPICLabelUId();
1363       unsigned DstReg = MI.getOperand(0).getReg();
1364       bool DstIsDead = MI.getOperand(0).isDead();
1365       const MachineOperand &MO1 = MI.getOperand(1);
1366       const GlobalValue *GV = MO1.getGlobal();
1367       unsigned TF = MO1.getTargetFlags();
1368       bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
1369       unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
1370       unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
1371       unsigned LO16TF = TF | ARMII::MO_LO16;
1372       unsigned HI16TF = TF | ARMII::MO_HI16;
1373       unsigned PICAddOpc = isARM
1374         ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1375         : ARM::tPICADD;
1376       MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1377                                          TII->get(LO16Opc), DstReg)
1378         .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
1379         .addImm(LabelId);
1380 
1381       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
1382         .addReg(DstReg)
1383         .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
1384         .addImm(LabelId);
1385 
1386       MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1387                                          TII->get(PICAddOpc))
1388         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1389         .addReg(DstReg).addImm(LabelId);
1390       if (isARM) {
1391         MIB3.add(predOps(ARMCC::AL));
1392         if (Opcode == ARM::MOV_ga_pcrel_ldr)
1393           MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1394       }
1395       TransferImpOps(MI, MIB1, MIB3);
1396       MI.eraseFromParent();
1397       return true;
1398     }
1399 
1400     case ARM::MOVi32imm:
1401     case ARM::MOVCCi32imm:
1402     case ARM::t2MOVi32imm:
1403     case ARM::t2MOVCCi32imm:
1404       ExpandMOV32BitImm(MBB, MBBI);
1405       return true;
1406 
1407     case ARM::SUBS_PC_LR: {
1408       MachineInstrBuilder MIB =
1409           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1410               .addReg(ARM::LR)
1411               .add(MI.getOperand(0))
1412               .add(MI.getOperand(1))
1413               .add(MI.getOperand(2))
1414               .addReg(ARM::CPSR, RegState::Undef);
1415       TransferImpOps(MI, MIB, MIB);
1416       MI.eraseFromParent();
1417       return true;
1418     }
1419     case ARM::VLDMQIA: {
1420       unsigned NewOpc = ARM::VLDMDIA;
1421       MachineInstrBuilder MIB =
1422         BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1423       unsigned OpIdx = 0;
1424 
1425       // Grab the Q register destination.
1426       bool DstIsDead = MI.getOperand(OpIdx).isDead();
1427       unsigned DstReg = MI.getOperand(OpIdx++).getReg();
1428 
1429       // Copy the source register.
1430       MIB.add(MI.getOperand(OpIdx++));
1431 
1432       // Copy the predicate operands.
1433       MIB.add(MI.getOperand(OpIdx++));
1434       MIB.add(MI.getOperand(OpIdx++));
1435 
1436       // Add the destination operands (D subregs).
1437       unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1438       unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1439       MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1440         .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1441 
1442       // Add an implicit def for the super-register.
1443       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1444       TransferImpOps(MI, MIB, MIB);
1445       MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1446       MI.eraseFromParent();
1447       return true;
1448     }
1449 
1450     case ARM::VSTMQIA: {
1451       unsigned NewOpc = ARM::VSTMDIA;
1452       MachineInstrBuilder MIB =
1453         BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1454       unsigned OpIdx = 0;
1455 
1456       // Grab the Q register source.
1457       bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1458       unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1459 
1460       // Copy the destination register.
1461       MIB.add(MI.getOperand(OpIdx++));
1462 
1463       // Copy the predicate operands.
1464       MIB.add(MI.getOperand(OpIdx++));
1465       MIB.add(MI.getOperand(OpIdx++));
1466 
1467       // Add the source operands (D subregs).
1468       unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1469       unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1470       MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
1471          .addReg(D1, SrcIsKill ? RegState::Kill : 0);
1472 
1473       if (SrcIsKill)      // Add an implicit kill for the Q register.
1474         MIB->addRegisterKilled(SrcReg, TRI, true);
1475 
1476       TransferImpOps(MI, MIB, MIB);
1477       MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1478       MI.eraseFromParent();
1479       return true;
1480     }
1481 
1482     case ARM::VLD2q8Pseudo:
1483     case ARM::VLD2q16Pseudo:
1484     case ARM::VLD2q32Pseudo:
1485     case ARM::VLD2q8PseudoWB_fixed:
1486     case ARM::VLD2q16PseudoWB_fixed:
1487     case ARM::VLD2q32PseudoWB_fixed:
1488     case ARM::VLD2q8PseudoWB_register:
1489     case ARM::VLD2q16PseudoWB_register:
1490     case ARM::VLD2q32PseudoWB_register:
1491     case ARM::VLD3d8Pseudo:
1492     case ARM::VLD3d16Pseudo:
1493     case ARM::VLD3d32Pseudo:
1494     case ARM::VLD1d64TPseudo:
1495     case ARM::VLD1d64TPseudoWB_fixed:
1496     case ARM::VLD3d8Pseudo_UPD:
1497     case ARM::VLD3d16Pseudo_UPD:
1498     case ARM::VLD3d32Pseudo_UPD:
1499     case ARM::VLD3q8Pseudo_UPD:
1500     case ARM::VLD3q16Pseudo_UPD:
1501     case ARM::VLD3q32Pseudo_UPD:
1502     case ARM::VLD3q8oddPseudo:
1503     case ARM::VLD3q16oddPseudo:
1504     case ARM::VLD3q32oddPseudo:
1505     case ARM::VLD3q8oddPseudo_UPD:
1506     case ARM::VLD3q16oddPseudo_UPD:
1507     case ARM::VLD3q32oddPseudo_UPD:
1508     case ARM::VLD4d8Pseudo:
1509     case ARM::VLD4d16Pseudo:
1510     case ARM::VLD4d32Pseudo:
1511     case ARM::VLD1d64QPseudo:
1512     case ARM::VLD1d64QPseudoWB_fixed:
1513     case ARM::VLD4d8Pseudo_UPD:
1514     case ARM::VLD4d16Pseudo_UPD:
1515     case ARM::VLD4d32Pseudo_UPD:
1516     case ARM::VLD4q8Pseudo_UPD:
1517     case ARM::VLD4q16Pseudo_UPD:
1518     case ARM::VLD4q32Pseudo_UPD:
1519     case ARM::VLD4q8oddPseudo:
1520     case ARM::VLD4q16oddPseudo:
1521     case ARM::VLD4q32oddPseudo:
1522     case ARM::VLD4q8oddPseudo_UPD:
1523     case ARM::VLD4q16oddPseudo_UPD:
1524     case ARM::VLD4q32oddPseudo_UPD:
1525     case ARM::VLD3DUPd8Pseudo:
1526     case ARM::VLD3DUPd16Pseudo:
1527     case ARM::VLD3DUPd32Pseudo:
1528     case ARM::VLD3DUPd8Pseudo_UPD:
1529     case ARM::VLD3DUPd16Pseudo_UPD:
1530     case ARM::VLD3DUPd32Pseudo_UPD:
1531     case ARM::VLD4DUPd8Pseudo:
1532     case ARM::VLD4DUPd16Pseudo:
1533     case ARM::VLD4DUPd32Pseudo:
1534     case ARM::VLD4DUPd8Pseudo_UPD:
1535     case ARM::VLD4DUPd16Pseudo_UPD:
1536     case ARM::VLD4DUPd32Pseudo_UPD:
1537       ExpandVLD(MBBI);
1538       return true;
1539 
1540     case ARM::VST2q8Pseudo:
1541     case ARM::VST2q16Pseudo:
1542     case ARM::VST2q32Pseudo:
1543     case ARM::VST2q8PseudoWB_fixed:
1544     case ARM::VST2q16PseudoWB_fixed:
1545     case ARM::VST2q32PseudoWB_fixed:
1546     case ARM::VST2q8PseudoWB_register:
1547     case ARM::VST2q16PseudoWB_register:
1548     case ARM::VST2q32PseudoWB_register:
1549     case ARM::VST3d8Pseudo:
1550     case ARM::VST3d16Pseudo:
1551     case ARM::VST3d32Pseudo:
1552     case ARM::VST1d64TPseudo:
1553     case ARM::VST3d8Pseudo_UPD:
1554     case ARM::VST3d16Pseudo_UPD:
1555     case ARM::VST3d32Pseudo_UPD:
1556     case ARM::VST1d64TPseudoWB_fixed:
1557     case ARM::VST1d64TPseudoWB_register:
1558     case ARM::VST3q8Pseudo_UPD:
1559     case ARM::VST3q16Pseudo_UPD:
1560     case ARM::VST3q32Pseudo_UPD:
1561     case ARM::VST3q8oddPseudo:
1562     case ARM::VST3q16oddPseudo:
1563     case ARM::VST3q32oddPseudo:
1564     case ARM::VST3q8oddPseudo_UPD:
1565     case ARM::VST3q16oddPseudo_UPD:
1566     case ARM::VST3q32oddPseudo_UPD:
1567     case ARM::VST4d8Pseudo:
1568     case ARM::VST4d16Pseudo:
1569     case ARM::VST4d32Pseudo:
1570     case ARM::VST1d64QPseudo:
1571     case ARM::VST4d8Pseudo_UPD:
1572     case ARM::VST4d16Pseudo_UPD:
1573     case ARM::VST4d32Pseudo_UPD:
1574     case ARM::VST1d64QPseudoWB_fixed:
1575     case ARM::VST1d64QPseudoWB_register:
1576     case ARM::VST4q8Pseudo_UPD:
1577     case ARM::VST4q16Pseudo_UPD:
1578     case ARM::VST4q32Pseudo_UPD:
1579     case ARM::VST4q8oddPseudo:
1580     case ARM::VST4q16oddPseudo:
1581     case ARM::VST4q32oddPseudo:
1582     case ARM::VST4q8oddPseudo_UPD:
1583     case ARM::VST4q16oddPseudo_UPD:
1584     case ARM::VST4q32oddPseudo_UPD:
1585       ExpandVST(MBBI);
1586       return true;
1587 
1588     case ARM::VLD1LNq8Pseudo:
1589     case ARM::VLD1LNq16Pseudo:
1590     case ARM::VLD1LNq32Pseudo:
1591     case ARM::VLD1LNq8Pseudo_UPD:
1592     case ARM::VLD1LNq16Pseudo_UPD:
1593     case ARM::VLD1LNq32Pseudo_UPD:
1594     case ARM::VLD2LNd8Pseudo:
1595     case ARM::VLD2LNd16Pseudo:
1596     case ARM::VLD2LNd32Pseudo:
1597     case ARM::VLD2LNq16Pseudo:
1598     case ARM::VLD2LNq32Pseudo:
1599     case ARM::VLD2LNd8Pseudo_UPD:
1600     case ARM::VLD2LNd16Pseudo_UPD:
1601     case ARM::VLD2LNd32Pseudo_UPD:
1602     case ARM::VLD2LNq16Pseudo_UPD:
1603     case ARM::VLD2LNq32Pseudo_UPD:
1604     case ARM::VLD3LNd8Pseudo:
1605     case ARM::VLD3LNd16Pseudo:
1606     case ARM::VLD3LNd32Pseudo:
1607     case ARM::VLD3LNq16Pseudo:
1608     case ARM::VLD3LNq32Pseudo:
1609     case ARM::VLD3LNd8Pseudo_UPD:
1610     case ARM::VLD3LNd16Pseudo_UPD:
1611     case ARM::VLD3LNd32Pseudo_UPD:
1612     case ARM::VLD3LNq16Pseudo_UPD:
1613     case ARM::VLD3LNq32Pseudo_UPD:
1614     case ARM::VLD4LNd8Pseudo:
1615     case ARM::VLD4LNd16Pseudo:
1616     case ARM::VLD4LNd32Pseudo:
1617     case ARM::VLD4LNq16Pseudo:
1618     case ARM::VLD4LNq32Pseudo:
1619     case ARM::VLD4LNd8Pseudo_UPD:
1620     case ARM::VLD4LNd16Pseudo_UPD:
1621     case ARM::VLD4LNd32Pseudo_UPD:
1622     case ARM::VLD4LNq16Pseudo_UPD:
1623     case ARM::VLD4LNq32Pseudo_UPD:
1624     case ARM::VST1LNq8Pseudo:
1625     case ARM::VST1LNq16Pseudo:
1626     case ARM::VST1LNq32Pseudo:
1627     case ARM::VST1LNq8Pseudo_UPD:
1628     case ARM::VST1LNq16Pseudo_UPD:
1629     case ARM::VST1LNq32Pseudo_UPD:
1630     case ARM::VST2LNd8Pseudo:
1631     case ARM::VST2LNd16Pseudo:
1632     case ARM::VST2LNd32Pseudo:
1633     case ARM::VST2LNq16Pseudo:
1634     case ARM::VST2LNq32Pseudo:
1635     case ARM::VST2LNd8Pseudo_UPD:
1636     case ARM::VST2LNd16Pseudo_UPD:
1637     case ARM::VST2LNd32Pseudo_UPD:
1638     case ARM::VST2LNq16Pseudo_UPD:
1639     case ARM::VST2LNq32Pseudo_UPD:
1640     case ARM::VST3LNd8Pseudo:
1641     case ARM::VST3LNd16Pseudo:
1642     case ARM::VST3LNd32Pseudo:
1643     case ARM::VST3LNq16Pseudo:
1644     case ARM::VST3LNq32Pseudo:
1645     case ARM::VST3LNd8Pseudo_UPD:
1646     case ARM::VST3LNd16Pseudo_UPD:
1647     case ARM::VST3LNd32Pseudo_UPD:
1648     case ARM::VST3LNq16Pseudo_UPD:
1649     case ARM::VST3LNq32Pseudo_UPD:
1650     case ARM::VST4LNd8Pseudo:
1651     case ARM::VST4LNd16Pseudo:
1652     case ARM::VST4LNd32Pseudo:
1653     case ARM::VST4LNq16Pseudo:
1654     case ARM::VST4LNq32Pseudo:
1655     case ARM::VST4LNd8Pseudo_UPD:
1656     case ARM::VST4LNd16Pseudo_UPD:
1657     case ARM::VST4LNd32Pseudo_UPD:
1658     case ARM::VST4LNq16Pseudo_UPD:
1659     case ARM::VST4LNq32Pseudo_UPD:
1660       ExpandLaneOp(MBBI);
1661       return true;
1662 
1663     case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1664     case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1665     case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1666     case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1667 
1668     case ARM::CMP_SWAP_8:
1669       if (STI->isThumb())
1670         return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB,
1671                               ARM::tUXTB, NextMBBI);
1672       else
1673         return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB,
1674                               ARM::UXTB, NextMBBI);
1675     case ARM::CMP_SWAP_16:
1676       if (STI->isThumb())
1677         return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH,
1678                               ARM::tUXTH, NextMBBI);
1679       else
1680         return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH,
1681                               ARM::UXTH, NextMBBI);
1682     case ARM::CMP_SWAP_32:
1683       if (STI->isThumb())
1684         return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0,
1685                               NextMBBI);
1686       else
1687         return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
1688 
1689     case ARM::CMP_SWAP_64:
1690       return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
1691   }
1692 }
1693 
1694 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1695   bool Modified = false;
1696 
1697   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1698   while (MBBI != E) {
1699     MachineBasicBlock::iterator NMBBI = std::next(MBBI);
1700     Modified |= ExpandMI(MBB, MBBI, NMBBI);
1701     MBBI = NMBBI;
1702   }
1703 
1704   return Modified;
1705 }
1706 
1707 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1708   STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
1709   TII = STI->getInstrInfo();
1710   TRI = STI->getRegisterInfo();
1711   AFI = MF.getInfo<ARMFunctionInfo>();
1712 
1713   bool Modified = false;
1714   for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1715        ++MFI)
1716     Modified |= ExpandMBB(*MFI);
1717   if (VerifyARMPseudo)
1718     MF.verify(this, "After expanding ARM pseudo instructions.");
1719   return Modified;
1720 }
1721 
1722 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1723 /// expansion pass.
1724 FunctionPass *llvm::createARMExpandPseudoPass() {
1725   return new ARMExpandPseudo();
1726 }
1727