1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains a pass that expands pseudo instructions into target 10 // instructions to allow proper scheduling, if-conversion, and other late 11 // optimizations. This pass should be run after register allocation but before 12 // the post-regalloc scheduling pass. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "ARM.h" 17 #include "ARMBaseInstrInfo.h" 18 #include "ARMBaseRegisterInfo.h" 19 #include "ARMConstantPoolValue.h" 20 #include "ARMMachineFunctionInfo.h" 21 #include "ARMSubtarget.h" 22 #include "MCTargetDesc/ARMAddressingModes.h" 23 #include "llvm/CodeGen/LivePhysRegs.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunctionPass.h" 26 #include "llvm/Support/Debug.h" 27 28 using namespace llvm; 29 30 #define DEBUG_TYPE "arm-pseudo" 31 32 static cl::opt<bool> 33 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, 34 cl::desc("Verify machine code after expanding ARM pseudos")); 35 36 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass" 37 38 namespace { 39 class ARMExpandPseudo : public MachineFunctionPass { 40 public: 41 static char ID; 42 ARMExpandPseudo() : MachineFunctionPass(ID) {} 43 44 const ARMBaseInstrInfo *TII; 45 const TargetRegisterInfo *TRI; 46 const ARMSubtarget *STI; 47 ARMFunctionInfo *AFI; 48 49 bool runOnMachineFunction(MachineFunction &Fn) override; 50 51 MachineFunctionProperties getRequiredProperties() const override { 52 return MachineFunctionProperties().set( 53 MachineFunctionProperties::Property::NoVRegs); 54 } 55 56 StringRef getPassName() const override { 57 return ARM_EXPAND_PSEUDO_NAME; 58 } 59 60 private: 61 void TransferImpOps(MachineInstr &OldMI, 62 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 63 bool ExpandMI(MachineBasicBlock &MBB, 64 MachineBasicBlock::iterator MBBI, 65 MachineBasicBlock::iterator &NextMBBI); 66 bool ExpandMBB(MachineBasicBlock &MBB); 67 void ExpandVLD(MachineBasicBlock::iterator &MBBI); 68 void ExpandVST(MachineBasicBlock::iterator &MBBI); 69 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 70 void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 71 unsigned Opc, bool IsExt); 72 void ExpandMOV32BitImm(MachineBasicBlock &MBB, 73 MachineBasicBlock::iterator &MBBI); 74 bool ExpandCMP_SWAP(MachineBasicBlock &MBB, 75 MachineBasicBlock::iterator MBBI, unsigned LdrexOp, 76 unsigned StrexOp, unsigned UxtOp, 77 MachineBasicBlock::iterator &NextMBBI); 78 79 bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB, 80 MachineBasicBlock::iterator MBBI, 81 MachineBasicBlock::iterator &NextMBBI); 82 }; 83 char ARMExpandPseudo::ID = 0; 84 } 85 86 INITIALIZE_PASS(ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false, 87 false) 88 89 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to 90 /// the instructions created from the expansion. 91 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 92 MachineInstrBuilder &UseMI, 93 MachineInstrBuilder &DefMI) { 94 const MCInstrDesc &Desc = OldMI.getDesc(); 95 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); 96 i != e; ++i) { 97 const MachineOperand &MO = OldMI.getOperand(i); 98 assert(MO.isReg() && MO.getReg()); 99 if (MO.isUse()) 100 UseMI.add(MO); 101 else 102 DefMI.add(MO); 103 } 104 } 105 106 namespace { 107 // Constants for register spacing in NEON load/store instructions. 108 // For quad-register load-lane and store-lane pseudo instructors, the 109 // spacing is initially assumed to be EvenDblSpc, and that is changed to 110 // OddDblSpc depending on the lane number operand. 111 enum NEONRegSpacing { 112 SingleSpc, 113 SingleLowSpc , // Single spacing, low registers, three and four vectors. 114 SingleHighQSpc, // Single spacing, high registers, four vectors. 115 SingleHighTSpc, // Single spacing, high registers, three vectors. 116 EvenDblSpc, 117 OddDblSpc 118 }; 119 120 // Entries for NEON load/store information table. The table is sorted by 121 // PseudoOpc for fast binary-search lookups. 122 struct NEONLdStTableEntry { 123 uint16_t PseudoOpc; 124 uint16_t RealOpc; 125 bool IsLoad; 126 bool isUpdating; 127 bool hasWritebackOperand; 128 uint8_t RegSpacing; // One of type NEONRegSpacing 129 uint8_t NumRegs; // D registers loaded or stored 130 uint8_t RegElts; // elements per D register; used for lane ops 131 // FIXME: Temporary flag to denote whether the real instruction takes 132 // a single register (like the encoding) or all of the registers in 133 // the list (like the asm syntax and the isel DAG). When all definitions 134 // are converted to take only the single encoded register, this will 135 // go away. 136 bool copyAllListRegs; 137 138 // Comparison methods for binary search of the table. 139 bool operator<(const NEONLdStTableEntry &TE) const { 140 return PseudoOpc < TE.PseudoOpc; 141 } 142 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 143 return TE.PseudoOpc < PseudoOpc; 144 } 145 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 146 const NEONLdStTableEntry &TE) { 147 return PseudoOpc < TE.PseudoOpc; 148 } 149 }; 150 } 151 152 static const NEONLdStTableEntry NEONLdStTable[] = { 153 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true}, 154 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true}, 155 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}, 156 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true}, 157 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true}, 158 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true}, 159 160 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false}, 161 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false}, 162 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false}, 163 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false}, 164 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false}, 165 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false}, 166 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 ,false}, 167 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false}, 168 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false}, 169 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,false}, 170 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false}, 171 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false}, 172 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false}, 173 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false}, 174 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,false}, 175 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,false}, 176 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false}, 177 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false}, 178 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,false}, 179 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,false}, 180 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false}, 181 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false}, 182 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,false}, 183 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,false}, 184 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false}, 185 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false}, 186 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false}, 187 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false}, 188 189 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false}, 190 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false}, 191 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false}, 192 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false}, 193 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false}, 194 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false}, 195 196 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, 197 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true}, 198 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true}, 199 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true}, 200 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true}, 201 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true}, 202 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true}, 203 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true}, 204 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true}, 205 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true}, 206 207 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false}, 208 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false}, 209 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false}, 210 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false}, 211 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false}, 212 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false}, 213 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false}, 214 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false}, 215 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false}, 216 217 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true}, 218 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true}, 219 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true}, 220 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true}, 221 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true}, 222 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true}, 223 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 224 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true}, 225 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 226 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true}, 227 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true}, 228 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true}, 229 230 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true}, 231 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 232 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true}, 233 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 234 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true}, 235 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 236 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 237 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 238 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 239 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 240 241 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true}, 242 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 243 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true}, 244 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 245 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true}, 246 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 247 248 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 249 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true}, 250 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true}, 251 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 252 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true}, 253 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true}, 254 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true}, 255 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true}, 256 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true}, 257 258 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true}, 259 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true}, 260 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true}, 261 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true}, 262 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true}, 263 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true}, 264 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 265 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true}, 266 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 267 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true}, 268 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true}, 269 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true}, 270 271 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true}, 272 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 273 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true}, 274 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 275 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true}, 276 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 277 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 278 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 279 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 280 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 281 282 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true}, 283 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 284 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true}, 285 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 286 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true}, 287 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 288 289 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 290 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true}, 291 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true}, 292 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 293 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true}, 294 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true}, 295 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true}, 296 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true}, 297 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true}, 298 299 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true}, 300 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true}, 301 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true}, 302 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true}, 303 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true}, 304 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true}, 305 306 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false}, 307 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false}, 308 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false}, 309 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false}, 310 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false}, 311 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false}, 312 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false}, 313 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false}, 314 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false}, 315 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false}, 316 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false}, 317 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false}, 318 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false}, 319 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false}, 320 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,false}, 321 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,false}, 322 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false}, 323 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false}, 324 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,false}, 325 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,false}, 326 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false}, 327 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false}, 328 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,false}, 329 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,false}, 330 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false}, 331 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false}, 332 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,false}, 333 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,false}, 334 335 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true}, 336 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true}, 337 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true}, 338 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true}, 339 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true}, 340 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true}, 341 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true}, 342 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true}, 343 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true}, 344 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true}, 345 346 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false}, 347 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false}, 348 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false}, 349 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false}, 350 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false}, 351 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false}, 352 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false}, 353 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false}, 354 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false}, 355 356 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true}, 357 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 358 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true}, 359 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 360 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true}, 361 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 362 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true}, 363 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true}, 364 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true}, 365 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true}, 366 367 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true}, 368 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 369 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true}, 370 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 371 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true}, 372 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 373 374 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true}, 375 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true}, 376 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true}, 377 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true}, 378 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true}, 379 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true}, 380 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true}, 381 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true}, 382 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true}, 383 384 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true}, 385 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 386 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true}, 387 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 388 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true}, 389 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 390 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true}, 391 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true}, 392 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true}, 393 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true}, 394 395 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true}, 396 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 397 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true}, 398 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 399 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true}, 400 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 401 402 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true}, 403 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true}, 404 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true}, 405 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true}, 406 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true}, 407 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true}, 408 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true}, 409 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true}, 410 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true} 411 }; 412 413 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 414 /// load or store pseudo instruction. 415 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 416 #ifndef NDEBUG 417 // Make sure the table is sorted. 418 static std::atomic<bool> TableChecked(false); 419 if (!TableChecked.load(std::memory_order_relaxed)) { 420 assert(llvm::is_sorted(NEONLdStTable) && "NEONLdStTable is not sorted!"); 421 TableChecked.store(true, std::memory_order_relaxed); 422 } 423 #endif 424 425 auto I = llvm::lower_bound(NEONLdStTable, Opcode); 426 if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode) 427 return I; 428 return nullptr; 429 } 430 431 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 432 /// corresponding to the specified register spacing. Not all of the results 433 /// are necessarily valid, e.g., a Q register only has 2 D subregisters. 434 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 435 const TargetRegisterInfo *TRI, unsigned &D0, 436 unsigned &D1, unsigned &D2, unsigned &D3) { 437 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) { 438 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 439 D1 = TRI->getSubReg(Reg, ARM::dsub_1); 440 D2 = TRI->getSubReg(Reg, ARM::dsub_2); 441 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 442 } else if (RegSpc == SingleHighQSpc) { 443 D0 = TRI->getSubReg(Reg, ARM::dsub_4); 444 D1 = TRI->getSubReg(Reg, ARM::dsub_5); 445 D2 = TRI->getSubReg(Reg, ARM::dsub_6); 446 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 447 } else if (RegSpc == SingleHighTSpc) { 448 D0 = TRI->getSubReg(Reg, ARM::dsub_3); 449 D1 = TRI->getSubReg(Reg, ARM::dsub_4); 450 D2 = TRI->getSubReg(Reg, ARM::dsub_5); 451 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 452 } else if (RegSpc == EvenDblSpc) { 453 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 454 D1 = TRI->getSubReg(Reg, ARM::dsub_2); 455 D2 = TRI->getSubReg(Reg, ARM::dsub_4); 456 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 457 } else { 458 assert(RegSpc == OddDblSpc && "unknown register spacing"); 459 D0 = TRI->getSubReg(Reg, ARM::dsub_1); 460 D1 = TRI->getSubReg(Reg, ARM::dsub_3); 461 D2 = TRI->getSubReg(Reg, ARM::dsub_5); 462 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 463 } 464 } 465 466 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 467 /// operands to real VLD instructions with D register operands. 468 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 469 MachineInstr &MI = *MBBI; 470 MachineBasicBlock &MBB = *MI.getParent(); 471 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 472 473 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 474 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 475 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 476 unsigned NumRegs = TableEntry->NumRegs; 477 478 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 479 TII->get(TableEntry->RealOpc)); 480 unsigned OpIdx = 0; 481 482 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 483 Register DstReg = MI.getOperand(OpIdx++).getReg(); 484 if(TableEntry->RealOpc == ARM::VLD2DUPd8x2 || 485 TableEntry->RealOpc == ARM::VLD2DUPd16x2 || 486 TableEntry->RealOpc == ARM::VLD2DUPd32x2) { 487 unsigned SubRegIndex; 488 if (RegSpc == EvenDblSpc) { 489 SubRegIndex = ARM::dsub_0; 490 } else { 491 assert(RegSpc == OddDblSpc && "Unexpected spacing!"); 492 SubRegIndex = ARM::dsub_1; 493 } 494 Register SubReg = TRI->getSubReg(DstReg, SubRegIndex); 495 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0, 496 &ARM::DPairSpcRegClass); 497 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); 498 } else { 499 unsigned D0, D1, D2, D3; 500 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 501 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 502 if (NumRegs > 1 && TableEntry->copyAllListRegs) 503 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 504 if (NumRegs > 2 && TableEntry->copyAllListRegs) 505 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 506 if (NumRegs > 3 && TableEntry->copyAllListRegs) 507 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 508 } 509 510 if (TableEntry->isUpdating) 511 MIB.add(MI.getOperand(OpIdx++)); 512 513 // Copy the addrmode6 operands. 514 MIB.add(MI.getOperand(OpIdx++)); 515 MIB.add(MI.getOperand(OpIdx++)); 516 517 // Copy the am6offset operand. 518 if (TableEntry->hasWritebackOperand) { 519 // TODO: The writing-back pseudo instructions we translate here are all 520 // defined to take am6offset nodes that are capable to represent both fixed 521 // and register forms. Some real instructions, however, do not rely on 522 // am6offset and have separate definitions for such forms. When this is the 523 // case, fixed forms do not take any offset nodes, so here we skip them for 524 // such instructions. Once all real and pseudo writing-back instructions are 525 // rewritten without use of am6offset nodes, this code will go away. 526 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++); 527 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed || 528 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed || 529 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed || 530 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed || 531 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed || 532 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed || 533 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed || 534 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed) { 535 assert(AM6Offset.getReg() == 0 && 536 "A fixed writing-back pseudo instruction provides an offset " 537 "register!"); 538 } else { 539 MIB.add(AM6Offset); 540 } 541 } 542 543 // For an instruction writing double-spaced subregs, the pseudo instruction 544 // has an extra operand that is a use of the super-register. Record the 545 // operand index and skip over it. 546 unsigned SrcOpIdx = 0; 547 if(TableEntry->RealOpc != ARM::VLD2DUPd8x2 && 548 TableEntry->RealOpc != ARM::VLD2DUPd16x2 && 549 TableEntry->RealOpc != ARM::VLD2DUPd32x2) { 550 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc || 551 RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || 552 RegSpc == SingleHighTSpc) 553 SrcOpIdx = OpIdx++; 554 } 555 556 // Copy the predicate operands. 557 MIB.add(MI.getOperand(OpIdx++)); 558 MIB.add(MI.getOperand(OpIdx++)); 559 560 // Copy the super-register source operand used for double-spaced subregs over 561 // to the new instruction as an implicit operand. 562 if (SrcOpIdx != 0) { 563 MachineOperand MO = MI.getOperand(SrcOpIdx); 564 MO.setImplicit(true); 565 MIB.add(MO); 566 } 567 // Add an implicit def for the super-register. 568 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 569 TransferImpOps(MI, MIB, MIB); 570 571 // Transfer memoperands. 572 MIB.cloneMemRefs(MI); 573 MI.eraseFromParent(); 574 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 575 } 576 577 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 578 /// operands to real VST instructions with D register operands. 579 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 580 MachineInstr &MI = *MBBI; 581 MachineBasicBlock &MBB = *MI.getParent(); 582 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 583 584 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 585 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 586 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 587 unsigned NumRegs = TableEntry->NumRegs; 588 589 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 590 TII->get(TableEntry->RealOpc)); 591 unsigned OpIdx = 0; 592 if (TableEntry->isUpdating) 593 MIB.add(MI.getOperand(OpIdx++)); 594 595 // Copy the addrmode6 operands. 596 MIB.add(MI.getOperand(OpIdx++)); 597 MIB.add(MI.getOperand(OpIdx++)); 598 599 if (TableEntry->hasWritebackOperand) { 600 // TODO: The writing-back pseudo instructions we translate here are all 601 // defined to take am6offset nodes that are capable to represent both fixed 602 // and register forms. Some real instructions, however, do not rely on 603 // am6offset and have separate definitions for such forms. When this is the 604 // case, fixed forms do not take any offset nodes, so here we skip them for 605 // such instructions. Once all real and pseudo writing-back instructions are 606 // rewritten without use of am6offset nodes, this code will go away. 607 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++); 608 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed || 609 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed || 610 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed || 611 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed || 612 TableEntry->RealOpc == ARM::VST1d8Twb_fixed || 613 TableEntry->RealOpc == ARM::VST1d16Twb_fixed || 614 TableEntry->RealOpc == ARM::VST1d32Twb_fixed || 615 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) { 616 assert(AM6Offset.getReg() == 0 && 617 "A fixed writing-back pseudo instruction provides an offset " 618 "register!"); 619 } else { 620 MIB.add(AM6Offset); 621 } 622 } 623 624 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 625 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef(); 626 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 627 unsigned D0, D1, D2, D3; 628 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 629 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); 630 if (NumRegs > 1 && TableEntry->copyAllListRegs) 631 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); 632 if (NumRegs > 2 && TableEntry->copyAllListRegs) 633 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); 634 if (NumRegs > 3 && TableEntry->copyAllListRegs) 635 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); 636 637 // Copy the predicate operands. 638 MIB.add(MI.getOperand(OpIdx++)); 639 MIB.add(MI.getOperand(OpIdx++)); 640 641 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg. 642 MIB->addRegisterKilled(SrcReg, TRI, true); 643 else if (!SrcIsUndef) 644 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. 645 TransferImpOps(MI, MIB, MIB); 646 647 // Transfer memoperands. 648 MIB.cloneMemRefs(MI); 649 MI.eraseFromParent(); 650 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 651 } 652 653 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 654 /// register operands to real instructions with D register operands. 655 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 656 MachineInstr &MI = *MBBI; 657 MachineBasicBlock &MBB = *MI.getParent(); 658 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 659 660 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 661 assert(TableEntry && "NEONLdStTable lookup failed"); 662 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 663 unsigned NumRegs = TableEntry->NumRegs; 664 unsigned RegElts = TableEntry->RegElts; 665 666 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 667 TII->get(TableEntry->RealOpc)); 668 unsigned OpIdx = 0; 669 // The lane operand is always the 3rd from last operand, before the 2 670 // predicate operands. 671 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 672 673 // Adjust the lane and spacing as needed for Q registers. 674 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 675 if (RegSpc == EvenDblSpc && Lane >= RegElts) { 676 RegSpc = OddDblSpc; 677 Lane -= RegElts; 678 } 679 assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 680 681 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; 682 unsigned DstReg = 0; 683 bool DstIsDead = false; 684 if (TableEntry->IsLoad) { 685 DstIsDead = MI.getOperand(OpIdx).isDead(); 686 DstReg = MI.getOperand(OpIdx++).getReg(); 687 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 688 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 689 if (NumRegs > 1) 690 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 691 if (NumRegs > 2) 692 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 693 if (NumRegs > 3) 694 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 695 } 696 697 if (TableEntry->isUpdating) 698 MIB.add(MI.getOperand(OpIdx++)); 699 700 // Copy the addrmode6 operands. 701 MIB.add(MI.getOperand(OpIdx++)); 702 MIB.add(MI.getOperand(OpIdx++)); 703 // Copy the am6offset operand. 704 if (TableEntry->hasWritebackOperand) 705 MIB.add(MI.getOperand(OpIdx++)); 706 707 // Grab the super-register source. 708 MachineOperand MO = MI.getOperand(OpIdx++); 709 if (!TableEntry->IsLoad) 710 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 711 712 // Add the subregs as sources of the new instruction. 713 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 714 getKillRegState(MO.isKill())); 715 MIB.addReg(D0, SrcFlags); 716 if (NumRegs > 1) 717 MIB.addReg(D1, SrcFlags); 718 if (NumRegs > 2) 719 MIB.addReg(D2, SrcFlags); 720 if (NumRegs > 3) 721 MIB.addReg(D3, SrcFlags); 722 723 // Add the lane number operand. 724 MIB.addImm(Lane); 725 OpIdx += 1; 726 727 // Copy the predicate operands. 728 MIB.add(MI.getOperand(OpIdx++)); 729 MIB.add(MI.getOperand(OpIdx++)); 730 731 // Copy the super-register source to be an implicit source. 732 MO.setImplicit(true); 733 MIB.add(MO); 734 if (TableEntry->IsLoad) 735 // Add an implicit def for the super-register. 736 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 737 TransferImpOps(MI, MIB, MIB); 738 // Transfer memoperands. 739 MIB.cloneMemRefs(MI); 740 MI.eraseFromParent(); 741 } 742 743 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 744 /// register operands to real instructions with D register operands. 745 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 746 unsigned Opc, bool IsExt) { 747 MachineInstr &MI = *MBBI; 748 MachineBasicBlock &MBB = *MI.getParent(); 749 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 750 751 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 752 unsigned OpIdx = 0; 753 754 // Transfer the destination register operand. 755 MIB.add(MI.getOperand(OpIdx++)); 756 if (IsExt) { 757 MachineOperand VdSrc(MI.getOperand(OpIdx++)); 758 MIB.add(VdSrc); 759 } 760 761 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 762 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 763 unsigned D0, D1, D2, D3; 764 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 765 MIB.addReg(D0); 766 767 // Copy the other source register operand. 768 MachineOperand VmSrc(MI.getOperand(OpIdx++)); 769 MIB.add(VmSrc); 770 771 // Copy the predicate operands. 772 MIB.add(MI.getOperand(OpIdx++)); 773 MIB.add(MI.getOperand(OpIdx++)); 774 775 // Add an implicit kill and use for the super-reg. 776 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); 777 TransferImpOps(MI, MIB, MIB); 778 MI.eraseFromParent(); 779 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 780 } 781 782 static bool IsAnAddressOperand(const MachineOperand &MO) { 783 // This check is overly conservative. Unless we are certain that the machine 784 // operand is not a symbol reference, we return that it is a symbol reference. 785 // This is important as the load pair may not be split up Windows. 786 switch (MO.getType()) { 787 case MachineOperand::MO_Register: 788 case MachineOperand::MO_Immediate: 789 case MachineOperand::MO_CImmediate: 790 case MachineOperand::MO_FPImmediate: 791 case MachineOperand::MO_ShuffleMask: 792 return false; 793 case MachineOperand::MO_MachineBasicBlock: 794 return true; 795 case MachineOperand::MO_FrameIndex: 796 return false; 797 case MachineOperand::MO_ConstantPoolIndex: 798 case MachineOperand::MO_TargetIndex: 799 case MachineOperand::MO_JumpTableIndex: 800 case MachineOperand::MO_ExternalSymbol: 801 case MachineOperand::MO_GlobalAddress: 802 case MachineOperand::MO_BlockAddress: 803 return true; 804 case MachineOperand::MO_RegisterMask: 805 case MachineOperand::MO_RegisterLiveOut: 806 return false; 807 case MachineOperand::MO_Metadata: 808 case MachineOperand::MO_MCSymbol: 809 return true; 810 case MachineOperand::MO_CFIIndex: 811 return false; 812 case MachineOperand::MO_IntrinsicID: 813 case MachineOperand::MO_Predicate: 814 llvm_unreachable("should not exist post-isel"); 815 } 816 llvm_unreachable("unhandled machine operand type"); 817 } 818 819 static MachineOperand makeImplicit(const MachineOperand &MO) { 820 MachineOperand NewMO = MO; 821 NewMO.setImplicit(); 822 return NewMO; 823 } 824 825 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, 826 MachineBasicBlock::iterator &MBBI) { 827 MachineInstr &MI = *MBBI; 828 unsigned Opcode = MI.getOpcode(); 829 Register PredReg; 830 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 831 Register DstReg = MI.getOperand(0).getReg(); 832 bool DstIsDead = MI.getOperand(0).isDead(); 833 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; 834 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); 835 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO); 836 MachineInstrBuilder LO16, HI16; 837 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 838 839 if (!STI->hasV6T2Ops() && 840 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { 841 // FIXME Windows CE supports older ARM CPUs 842 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+"); 843 844 // Expand into a movi + orr. 845 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 846 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) 847 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 848 .addReg(DstReg); 849 850 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); 851 unsigned ImmVal = (unsigned)MO.getImm(); 852 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 853 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 854 unsigned MIFlags = MI.getFlags(); 855 LO16 = LO16.addImm(SOImmValV1); 856 HI16 = HI16.addImm(SOImmValV2); 857 LO16.cloneMemRefs(MI); 858 HI16.cloneMemRefs(MI); 859 LO16.setMIFlags(MIFlags); 860 HI16.setMIFlags(MIFlags); 861 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp()); 862 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp()); 863 if (isCC) 864 LO16.add(makeImplicit(MI.getOperand(1))); 865 TransferImpOps(MI, LO16, HI16); 866 MI.eraseFromParent(); 867 return; 868 } 869 870 unsigned LO16Opc = 0; 871 unsigned HI16Opc = 0; 872 unsigned MIFlags = MI.getFlags(); 873 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { 874 LO16Opc = ARM::t2MOVi16; 875 HI16Opc = ARM::t2MOVTi16; 876 } else { 877 LO16Opc = ARM::MOVi16; 878 HI16Opc = ARM::MOVTi16; 879 } 880 881 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); 882 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) 883 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 884 .addReg(DstReg); 885 886 LO16.setMIFlags(MIFlags); 887 HI16.setMIFlags(MIFlags); 888 889 switch (MO.getType()) { 890 case MachineOperand::MO_Immediate: { 891 unsigned Imm = MO.getImm(); 892 unsigned Lo16 = Imm & 0xffff; 893 unsigned Hi16 = (Imm >> 16) & 0xffff; 894 LO16 = LO16.addImm(Lo16); 895 HI16 = HI16.addImm(Hi16); 896 break; 897 } 898 case MachineOperand::MO_ExternalSymbol: { 899 const char *ES = MO.getSymbolName(); 900 unsigned TF = MO.getTargetFlags(); 901 LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16); 902 HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16); 903 break; 904 } 905 default: { 906 const GlobalValue *GV = MO.getGlobal(); 907 unsigned TF = MO.getTargetFlags(); 908 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 909 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 910 break; 911 } 912 } 913 914 LO16.cloneMemRefs(MI); 915 HI16.cloneMemRefs(MI); 916 LO16.addImm(Pred).addReg(PredReg); 917 HI16.addImm(Pred).addReg(PredReg); 918 919 if (RequiresBundling) 920 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator()); 921 922 if (isCC) 923 LO16.add(makeImplicit(MI.getOperand(1))); 924 TransferImpOps(MI, LO16, HI16); 925 MI.eraseFromParent(); 926 LLVM_DEBUG(dbgs() << "To: "; LO16.getInstr()->dump();); 927 LLVM_DEBUG(dbgs() << "And: "; HI16.getInstr()->dump();); 928 } 929 930 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as 931 /// possible. This only gets used at -O0 so we don't care about efficiency of 932 /// the generated code. 933 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB, 934 MachineBasicBlock::iterator MBBI, 935 unsigned LdrexOp, unsigned StrexOp, 936 unsigned UxtOp, 937 MachineBasicBlock::iterator &NextMBBI) { 938 bool IsThumb = STI->isThumb(); 939 MachineInstr &MI = *MBBI; 940 DebugLoc DL = MI.getDebugLoc(); 941 const MachineOperand &Dest = MI.getOperand(0); 942 Register TempReg = MI.getOperand(1).getReg(); 943 // Duplicating undef operands into 2 instructions does not guarantee the same 944 // value on both; However undef should be replaced by xzr anyway. 945 assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); 946 Register AddrReg = MI.getOperand(2).getReg(); 947 Register DesiredReg = MI.getOperand(3).getReg(); 948 Register NewReg = MI.getOperand(4).getReg(); 949 950 MachineFunction *MF = MBB.getParent(); 951 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 952 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 953 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 954 955 MF->insert(++MBB.getIterator(), LoadCmpBB); 956 MF->insert(++LoadCmpBB->getIterator(), StoreBB); 957 MF->insert(++StoreBB->getIterator(), DoneBB); 958 959 if (UxtOp) { 960 MachineInstrBuilder MIB = 961 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg) 962 .addReg(DesiredReg, RegState::Kill); 963 if (!IsThumb) 964 MIB.addImm(0); 965 MIB.add(predOps(ARMCC::AL)); 966 } 967 968 // .Lloadcmp: 969 // ldrex rDest, [rAddr] 970 // cmp rDest, rDesired 971 // bne .Ldone 972 973 MachineInstrBuilder MIB; 974 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg()); 975 MIB.addReg(AddrReg); 976 if (LdrexOp == ARM::t2LDREX) 977 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset. 978 MIB.add(predOps(ARMCC::AL)); 979 980 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; 981 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 982 .addReg(Dest.getReg(), getKillRegState(Dest.isDead())) 983 .addReg(DesiredReg) 984 .add(predOps(ARMCC::AL)); 985 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; 986 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) 987 .addMBB(DoneBB) 988 .addImm(ARMCC::NE) 989 .addReg(ARM::CPSR, RegState::Kill); 990 LoadCmpBB->addSuccessor(DoneBB); 991 LoadCmpBB->addSuccessor(StoreBB); 992 993 // .Lstore: 994 // strex rTempReg, rNew, [rAddr] 995 // cmp rTempReg, #0 996 // bne .Lloadcmp 997 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg) 998 .addReg(NewReg) 999 .addReg(AddrReg); 1000 if (StrexOp == ARM::t2STREX) 1001 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset. 1002 MIB.add(predOps(ARMCC::AL)); 1003 1004 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; 1005 BuildMI(StoreBB, DL, TII->get(CMPri)) 1006 .addReg(TempReg, RegState::Kill) 1007 .addImm(0) 1008 .add(predOps(ARMCC::AL)); 1009 BuildMI(StoreBB, DL, TII->get(Bcc)) 1010 .addMBB(LoadCmpBB) 1011 .addImm(ARMCC::NE) 1012 .addReg(ARM::CPSR, RegState::Kill); 1013 StoreBB->addSuccessor(LoadCmpBB); 1014 StoreBB->addSuccessor(DoneBB); 1015 1016 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); 1017 DoneBB->transferSuccessors(&MBB); 1018 1019 MBB.addSuccessor(LoadCmpBB); 1020 1021 NextMBBI = MBB.end(); 1022 MI.eraseFromParent(); 1023 1024 // Recompute livein lists. 1025 LivePhysRegs LiveRegs; 1026 computeAndAddLiveIns(LiveRegs, *DoneBB); 1027 computeAndAddLiveIns(LiveRegs, *StoreBB); 1028 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1029 // Do an extra pass around the loop to get loop carried registers right. 1030 StoreBB->clearLiveIns(); 1031 computeAndAddLiveIns(LiveRegs, *StoreBB); 1032 LoadCmpBB->clearLiveIns(); 1033 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1034 1035 return true; 1036 } 1037 1038 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a 1039 /// single GPRPair register), Thumb's take two separate registers so we need to 1040 /// extract the subregs from the pair. 1041 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, 1042 unsigned Flags, bool IsThumb, 1043 const TargetRegisterInfo *TRI) { 1044 if (IsThumb) { 1045 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); 1046 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); 1047 MIB.addReg(RegLo, Flags); 1048 MIB.addReg(RegHi, Flags); 1049 } else 1050 MIB.addReg(Reg.getReg(), Flags); 1051 } 1052 1053 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop. 1054 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB, 1055 MachineBasicBlock::iterator MBBI, 1056 MachineBasicBlock::iterator &NextMBBI) { 1057 bool IsThumb = STI->isThumb(); 1058 MachineInstr &MI = *MBBI; 1059 DebugLoc DL = MI.getDebugLoc(); 1060 MachineOperand &Dest = MI.getOperand(0); 1061 Register TempReg = MI.getOperand(1).getReg(); 1062 // Duplicating undef operands into 2 instructions does not guarantee the same 1063 // value on both; However undef should be replaced by xzr anyway. 1064 assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); 1065 Register AddrReg = MI.getOperand(2).getReg(); 1066 Register DesiredReg = MI.getOperand(3).getReg(); 1067 MachineOperand New = MI.getOperand(4); 1068 New.setIsKill(false); 1069 1070 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); 1071 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); 1072 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); 1073 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); 1074 1075 MachineFunction *MF = MBB.getParent(); 1076 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1077 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1078 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1079 1080 MF->insert(++MBB.getIterator(), LoadCmpBB); 1081 MF->insert(++LoadCmpBB->getIterator(), StoreBB); 1082 MF->insert(++StoreBB->getIterator(), DoneBB); 1083 1084 // .Lloadcmp: 1085 // ldrexd rDestLo, rDestHi, [rAddr] 1086 // cmp rDestLo, rDesiredLo 1087 // sbcs dead rTempReg, rDestHi, rDesiredHi 1088 // bne .Ldone 1089 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD; 1090 MachineInstrBuilder MIB; 1091 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD)); 1092 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI); 1093 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); 1094 1095 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; 1096 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 1097 .addReg(DestLo, getKillRegState(Dest.isDead())) 1098 .addReg(DesiredLo) 1099 .add(predOps(ARMCC::AL)); 1100 1101 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 1102 .addReg(DestHi, getKillRegState(Dest.isDead())) 1103 .addReg(DesiredHi) 1104 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); 1105 1106 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; 1107 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) 1108 .addMBB(DoneBB) 1109 .addImm(ARMCC::NE) 1110 .addReg(ARM::CPSR, RegState::Kill); 1111 LoadCmpBB->addSuccessor(DoneBB); 1112 LoadCmpBB->addSuccessor(StoreBB); 1113 1114 // .Lstore: 1115 // strexd rTempReg, rNewLo, rNewHi, [rAddr] 1116 // cmp rTempReg, #0 1117 // bne .Lloadcmp 1118 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; 1119 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); 1120 unsigned Flags = getKillRegState(New.isDead()); 1121 addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI); 1122 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); 1123 1124 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; 1125 BuildMI(StoreBB, DL, TII->get(CMPri)) 1126 .addReg(TempReg, RegState::Kill) 1127 .addImm(0) 1128 .add(predOps(ARMCC::AL)); 1129 BuildMI(StoreBB, DL, TII->get(Bcc)) 1130 .addMBB(LoadCmpBB) 1131 .addImm(ARMCC::NE) 1132 .addReg(ARM::CPSR, RegState::Kill); 1133 StoreBB->addSuccessor(LoadCmpBB); 1134 StoreBB->addSuccessor(DoneBB); 1135 1136 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); 1137 DoneBB->transferSuccessors(&MBB); 1138 1139 MBB.addSuccessor(LoadCmpBB); 1140 1141 NextMBBI = MBB.end(); 1142 MI.eraseFromParent(); 1143 1144 // Recompute livein lists. 1145 LivePhysRegs LiveRegs; 1146 computeAndAddLiveIns(LiveRegs, *DoneBB); 1147 computeAndAddLiveIns(LiveRegs, *StoreBB); 1148 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1149 // Do an extra pass around the loop to get loop carried registers right. 1150 StoreBB->clearLiveIns(); 1151 computeAndAddLiveIns(LiveRegs, *StoreBB); 1152 LoadCmpBB->clearLiveIns(); 1153 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1154 1155 return true; 1156 } 1157 1158 1159 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, 1160 MachineBasicBlock::iterator MBBI, 1161 MachineBasicBlock::iterator &NextMBBI) { 1162 MachineInstr &MI = *MBBI; 1163 unsigned Opcode = MI.getOpcode(); 1164 switch (Opcode) { 1165 default: 1166 return false; 1167 1168 case ARM::TCRETURNdi: 1169 case ARM::TCRETURNri: { 1170 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 1171 assert(MBBI->isReturn() && 1172 "Can only insert epilog into returning blocks"); 1173 unsigned RetOpcode = MBBI->getOpcode(); 1174 DebugLoc dl = MBBI->getDebugLoc(); 1175 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>( 1176 MBB.getParent()->getSubtarget().getInstrInfo()); 1177 1178 // Tail call return: adjust the stack pointer and jump to callee. 1179 MBBI = MBB.getLastNonDebugInstr(); 1180 MachineOperand &JumpTarget = MBBI->getOperand(0); 1181 1182 // Jump to label or value in register. 1183 if (RetOpcode == ARM::TCRETURNdi) { 1184 unsigned TCOpcode = 1185 STI->isThumb() 1186 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) 1187 : ARM::TAILJMPd; 1188 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); 1189 if (JumpTarget.isGlobal()) 1190 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 1191 JumpTarget.getTargetFlags()); 1192 else { 1193 assert(JumpTarget.isSymbol()); 1194 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 1195 JumpTarget.getTargetFlags()); 1196 } 1197 1198 // Add the default predicate in Thumb mode. 1199 if (STI->isThumb()) 1200 MIB.add(predOps(ARMCC::AL)); 1201 } else if (RetOpcode == ARM::TCRETURNri) { 1202 unsigned Opcode = 1203 STI->isThumb() ? ARM::tTAILJMPr 1204 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4); 1205 BuildMI(MBB, MBBI, dl, 1206 TII.get(Opcode)) 1207 .addReg(JumpTarget.getReg(), RegState::Kill); 1208 } 1209 1210 auto NewMI = std::prev(MBBI); 1211 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) 1212 NewMI->addOperand(MBBI->getOperand(i)); 1213 1214 1215 // Update call site info and delete the pseudo instruction TCRETURN. 1216 if (MI.isCandidateForCallSiteEntry()) 1217 MI.getMF()->moveCallSiteInfo(&MI, &*NewMI); 1218 MBB.erase(MBBI); 1219 1220 MBBI = NewMI; 1221 return true; 1222 } 1223 case ARM::VMOVHcc: 1224 case ARM::VMOVScc: 1225 case ARM::VMOVDcc: { 1226 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD; 1227 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), 1228 MI.getOperand(1).getReg()) 1229 .add(MI.getOperand(2)) 1230 .addImm(MI.getOperand(3).getImm()) // 'pred' 1231 .add(MI.getOperand(4)) 1232 .add(makeImplicit(MI.getOperand(1))); 1233 1234 MI.eraseFromParent(); 1235 return true; 1236 } 1237 case ARM::t2MOVCCr: 1238 case ARM::MOVCCr: { 1239 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; 1240 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 1241 MI.getOperand(1).getReg()) 1242 .add(MI.getOperand(2)) 1243 .addImm(MI.getOperand(3).getImm()) // 'pred' 1244 .add(MI.getOperand(4)) 1245 .add(condCodeOp()) // 's' bit 1246 .add(makeImplicit(MI.getOperand(1))); 1247 1248 MI.eraseFromParent(); 1249 return true; 1250 } 1251 case ARM::MOVCCsi: { 1252 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 1253 (MI.getOperand(1).getReg())) 1254 .add(MI.getOperand(2)) 1255 .addImm(MI.getOperand(3).getImm()) 1256 .addImm(MI.getOperand(4).getImm()) // 'pred' 1257 .add(MI.getOperand(5)) 1258 .add(condCodeOp()) // 's' bit 1259 .add(makeImplicit(MI.getOperand(1))); 1260 1261 MI.eraseFromParent(); 1262 return true; 1263 } 1264 case ARM::MOVCCsr: { 1265 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), 1266 (MI.getOperand(1).getReg())) 1267 .add(MI.getOperand(2)) 1268 .add(MI.getOperand(3)) 1269 .addImm(MI.getOperand(4).getImm()) 1270 .addImm(MI.getOperand(5).getImm()) // 'pred' 1271 .add(MI.getOperand(6)) 1272 .add(condCodeOp()) // 's' bit 1273 .add(makeImplicit(MI.getOperand(1))); 1274 1275 MI.eraseFromParent(); 1276 return true; 1277 } 1278 case ARM::t2MOVCCi16: 1279 case ARM::MOVCCi16: { 1280 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; 1281 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 1282 MI.getOperand(1).getReg()) 1283 .addImm(MI.getOperand(2).getImm()) 1284 .addImm(MI.getOperand(3).getImm()) // 'pred' 1285 .add(MI.getOperand(4)) 1286 .add(makeImplicit(MI.getOperand(1))); 1287 MI.eraseFromParent(); 1288 return true; 1289 } 1290 case ARM::t2MOVCCi: 1291 case ARM::MOVCCi: { 1292 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; 1293 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 1294 MI.getOperand(1).getReg()) 1295 .addImm(MI.getOperand(2).getImm()) 1296 .addImm(MI.getOperand(3).getImm()) // 'pred' 1297 .add(MI.getOperand(4)) 1298 .add(condCodeOp()) // 's' bit 1299 .add(makeImplicit(MI.getOperand(1))); 1300 1301 MI.eraseFromParent(); 1302 return true; 1303 } 1304 case ARM::t2MVNCCi: 1305 case ARM::MVNCCi: { 1306 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; 1307 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 1308 MI.getOperand(1).getReg()) 1309 .addImm(MI.getOperand(2).getImm()) 1310 .addImm(MI.getOperand(3).getImm()) // 'pred' 1311 .add(MI.getOperand(4)) 1312 .add(condCodeOp()) // 's' bit 1313 .add(makeImplicit(MI.getOperand(1))); 1314 1315 MI.eraseFromParent(); 1316 return true; 1317 } 1318 case ARM::t2MOVCClsl: 1319 case ARM::t2MOVCClsr: 1320 case ARM::t2MOVCCasr: 1321 case ARM::t2MOVCCror: { 1322 unsigned NewOpc; 1323 switch (Opcode) { 1324 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; 1325 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; 1326 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; 1327 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; 1328 default: llvm_unreachable("unexpeced conditional move"); 1329 } 1330 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 1331 MI.getOperand(1).getReg()) 1332 .add(MI.getOperand(2)) 1333 .addImm(MI.getOperand(3).getImm()) 1334 .addImm(MI.getOperand(4).getImm()) // 'pred' 1335 .add(MI.getOperand(5)) 1336 .add(condCodeOp()) // 's' bit 1337 .add(makeImplicit(MI.getOperand(1))); 1338 MI.eraseFromParent(); 1339 return true; 1340 } 1341 case ARM::Int_eh_sjlj_dispatchsetup: { 1342 MachineFunction &MF = *MI.getParent()->getParent(); 1343 const ARMBaseInstrInfo *AII = 1344 static_cast<const ARMBaseInstrInfo*>(TII); 1345 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 1346 // For functions using a base pointer, we rematerialize it (via the frame 1347 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it 1348 // for us. Otherwise, expand to nothing. 1349 if (RI.hasBasePointer(MF)) { 1350 int32_t NumBytes = AFI->getFramePtrSpillOffset(); 1351 Register FramePtr = RI.getFrameRegister(MF); 1352 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) && 1353 "base pointer without frame pointer?"); 1354 1355 if (AFI->isThumb2Function()) { 1356 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 1357 FramePtr, -NumBytes, ARMCC::AL, 0, *TII); 1358 } else if (AFI->isThumbFunction()) { 1359 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 1360 FramePtr, -NumBytes, *TII, RI); 1361 } else { 1362 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 1363 FramePtr, -NumBytes, ARMCC::AL, 0, 1364 *TII); 1365 } 1366 // If there's dynamic realignment, adjust for it. 1367 if (RI.needsStackRealignment(MF)) { 1368 MachineFrameInfo &MFI = MF.getFrameInfo(); 1369 Align MaxAlign = MFI.getMaxAlign(); 1370 assert (!AFI->isThumb1OnlyFunction()); 1371 // Emit bic r6, r6, MaxAlign 1372 assert(MaxAlign <= Align(256) && 1373 "The BIC instruction cannot encode " 1374 "immediates larger than 256 with all lower " 1375 "bits set."); 1376 unsigned bicOpc = AFI->isThumbFunction() ? 1377 ARM::t2BICri : ARM::BICri; 1378 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6) 1379 .addReg(ARM::R6, RegState::Kill) 1380 .addImm(MaxAlign.value() - 1) 1381 .add(predOps(ARMCC::AL)) 1382 .add(condCodeOp()); 1383 } 1384 1385 } 1386 MI.eraseFromParent(); 1387 return true; 1388 } 1389 1390 case ARM::MOVsrl_flag: 1391 case ARM::MOVsra_flag: { 1392 // These are just fancy MOVs instructions. 1393 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 1394 MI.getOperand(0).getReg()) 1395 .add(MI.getOperand(1)) 1396 .addImm(ARM_AM::getSORegOpc( 1397 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1)) 1398 .add(predOps(ARMCC::AL)) 1399 .addReg(ARM::CPSR, RegState::Define); 1400 MI.eraseFromParent(); 1401 return true; 1402 } 1403 case ARM::RRX: { 1404 // This encodes as "MOVs Rd, Rm, rrx 1405 MachineInstrBuilder MIB = 1406 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 1407 MI.getOperand(0).getReg()) 1408 .add(MI.getOperand(1)) 1409 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)) 1410 .add(predOps(ARMCC::AL)) 1411 .add(condCodeOp()); 1412 TransferImpOps(MI, MIB, MIB); 1413 MI.eraseFromParent(); 1414 return true; 1415 } 1416 case ARM::tTPsoft: 1417 case ARM::TPsoft: { 1418 const bool Thumb = Opcode == ARM::tTPsoft; 1419 1420 MachineInstrBuilder MIB; 1421 MachineFunction *MF = MBB.getParent(); 1422 if (STI->genLongCalls()) { 1423 MachineConstantPool *MCP = MF->getConstantPool(); 1424 unsigned PCLabelID = AFI->createPICLabelUId(); 1425 MachineConstantPoolValue *CPV = 1426 ARMConstantPoolSymbol::Create(MF->getFunction().getContext(), 1427 "__aeabi_read_tp", PCLabelID, 0); 1428 Register Reg = MI.getOperand(0).getReg(); 1429 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1430 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg) 1431 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4)); 1432 if (!Thumb) 1433 MIB.addImm(0); 1434 MIB.add(predOps(ARMCC::AL)); 1435 1436 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1437 TII->get(Thumb ? ARM::tBLXr : ARM::BLX)); 1438 if (Thumb) 1439 MIB.add(predOps(ARMCC::AL)); 1440 MIB.addReg(Reg, RegState::Kill); 1441 } else { 1442 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1443 TII->get(Thumb ? ARM::tBL : ARM::BL)); 1444 if (Thumb) 1445 MIB.add(predOps(ARMCC::AL)); 1446 MIB.addExternalSymbol("__aeabi_read_tp", 0); 1447 } 1448 1449 MIB.cloneMemRefs(MI); 1450 TransferImpOps(MI, MIB, MIB); 1451 // Update the call site info. 1452 if (MI.isCandidateForCallSiteEntry()) 1453 MF->moveCallSiteInfo(&MI, &*MIB); 1454 MI.eraseFromParent(); 1455 return true; 1456 } 1457 case ARM::tLDRpci_pic: 1458 case ARM::t2LDRpci_pic: { 1459 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 1460 ? ARM::tLDRpci : ARM::t2LDRpci; 1461 Register DstReg = MI.getOperand(0).getReg(); 1462 bool DstIsDead = MI.getOperand(0).isDead(); 1463 MachineInstrBuilder MIB1 = 1464 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg) 1465 .add(MI.getOperand(1)) 1466 .add(predOps(ARMCC::AL)); 1467 MIB1.cloneMemRefs(MI); 1468 MachineInstrBuilder MIB2 = 1469 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) 1470 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 1471 .addReg(DstReg) 1472 .add(MI.getOperand(2)); 1473 TransferImpOps(MI, MIB1, MIB2); 1474 MI.eraseFromParent(); 1475 return true; 1476 } 1477 1478 case ARM::LDRLIT_ga_abs: 1479 case ARM::LDRLIT_ga_pcrel: 1480 case ARM::LDRLIT_ga_pcrel_ldr: 1481 case ARM::tLDRLIT_ga_abs: 1482 case ARM::tLDRLIT_ga_pcrel: { 1483 Register DstReg = MI.getOperand(0).getReg(); 1484 bool DstIsDead = MI.getOperand(0).isDead(); 1485 const MachineOperand &MO1 = MI.getOperand(1); 1486 auto Flags = MO1.getTargetFlags(); 1487 const GlobalValue *GV = MO1.getGlobal(); 1488 bool IsARM = 1489 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs; 1490 bool IsPIC = 1491 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; 1492 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; 1493 unsigned PICAddOpc = 1494 IsARM 1495 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 1496 : ARM::tPICADD; 1497 1498 // We need a new const-pool entry to load from. 1499 MachineConstantPool *MCP = MBB.getParent()->getConstantPool(); 1500 unsigned ARMPCLabelIndex = 0; 1501 MachineConstantPoolValue *CPV; 1502 1503 if (IsPIC) { 1504 unsigned PCAdj = IsARM ? 8 : 4; 1505 auto Modifier = (Flags & ARMII::MO_GOT) 1506 ? ARMCP::GOT_PREL 1507 : ARMCP::no_modifier; 1508 ARMPCLabelIndex = AFI->createPICLabelUId(); 1509 CPV = ARMConstantPoolConstant::Create( 1510 GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj, Modifier, 1511 /*AddCurrentAddr*/ Modifier == ARMCP::GOT_PREL); 1512 } else 1513 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier); 1514 1515 MachineInstrBuilder MIB = 1516 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg) 1517 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4)); 1518 if (IsARM) 1519 MIB.addImm(0); 1520 MIB.add(predOps(ARMCC::AL)); 1521 1522 if (IsPIC) { 1523 MachineInstrBuilder MIB = 1524 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc)) 1525 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 1526 .addReg(DstReg) 1527 .addImm(ARMPCLabelIndex); 1528 1529 if (IsARM) 1530 MIB.add(predOps(ARMCC::AL)); 1531 } 1532 1533 MI.eraseFromParent(); 1534 return true; 1535 } 1536 case ARM::MOV_ga_pcrel: 1537 case ARM::MOV_ga_pcrel_ldr: 1538 case ARM::t2MOV_ga_pcrel: { 1539 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode. 1540 unsigned LabelId = AFI->createPICLabelUId(); 1541 Register DstReg = MI.getOperand(0).getReg(); 1542 bool DstIsDead = MI.getOperand(0).isDead(); 1543 const MachineOperand &MO1 = MI.getOperand(1); 1544 const GlobalValue *GV = MO1.getGlobal(); 1545 unsigned TF = MO1.getTargetFlags(); 1546 bool isARM = Opcode != ARM::t2MOV_ga_pcrel; 1547 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; 1548 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; 1549 unsigned LO16TF = TF | ARMII::MO_LO16; 1550 unsigned HI16TF = TF | ARMII::MO_HI16; 1551 unsigned PICAddOpc = isARM 1552 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 1553 : ARM::tPICADD; 1554 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1555 TII->get(LO16Opc), DstReg) 1556 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) 1557 .addImm(LabelId); 1558 1559 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg) 1560 .addReg(DstReg) 1561 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) 1562 .addImm(LabelId); 1563 1564 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1565 TII->get(PICAddOpc)) 1566 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 1567 .addReg(DstReg).addImm(LabelId); 1568 if (isARM) { 1569 MIB3.add(predOps(ARMCC::AL)); 1570 if (Opcode == ARM::MOV_ga_pcrel_ldr) 1571 MIB3.cloneMemRefs(MI); 1572 } 1573 TransferImpOps(MI, MIB1, MIB3); 1574 MI.eraseFromParent(); 1575 return true; 1576 } 1577 1578 case ARM::MOVi32imm: 1579 case ARM::MOVCCi32imm: 1580 case ARM::t2MOVi32imm: 1581 case ARM::t2MOVCCi32imm: 1582 ExpandMOV32BitImm(MBB, MBBI); 1583 return true; 1584 1585 case ARM::SUBS_PC_LR: { 1586 MachineInstrBuilder MIB = 1587 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) 1588 .addReg(ARM::LR) 1589 .add(MI.getOperand(0)) 1590 .add(MI.getOperand(1)) 1591 .add(MI.getOperand(2)) 1592 .addReg(ARM::CPSR, RegState::Undef); 1593 TransferImpOps(MI, MIB, MIB); 1594 MI.eraseFromParent(); 1595 return true; 1596 } 1597 case ARM::VLDMQIA: { 1598 unsigned NewOpc = ARM::VLDMDIA; 1599 MachineInstrBuilder MIB = 1600 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 1601 unsigned OpIdx = 0; 1602 1603 // Grab the Q register destination. 1604 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 1605 Register DstReg = MI.getOperand(OpIdx++).getReg(); 1606 1607 // Copy the source register. 1608 MIB.add(MI.getOperand(OpIdx++)); 1609 1610 // Copy the predicate operands. 1611 MIB.add(MI.getOperand(OpIdx++)); 1612 MIB.add(MI.getOperand(OpIdx++)); 1613 1614 // Add the destination operands (D subregs). 1615 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0); 1616 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1); 1617 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 1618 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 1619 1620 // Add an implicit def for the super-register. 1621 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 1622 TransferImpOps(MI, MIB, MIB); 1623 MIB.cloneMemRefs(MI); 1624 MI.eraseFromParent(); 1625 return true; 1626 } 1627 1628 case ARM::VSTMQIA: { 1629 unsigned NewOpc = ARM::VSTMDIA; 1630 MachineInstrBuilder MIB = 1631 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 1632 unsigned OpIdx = 0; 1633 1634 // Grab the Q register source. 1635 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 1636 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 1637 1638 // Copy the destination register. 1639 MachineOperand Dst(MI.getOperand(OpIdx++)); 1640 MIB.add(Dst); 1641 1642 // Copy the predicate operands. 1643 MIB.add(MI.getOperand(OpIdx++)); 1644 MIB.add(MI.getOperand(OpIdx++)); 1645 1646 // Add the source operands (D subregs). 1647 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); 1648 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); 1649 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) 1650 .addReg(D1, SrcIsKill ? RegState::Kill : 0); 1651 1652 if (SrcIsKill) // Add an implicit kill for the Q register. 1653 MIB->addRegisterKilled(SrcReg, TRI, true); 1654 1655 TransferImpOps(MI, MIB, MIB); 1656 MIB.cloneMemRefs(MI); 1657 MI.eraseFromParent(); 1658 return true; 1659 } 1660 1661 case ARM::VLD2q8Pseudo: 1662 case ARM::VLD2q16Pseudo: 1663 case ARM::VLD2q32Pseudo: 1664 case ARM::VLD2q8PseudoWB_fixed: 1665 case ARM::VLD2q16PseudoWB_fixed: 1666 case ARM::VLD2q32PseudoWB_fixed: 1667 case ARM::VLD2q8PseudoWB_register: 1668 case ARM::VLD2q16PseudoWB_register: 1669 case ARM::VLD2q32PseudoWB_register: 1670 case ARM::VLD3d8Pseudo: 1671 case ARM::VLD3d16Pseudo: 1672 case ARM::VLD3d32Pseudo: 1673 case ARM::VLD1d8TPseudo: 1674 case ARM::VLD1d16TPseudo: 1675 case ARM::VLD1d32TPseudo: 1676 case ARM::VLD1d64TPseudo: 1677 case ARM::VLD1d64TPseudoWB_fixed: 1678 case ARM::VLD1d64TPseudoWB_register: 1679 case ARM::VLD3d8Pseudo_UPD: 1680 case ARM::VLD3d16Pseudo_UPD: 1681 case ARM::VLD3d32Pseudo_UPD: 1682 case ARM::VLD3q8Pseudo_UPD: 1683 case ARM::VLD3q16Pseudo_UPD: 1684 case ARM::VLD3q32Pseudo_UPD: 1685 case ARM::VLD3q8oddPseudo: 1686 case ARM::VLD3q16oddPseudo: 1687 case ARM::VLD3q32oddPseudo: 1688 case ARM::VLD3q8oddPseudo_UPD: 1689 case ARM::VLD3q16oddPseudo_UPD: 1690 case ARM::VLD3q32oddPseudo_UPD: 1691 case ARM::VLD4d8Pseudo: 1692 case ARM::VLD4d16Pseudo: 1693 case ARM::VLD4d32Pseudo: 1694 case ARM::VLD1d8QPseudo: 1695 case ARM::VLD1d16QPseudo: 1696 case ARM::VLD1d32QPseudo: 1697 case ARM::VLD1d64QPseudo: 1698 case ARM::VLD1d64QPseudoWB_fixed: 1699 case ARM::VLD1d64QPseudoWB_register: 1700 case ARM::VLD1q8HighQPseudo: 1701 case ARM::VLD1q8LowQPseudo_UPD: 1702 case ARM::VLD1q8HighTPseudo: 1703 case ARM::VLD1q8LowTPseudo_UPD: 1704 case ARM::VLD1q16HighQPseudo: 1705 case ARM::VLD1q16LowQPseudo_UPD: 1706 case ARM::VLD1q16HighTPseudo: 1707 case ARM::VLD1q16LowTPseudo_UPD: 1708 case ARM::VLD1q32HighQPseudo: 1709 case ARM::VLD1q32LowQPseudo_UPD: 1710 case ARM::VLD1q32HighTPseudo: 1711 case ARM::VLD1q32LowTPseudo_UPD: 1712 case ARM::VLD1q64HighQPseudo: 1713 case ARM::VLD1q64LowQPseudo_UPD: 1714 case ARM::VLD1q64HighTPseudo: 1715 case ARM::VLD1q64LowTPseudo_UPD: 1716 case ARM::VLD4d8Pseudo_UPD: 1717 case ARM::VLD4d16Pseudo_UPD: 1718 case ARM::VLD4d32Pseudo_UPD: 1719 case ARM::VLD4q8Pseudo_UPD: 1720 case ARM::VLD4q16Pseudo_UPD: 1721 case ARM::VLD4q32Pseudo_UPD: 1722 case ARM::VLD4q8oddPseudo: 1723 case ARM::VLD4q16oddPseudo: 1724 case ARM::VLD4q32oddPseudo: 1725 case ARM::VLD4q8oddPseudo_UPD: 1726 case ARM::VLD4q16oddPseudo_UPD: 1727 case ARM::VLD4q32oddPseudo_UPD: 1728 case ARM::VLD3DUPd8Pseudo: 1729 case ARM::VLD3DUPd16Pseudo: 1730 case ARM::VLD3DUPd32Pseudo: 1731 case ARM::VLD3DUPd8Pseudo_UPD: 1732 case ARM::VLD3DUPd16Pseudo_UPD: 1733 case ARM::VLD3DUPd32Pseudo_UPD: 1734 case ARM::VLD4DUPd8Pseudo: 1735 case ARM::VLD4DUPd16Pseudo: 1736 case ARM::VLD4DUPd32Pseudo: 1737 case ARM::VLD4DUPd8Pseudo_UPD: 1738 case ARM::VLD4DUPd16Pseudo_UPD: 1739 case ARM::VLD4DUPd32Pseudo_UPD: 1740 case ARM::VLD2DUPq8EvenPseudo: 1741 case ARM::VLD2DUPq8OddPseudo: 1742 case ARM::VLD2DUPq16EvenPseudo: 1743 case ARM::VLD2DUPq16OddPseudo: 1744 case ARM::VLD2DUPq32EvenPseudo: 1745 case ARM::VLD2DUPq32OddPseudo: 1746 case ARM::VLD3DUPq8EvenPseudo: 1747 case ARM::VLD3DUPq8OddPseudo: 1748 case ARM::VLD3DUPq16EvenPseudo: 1749 case ARM::VLD3DUPq16OddPseudo: 1750 case ARM::VLD3DUPq32EvenPseudo: 1751 case ARM::VLD3DUPq32OddPseudo: 1752 case ARM::VLD4DUPq8EvenPseudo: 1753 case ARM::VLD4DUPq8OddPseudo: 1754 case ARM::VLD4DUPq16EvenPseudo: 1755 case ARM::VLD4DUPq16OddPseudo: 1756 case ARM::VLD4DUPq32EvenPseudo: 1757 case ARM::VLD4DUPq32OddPseudo: 1758 ExpandVLD(MBBI); 1759 return true; 1760 1761 case ARM::VST2q8Pseudo: 1762 case ARM::VST2q16Pseudo: 1763 case ARM::VST2q32Pseudo: 1764 case ARM::VST2q8PseudoWB_fixed: 1765 case ARM::VST2q16PseudoWB_fixed: 1766 case ARM::VST2q32PseudoWB_fixed: 1767 case ARM::VST2q8PseudoWB_register: 1768 case ARM::VST2q16PseudoWB_register: 1769 case ARM::VST2q32PseudoWB_register: 1770 case ARM::VST3d8Pseudo: 1771 case ARM::VST3d16Pseudo: 1772 case ARM::VST3d32Pseudo: 1773 case ARM::VST1d8TPseudo: 1774 case ARM::VST1d16TPseudo: 1775 case ARM::VST1d32TPseudo: 1776 case ARM::VST1d64TPseudo: 1777 case ARM::VST3d8Pseudo_UPD: 1778 case ARM::VST3d16Pseudo_UPD: 1779 case ARM::VST3d32Pseudo_UPD: 1780 case ARM::VST1d64TPseudoWB_fixed: 1781 case ARM::VST1d64TPseudoWB_register: 1782 case ARM::VST3q8Pseudo_UPD: 1783 case ARM::VST3q16Pseudo_UPD: 1784 case ARM::VST3q32Pseudo_UPD: 1785 case ARM::VST3q8oddPseudo: 1786 case ARM::VST3q16oddPseudo: 1787 case ARM::VST3q32oddPseudo: 1788 case ARM::VST3q8oddPseudo_UPD: 1789 case ARM::VST3q16oddPseudo_UPD: 1790 case ARM::VST3q32oddPseudo_UPD: 1791 case ARM::VST4d8Pseudo: 1792 case ARM::VST4d16Pseudo: 1793 case ARM::VST4d32Pseudo: 1794 case ARM::VST1d8QPseudo: 1795 case ARM::VST1d16QPseudo: 1796 case ARM::VST1d32QPseudo: 1797 case ARM::VST1d64QPseudo: 1798 case ARM::VST4d8Pseudo_UPD: 1799 case ARM::VST4d16Pseudo_UPD: 1800 case ARM::VST4d32Pseudo_UPD: 1801 case ARM::VST1d64QPseudoWB_fixed: 1802 case ARM::VST1d64QPseudoWB_register: 1803 case ARM::VST1q8HighQPseudo: 1804 case ARM::VST1q8LowQPseudo_UPD: 1805 case ARM::VST1q8HighTPseudo: 1806 case ARM::VST1q8LowTPseudo_UPD: 1807 case ARM::VST1q16HighQPseudo: 1808 case ARM::VST1q16LowQPseudo_UPD: 1809 case ARM::VST1q16HighTPseudo: 1810 case ARM::VST1q16LowTPseudo_UPD: 1811 case ARM::VST1q32HighQPseudo: 1812 case ARM::VST1q32LowQPseudo_UPD: 1813 case ARM::VST1q32HighTPseudo: 1814 case ARM::VST1q32LowTPseudo_UPD: 1815 case ARM::VST1q64HighQPseudo: 1816 case ARM::VST1q64LowQPseudo_UPD: 1817 case ARM::VST1q64HighTPseudo: 1818 case ARM::VST1q64LowTPseudo_UPD: 1819 case ARM::VST4q8Pseudo_UPD: 1820 case ARM::VST4q16Pseudo_UPD: 1821 case ARM::VST4q32Pseudo_UPD: 1822 case ARM::VST4q8oddPseudo: 1823 case ARM::VST4q16oddPseudo: 1824 case ARM::VST4q32oddPseudo: 1825 case ARM::VST4q8oddPseudo_UPD: 1826 case ARM::VST4q16oddPseudo_UPD: 1827 case ARM::VST4q32oddPseudo_UPD: 1828 ExpandVST(MBBI); 1829 return true; 1830 1831 case ARM::VLD1LNq8Pseudo: 1832 case ARM::VLD1LNq16Pseudo: 1833 case ARM::VLD1LNq32Pseudo: 1834 case ARM::VLD1LNq8Pseudo_UPD: 1835 case ARM::VLD1LNq16Pseudo_UPD: 1836 case ARM::VLD1LNq32Pseudo_UPD: 1837 case ARM::VLD2LNd8Pseudo: 1838 case ARM::VLD2LNd16Pseudo: 1839 case ARM::VLD2LNd32Pseudo: 1840 case ARM::VLD2LNq16Pseudo: 1841 case ARM::VLD2LNq32Pseudo: 1842 case ARM::VLD2LNd8Pseudo_UPD: 1843 case ARM::VLD2LNd16Pseudo_UPD: 1844 case ARM::VLD2LNd32Pseudo_UPD: 1845 case ARM::VLD2LNq16Pseudo_UPD: 1846 case ARM::VLD2LNq32Pseudo_UPD: 1847 case ARM::VLD3LNd8Pseudo: 1848 case ARM::VLD3LNd16Pseudo: 1849 case ARM::VLD3LNd32Pseudo: 1850 case ARM::VLD3LNq16Pseudo: 1851 case ARM::VLD3LNq32Pseudo: 1852 case ARM::VLD3LNd8Pseudo_UPD: 1853 case ARM::VLD3LNd16Pseudo_UPD: 1854 case ARM::VLD3LNd32Pseudo_UPD: 1855 case ARM::VLD3LNq16Pseudo_UPD: 1856 case ARM::VLD3LNq32Pseudo_UPD: 1857 case ARM::VLD4LNd8Pseudo: 1858 case ARM::VLD4LNd16Pseudo: 1859 case ARM::VLD4LNd32Pseudo: 1860 case ARM::VLD4LNq16Pseudo: 1861 case ARM::VLD4LNq32Pseudo: 1862 case ARM::VLD4LNd8Pseudo_UPD: 1863 case ARM::VLD4LNd16Pseudo_UPD: 1864 case ARM::VLD4LNd32Pseudo_UPD: 1865 case ARM::VLD4LNq16Pseudo_UPD: 1866 case ARM::VLD4LNq32Pseudo_UPD: 1867 case ARM::VST1LNq8Pseudo: 1868 case ARM::VST1LNq16Pseudo: 1869 case ARM::VST1LNq32Pseudo: 1870 case ARM::VST1LNq8Pseudo_UPD: 1871 case ARM::VST1LNq16Pseudo_UPD: 1872 case ARM::VST1LNq32Pseudo_UPD: 1873 case ARM::VST2LNd8Pseudo: 1874 case ARM::VST2LNd16Pseudo: 1875 case ARM::VST2LNd32Pseudo: 1876 case ARM::VST2LNq16Pseudo: 1877 case ARM::VST2LNq32Pseudo: 1878 case ARM::VST2LNd8Pseudo_UPD: 1879 case ARM::VST2LNd16Pseudo_UPD: 1880 case ARM::VST2LNd32Pseudo_UPD: 1881 case ARM::VST2LNq16Pseudo_UPD: 1882 case ARM::VST2LNq32Pseudo_UPD: 1883 case ARM::VST3LNd8Pseudo: 1884 case ARM::VST3LNd16Pseudo: 1885 case ARM::VST3LNd32Pseudo: 1886 case ARM::VST3LNq16Pseudo: 1887 case ARM::VST3LNq32Pseudo: 1888 case ARM::VST3LNd8Pseudo_UPD: 1889 case ARM::VST3LNd16Pseudo_UPD: 1890 case ARM::VST3LNd32Pseudo_UPD: 1891 case ARM::VST3LNq16Pseudo_UPD: 1892 case ARM::VST3LNq32Pseudo_UPD: 1893 case ARM::VST4LNd8Pseudo: 1894 case ARM::VST4LNd16Pseudo: 1895 case ARM::VST4LNd32Pseudo: 1896 case ARM::VST4LNq16Pseudo: 1897 case ARM::VST4LNq32Pseudo: 1898 case ARM::VST4LNd8Pseudo_UPD: 1899 case ARM::VST4LNd16Pseudo_UPD: 1900 case ARM::VST4LNd32Pseudo_UPD: 1901 case ARM::VST4LNq16Pseudo_UPD: 1902 case ARM::VST4LNq32Pseudo_UPD: 1903 ExpandLaneOp(MBBI); 1904 return true; 1905 1906 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; 1907 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; 1908 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; 1909 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; 1910 1911 case ARM::CMP_SWAP_8: 1912 if (STI->isThumb()) 1913 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, 1914 ARM::tUXTB, NextMBBI); 1915 else 1916 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, 1917 ARM::UXTB, NextMBBI); 1918 case ARM::CMP_SWAP_16: 1919 if (STI->isThumb()) 1920 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, 1921 ARM::tUXTH, NextMBBI); 1922 else 1923 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, 1924 ARM::UXTH, NextMBBI); 1925 case ARM::CMP_SWAP_32: 1926 if (STI->isThumb()) 1927 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, 1928 NextMBBI); 1929 else 1930 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); 1931 1932 case ARM::CMP_SWAP_64: 1933 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI); 1934 1935 case ARM::tBL_PUSHLR: 1936 case ARM::BL_PUSHLR: { 1937 const bool Thumb = Opcode == ARM::tBL_PUSHLR; 1938 Register Reg = MI.getOperand(0).getReg(); 1939 assert(Reg == ARM::LR && "expect LR register!"); 1940 MachineInstrBuilder MIB; 1941 if (Thumb) { 1942 // push {lr} 1943 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH)) 1944 .add(predOps(ARMCC::AL)) 1945 .addReg(Reg); 1946 1947 // bl __gnu_mcount_nc 1948 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL)); 1949 } else { 1950 // stmdb sp!, {lr} 1951 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD)) 1952 .addReg(ARM::SP, RegState::Define) 1953 .addReg(ARM::SP) 1954 .add(predOps(ARMCC::AL)) 1955 .addReg(Reg); 1956 1957 // bl __gnu_mcount_nc 1958 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL)); 1959 } 1960 MIB.cloneMemRefs(MI); 1961 for (unsigned i = 1; i < MI.getNumOperands(); ++i) MIB.add(MI.getOperand(i)); 1962 MI.eraseFromParent(); 1963 return true; 1964 } 1965 case ARM::LOADDUAL: 1966 case ARM::STOREDUAL: { 1967 Register PairReg = MI.getOperand(0).getReg(); 1968 1969 MachineInstrBuilder MIB = 1970 BuildMI(MBB, MBBI, MI.getDebugLoc(), 1971 TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD)) 1972 .addReg(TRI->getSubReg(PairReg, ARM::gsub_0), 1973 Opcode == ARM::LOADDUAL ? RegState::Define : 0) 1974 .addReg(TRI->getSubReg(PairReg, ARM::gsub_1), 1975 Opcode == ARM::LOADDUAL ? RegState::Define : 0); 1976 for (unsigned i = 1; i < MI.getNumOperands(); i++) 1977 MIB.add(MI.getOperand(i)); 1978 MIB.add(predOps(ARMCC::AL)); 1979 MIB.cloneMemRefs(MI); 1980 MI.eraseFromParent(); 1981 return true; 1982 } 1983 } 1984 } 1985 1986 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 1987 bool Modified = false; 1988 1989 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 1990 while (MBBI != E) { 1991 MachineBasicBlock::iterator NMBBI = std::next(MBBI); 1992 Modified |= ExpandMI(MBB, MBBI, NMBBI); 1993 MBBI = NMBBI; 1994 } 1995 1996 return Modified; 1997 } 1998 1999 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 2000 STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget()); 2001 TII = STI->getInstrInfo(); 2002 TRI = STI->getRegisterInfo(); 2003 AFI = MF.getInfo<ARMFunctionInfo>(); 2004 2005 LLVM_DEBUG(dbgs() << "********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n" 2006 << "********** Function: " << MF.getName() << '\n'); 2007 2008 bool Modified = false; 2009 for (MachineBasicBlock &MBB : MF) 2010 Modified |= ExpandMBB(MBB); 2011 if (VerifyARMPseudo) 2012 MF.verify(this, "After expanding ARM pseudo instructions."); 2013 2014 LLVM_DEBUG(dbgs() << "***************************************************\n"); 2015 return Modified; 2016 } 2017 2018 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction 2019 /// expansion pass. 2020 FunctionPass *llvm::createARMExpandPseudoPass() { 2021 return new ARMExpandPseudo(); 2022 } 2023