1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains a pass that expands pseudo instructions into target 10 // instructions to allow proper scheduling, if-conversion, and other late 11 // optimizations. This pass should be run after register allocation but before 12 // the post-regalloc scheduling pass. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "ARM.h" 17 #include "ARMBaseInstrInfo.h" 18 #include "ARMBaseRegisterInfo.h" 19 #include "ARMConstantPoolValue.h" 20 #include "ARMMachineFunctionInfo.h" 21 #include "ARMSubtarget.h" 22 #include "MCTargetDesc/ARMAddressingModes.h" 23 #include "llvm/CodeGen/LivePhysRegs.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunctionPass.h" 26 #include "llvm/Support/Debug.h" 27 28 using namespace llvm; 29 30 #define DEBUG_TYPE "arm-pseudo" 31 32 static cl::opt<bool> 33 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, 34 cl::desc("Verify machine code after expanding ARM pseudos")); 35 36 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass" 37 38 namespace { 39 class ARMExpandPseudo : public MachineFunctionPass { 40 public: 41 static char ID; 42 ARMExpandPseudo() : MachineFunctionPass(ID) {} 43 44 const ARMBaseInstrInfo *TII; 45 const TargetRegisterInfo *TRI; 46 const ARMSubtarget *STI; 47 ARMFunctionInfo *AFI; 48 49 bool runOnMachineFunction(MachineFunction &Fn) override; 50 51 MachineFunctionProperties getRequiredProperties() const override { 52 return MachineFunctionProperties().set( 53 MachineFunctionProperties::Property::NoVRegs); 54 } 55 56 StringRef getPassName() const override { 57 return ARM_EXPAND_PSEUDO_NAME; 58 } 59 60 private: 61 void TransferImpOps(MachineInstr &OldMI, 62 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 63 bool ExpandMI(MachineBasicBlock &MBB, 64 MachineBasicBlock::iterator MBBI, 65 MachineBasicBlock::iterator &NextMBBI); 66 bool ExpandMBB(MachineBasicBlock &MBB); 67 void ExpandVLD(MachineBasicBlock::iterator &MBBI); 68 void ExpandVST(MachineBasicBlock::iterator &MBBI); 69 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 70 void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 71 unsigned Opc, bool IsExt); 72 void ExpandMOV32BitImm(MachineBasicBlock &MBB, 73 MachineBasicBlock::iterator &MBBI); 74 void CMSEClearGPRegs(MachineBasicBlock &MBB, 75 MachineBasicBlock::iterator MBBI, const DebugLoc &DL, 76 const SmallVectorImpl<unsigned> &ClearRegs, 77 unsigned ClobberReg); 78 MachineBasicBlock &CMSEClearFPRegs(MachineBasicBlock &MBB, 79 MachineBasicBlock::iterator MBBI); 80 MachineBasicBlock &CMSEClearFPRegsV8(MachineBasicBlock &MBB, 81 MachineBasicBlock::iterator MBBI, 82 const BitVector &ClearRegs); 83 MachineBasicBlock &CMSEClearFPRegsV81(MachineBasicBlock &MBB, 84 MachineBasicBlock::iterator MBBI, 85 const BitVector &ClearRegs); 86 void CMSESaveClearFPRegs(MachineBasicBlock &MBB, 87 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 88 const LivePhysRegs &LiveRegs, 89 SmallVectorImpl<unsigned> &AvailableRegs); 90 void CMSESaveClearFPRegsV8(MachineBasicBlock &MBB, 91 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 92 const LivePhysRegs &LiveRegs, 93 SmallVectorImpl<unsigned> &ScratchRegs); 94 void CMSESaveClearFPRegsV81(MachineBasicBlock &MBB, 95 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 96 const LivePhysRegs &LiveRegs); 97 void CMSERestoreFPRegs(MachineBasicBlock &MBB, 98 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 99 SmallVectorImpl<unsigned> &AvailableRegs); 100 void CMSERestoreFPRegsV8(MachineBasicBlock &MBB, 101 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 102 SmallVectorImpl<unsigned> &AvailableRegs); 103 void CMSERestoreFPRegsV81(MachineBasicBlock &MBB, 104 MachineBasicBlock::iterator MBBI, DebugLoc &DL, 105 SmallVectorImpl<unsigned> &AvailableRegs); 106 bool ExpandCMP_SWAP(MachineBasicBlock &MBB, 107 MachineBasicBlock::iterator MBBI, unsigned LdrexOp, 108 unsigned StrexOp, unsigned UxtOp, 109 MachineBasicBlock::iterator &NextMBBI); 110 111 bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB, 112 MachineBasicBlock::iterator MBBI, 113 MachineBasicBlock::iterator &NextMBBI); 114 }; 115 char ARMExpandPseudo::ID = 0; 116 } 117 118 INITIALIZE_PASS(ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false, 119 false) 120 121 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to 122 /// the instructions created from the expansion. 123 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 124 MachineInstrBuilder &UseMI, 125 MachineInstrBuilder &DefMI) { 126 const MCInstrDesc &Desc = OldMI.getDesc(); 127 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); 128 i != e; ++i) { 129 const MachineOperand &MO = OldMI.getOperand(i); 130 assert(MO.isReg() && MO.getReg()); 131 if (MO.isUse()) 132 UseMI.add(MO); 133 else 134 DefMI.add(MO); 135 } 136 } 137 138 namespace { 139 // Constants for register spacing in NEON load/store instructions. 140 // For quad-register load-lane and store-lane pseudo instructors, the 141 // spacing is initially assumed to be EvenDblSpc, and that is changed to 142 // OddDblSpc depending on the lane number operand. 143 enum NEONRegSpacing { 144 SingleSpc, 145 SingleLowSpc , // Single spacing, low registers, three and four vectors. 146 SingleHighQSpc, // Single spacing, high registers, four vectors. 147 SingleHighTSpc, // Single spacing, high registers, three vectors. 148 EvenDblSpc, 149 OddDblSpc 150 }; 151 152 // Entries for NEON load/store information table. The table is sorted by 153 // PseudoOpc for fast binary-search lookups. 154 struct NEONLdStTableEntry { 155 uint16_t PseudoOpc; 156 uint16_t RealOpc; 157 bool IsLoad; 158 bool isUpdating; 159 bool hasWritebackOperand; 160 uint8_t RegSpacing; // One of type NEONRegSpacing 161 uint8_t NumRegs; // D registers loaded or stored 162 uint8_t RegElts; // elements per D register; used for lane ops 163 // FIXME: Temporary flag to denote whether the real instruction takes 164 // a single register (like the encoding) or all of the registers in 165 // the list (like the asm syntax and the isel DAG). When all definitions 166 // are converted to take only the single encoded register, this will 167 // go away. 168 bool copyAllListRegs; 169 170 // Comparison methods for binary search of the table. 171 bool operator<(const NEONLdStTableEntry &TE) const { 172 return PseudoOpc < TE.PseudoOpc; 173 } 174 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 175 return TE.PseudoOpc < PseudoOpc; 176 } 177 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 178 const NEONLdStTableEntry &TE) { 179 return PseudoOpc < TE.PseudoOpc; 180 } 181 }; 182 } 183 184 static const NEONLdStTableEntry NEONLdStTable[] = { 185 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true}, 186 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true}, 187 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}, 188 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true}, 189 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true}, 190 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true}, 191 192 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false}, 193 { ARM::VLD1d16QPseudoWB_fixed, ARM::VLD1d16Qwb_fixed, true, true, false, SingleSpc, 4, 4 ,false}, 194 { ARM::VLD1d16QPseudoWB_register, ARM::VLD1d16Qwb_register, true, true, true, SingleSpc, 4, 4 ,false}, 195 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false}, 196 { ARM::VLD1d16TPseudoWB_fixed, ARM::VLD1d16Twb_fixed, true, true, false, SingleSpc, 3, 4 ,false}, 197 { ARM::VLD1d16TPseudoWB_register, ARM::VLD1d16Twb_register, true, true, true, SingleSpc, 3, 4 ,false}, 198 199 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false}, 200 { ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d32Qwb_fixed, true, true, false, SingleSpc, 4, 2 ,false}, 201 { ARM::VLD1d32QPseudoWB_register, ARM::VLD1d32Qwb_register, true, true, true, SingleSpc, 4, 2 ,false}, 202 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false}, 203 { ARM::VLD1d32TPseudoWB_fixed, ARM::VLD1d32Twb_fixed, true, true, false, SingleSpc, 3, 2 ,false}, 204 { ARM::VLD1d32TPseudoWB_register, ARM::VLD1d32Twb_register, true, true, true, SingleSpc, 3, 2 ,false}, 205 206 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false}, 207 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false}, 208 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 ,false}, 209 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false}, 210 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false}, 211 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,false}, 212 213 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false}, 214 { ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d8Qwb_fixed, true, true, false, SingleSpc, 4, 8 ,false}, 215 { ARM::VLD1d8QPseudoWB_register, ARM::VLD1d8Qwb_register, true, true, true, SingleSpc, 4, 8 ,false}, 216 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false}, 217 { ARM::VLD1d8TPseudoWB_fixed, ARM::VLD1d8Twb_fixed, true, true, false, SingleSpc, 3, 8 ,false}, 218 { ARM::VLD1d8TPseudoWB_register, ARM::VLD1d8Twb_register, true, true, true, SingleSpc, 3, 8 ,false}, 219 220 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false}, 221 { ARM::VLD1q16HighQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleHighQSpc, 4, 4 ,false}, 222 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false}, 223 { ARM::VLD1q16HighTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleHighTSpc, 3, 4 ,false}, 224 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,false}, 225 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,false}, 226 227 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false}, 228 { ARM::VLD1q32HighQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleHighQSpc, 4, 2 ,false}, 229 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false}, 230 { ARM::VLD1q32HighTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleHighTSpc, 3, 2 ,false}, 231 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,false}, 232 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,false}, 233 234 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false}, 235 { ARM::VLD1q64HighQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleHighQSpc, 4, 1 ,false}, 236 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false}, 237 { ARM::VLD1q64HighTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleHighTSpc, 3, 1 ,false}, 238 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,false}, 239 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,false}, 240 241 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false}, 242 { ARM::VLD1q8HighQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleHighQSpc, 4, 8 ,false}, 243 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false}, 244 { ARM::VLD1q8HighTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleHighTSpc, 3, 8 ,false}, 245 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false}, 246 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false}, 247 248 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false}, 249 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false}, 250 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false}, 251 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false}, 252 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false}, 253 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false}, 254 255 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, 256 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true}, 257 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true}, 258 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true}, 259 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true}, 260 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true}, 261 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true}, 262 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true}, 263 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true}, 264 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true}, 265 266 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false}, 267 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false}, 268 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false}, 269 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false}, 270 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false}, 271 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false}, 272 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false}, 273 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false}, 274 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false}, 275 276 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true}, 277 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true}, 278 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true}, 279 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true}, 280 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true}, 281 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true}, 282 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 283 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true}, 284 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 285 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true}, 286 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true}, 287 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true}, 288 289 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true}, 290 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 291 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true}, 292 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 293 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true}, 294 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 295 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 296 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 297 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 298 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 299 300 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true}, 301 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 302 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true}, 303 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 304 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true}, 305 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 306 307 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 308 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true}, 309 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true}, 310 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 311 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true}, 312 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true}, 313 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true}, 314 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true}, 315 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true}, 316 317 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true}, 318 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true}, 319 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true}, 320 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true}, 321 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true}, 322 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true}, 323 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 324 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true}, 325 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 326 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true}, 327 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true}, 328 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true}, 329 330 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true}, 331 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 332 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true}, 333 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 334 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true}, 335 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 336 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 337 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 338 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 339 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 340 341 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true}, 342 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 343 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true}, 344 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 345 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true}, 346 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 347 348 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 349 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true}, 350 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true}, 351 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 352 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true}, 353 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true}, 354 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true}, 355 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true}, 356 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true}, 357 358 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true}, 359 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true}, 360 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true}, 361 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true}, 362 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true}, 363 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true}, 364 365 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false}, 366 { ARM::VST1d16QPseudoWB_fixed, ARM::VST1d16Qwb_fixed, false, true, false, SingleSpc, 4, 4 ,false}, 367 { ARM::VST1d16QPseudoWB_register, ARM::VST1d16Qwb_register, false, true, true, SingleSpc, 4, 4 ,false}, 368 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false}, 369 { ARM::VST1d16TPseudoWB_fixed, ARM::VST1d16Twb_fixed, false, true, false, SingleSpc, 3, 4 ,false}, 370 { ARM::VST1d16TPseudoWB_register, ARM::VST1d16Twb_register, false, true, true, SingleSpc, 3, 4 ,false}, 371 372 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false}, 373 { ARM::VST1d32QPseudoWB_fixed, ARM::VST1d32Qwb_fixed, false, true, false, SingleSpc, 4, 2 ,false}, 374 { ARM::VST1d32QPseudoWB_register, ARM::VST1d32Qwb_register, false, true, true, SingleSpc, 4, 2 ,false}, 375 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false}, 376 { ARM::VST1d32TPseudoWB_fixed, ARM::VST1d32Twb_fixed, false, true, false, SingleSpc, 3, 2 ,false}, 377 { ARM::VST1d32TPseudoWB_register, ARM::VST1d32Twb_register, false, true, true, SingleSpc, 3, 2 ,false}, 378 379 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false}, 380 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false}, 381 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false}, 382 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false}, 383 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false}, 384 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false}, 385 386 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false}, 387 { ARM::VST1d8QPseudoWB_fixed, ARM::VST1d8Qwb_fixed, false, true, false, SingleSpc, 4, 8 ,false}, 388 { ARM::VST1d8QPseudoWB_register, ARM::VST1d8Qwb_register, false, true, true, SingleSpc, 4, 8 ,false}, 389 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false}, 390 { ARM::VST1d8TPseudoWB_fixed, ARM::VST1d8Twb_fixed, false, true, false, SingleSpc, 3, 8 ,false}, 391 { ARM::VST1d8TPseudoWB_register, ARM::VST1d8Twb_register, false, true, true, SingleSpc, 3, 8 ,false}, 392 393 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false}, 394 { ARM::VST1q16HighQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false}, 395 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false}, 396 { ARM::VST1q16HighTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleHighTSpc, 3, 4 ,false}, 397 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,false}, 398 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,false}, 399 400 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false}, 401 { ARM::VST1q32HighQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false}, 402 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false}, 403 { ARM::VST1q32HighTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleHighTSpc, 3, 2 ,false}, 404 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,false}, 405 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,false}, 406 407 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false}, 408 { ARM::VST1q64HighQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false}, 409 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false}, 410 { ARM::VST1q64HighTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleHighTSpc, 3, 1 ,false}, 411 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,false}, 412 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,false}, 413 414 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false}, 415 { ARM::VST1q8HighQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false}, 416 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false}, 417 { ARM::VST1q8HighTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleHighTSpc, 3, 8 ,false}, 418 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,false}, 419 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,false}, 420 421 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true}, 422 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true}, 423 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true}, 424 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true}, 425 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true}, 426 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true}, 427 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true}, 428 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true}, 429 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true}, 430 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true}, 431 432 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false}, 433 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false}, 434 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false}, 435 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false}, 436 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false}, 437 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false}, 438 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false}, 439 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false}, 440 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false}, 441 442 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true}, 443 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 444 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true}, 445 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 446 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true}, 447 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 448 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true}, 449 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true}, 450 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true}, 451 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true}, 452 453 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true}, 454 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 455 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true}, 456 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 457 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true}, 458 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 459 460 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true}, 461 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true}, 462 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true}, 463 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true}, 464 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true}, 465 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true}, 466 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true}, 467 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true}, 468 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true}, 469 470 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true}, 471 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 472 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true}, 473 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 474 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true}, 475 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 476 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true}, 477 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true}, 478 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true}, 479 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true}, 480 481 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true}, 482 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 483 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true}, 484 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 485 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true}, 486 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 487 488 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true}, 489 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true}, 490 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true}, 491 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true}, 492 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true}, 493 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true}, 494 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true}, 495 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true}, 496 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true} 497 }; 498 499 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 500 /// load or store pseudo instruction. 501 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 502 #ifndef NDEBUG 503 // Make sure the table is sorted. 504 static std::atomic<bool> TableChecked(false); 505 if (!TableChecked.load(std::memory_order_relaxed)) { 506 assert(llvm::is_sorted(NEONLdStTable) && "NEONLdStTable is not sorted!"); 507 TableChecked.store(true, std::memory_order_relaxed); 508 } 509 #endif 510 511 auto I = llvm::lower_bound(NEONLdStTable, Opcode); 512 if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode) 513 return I; 514 return nullptr; 515 } 516 517 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 518 /// corresponding to the specified register spacing. Not all of the results 519 /// are necessarily valid, e.g., a Q register only has 2 D subregisters. 520 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 521 const TargetRegisterInfo *TRI, unsigned &D0, 522 unsigned &D1, unsigned &D2, unsigned &D3) { 523 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) { 524 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 525 D1 = TRI->getSubReg(Reg, ARM::dsub_1); 526 D2 = TRI->getSubReg(Reg, ARM::dsub_2); 527 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 528 } else if (RegSpc == SingleHighQSpc) { 529 D0 = TRI->getSubReg(Reg, ARM::dsub_4); 530 D1 = TRI->getSubReg(Reg, ARM::dsub_5); 531 D2 = TRI->getSubReg(Reg, ARM::dsub_6); 532 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 533 } else if (RegSpc == SingleHighTSpc) { 534 D0 = TRI->getSubReg(Reg, ARM::dsub_3); 535 D1 = TRI->getSubReg(Reg, ARM::dsub_4); 536 D2 = TRI->getSubReg(Reg, ARM::dsub_5); 537 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 538 } else if (RegSpc == EvenDblSpc) { 539 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 540 D1 = TRI->getSubReg(Reg, ARM::dsub_2); 541 D2 = TRI->getSubReg(Reg, ARM::dsub_4); 542 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 543 } else { 544 assert(RegSpc == OddDblSpc && "unknown register spacing"); 545 D0 = TRI->getSubReg(Reg, ARM::dsub_1); 546 D1 = TRI->getSubReg(Reg, ARM::dsub_3); 547 D2 = TRI->getSubReg(Reg, ARM::dsub_5); 548 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 549 } 550 } 551 552 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 553 /// operands to real VLD instructions with D register operands. 554 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 555 MachineInstr &MI = *MBBI; 556 MachineBasicBlock &MBB = *MI.getParent(); 557 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 558 559 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 560 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 561 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 562 unsigned NumRegs = TableEntry->NumRegs; 563 564 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 565 TII->get(TableEntry->RealOpc)); 566 unsigned OpIdx = 0; 567 568 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 569 Register DstReg = MI.getOperand(OpIdx++).getReg(); 570 if(TableEntry->RealOpc == ARM::VLD2DUPd8x2 || 571 TableEntry->RealOpc == ARM::VLD2DUPd16x2 || 572 TableEntry->RealOpc == ARM::VLD2DUPd32x2) { 573 unsigned SubRegIndex; 574 if (RegSpc == EvenDblSpc) { 575 SubRegIndex = ARM::dsub_0; 576 } else { 577 assert(RegSpc == OddDblSpc && "Unexpected spacing!"); 578 SubRegIndex = ARM::dsub_1; 579 } 580 Register SubReg = TRI->getSubReg(DstReg, SubRegIndex); 581 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0, 582 &ARM::DPairSpcRegClass); 583 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); 584 } else { 585 unsigned D0, D1, D2, D3; 586 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 587 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 588 if (NumRegs > 1 && TableEntry->copyAllListRegs) 589 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 590 if (NumRegs > 2 && TableEntry->copyAllListRegs) 591 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 592 if (NumRegs > 3 && TableEntry->copyAllListRegs) 593 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 594 } 595 596 if (TableEntry->isUpdating) 597 MIB.add(MI.getOperand(OpIdx++)); 598 599 // Copy the addrmode6 operands. 600 MIB.add(MI.getOperand(OpIdx++)); 601 MIB.add(MI.getOperand(OpIdx++)); 602 603 // Copy the am6offset operand. 604 if (TableEntry->hasWritebackOperand) { 605 // TODO: The writing-back pseudo instructions we translate here are all 606 // defined to take am6offset nodes that are capable to represent both fixed 607 // and register forms. Some real instructions, however, do not rely on 608 // am6offset and have separate definitions for such forms. When this is the 609 // case, fixed forms do not take any offset nodes, so here we skip them for 610 // such instructions. Once all real and pseudo writing-back instructions are 611 // rewritten without use of am6offset nodes, this code will go away. 612 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++); 613 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed || 614 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed || 615 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed || 616 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed || 617 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed || 618 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed || 619 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed || 620 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed) { 621 assert(AM6Offset.getReg() == 0 && 622 "A fixed writing-back pseudo instruction provides an offset " 623 "register!"); 624 } else { 625 MIB.add(AM6Offset); 626 } 627 } 628 629 // For an instruction writing double-spaced subregs, the pseudo instruction 630 // has an extra operand that is a use of the super-register. Record the 631 // operand index and skip over it. 632 unsigned SrcOpIdx = 0; 633 if(TableEntry->RealOpc != ARM::VLD2DUPd8x2 && 634 TableEntry->RealOpc != ARM::VLD2DUPd16x2 && 635 TableEntry->RealOpc != ARM::VLD2DUPd32x2) { 636 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc || 637 RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || 638 RegSpc == SingleHighTSpc) 639 SrcOpIdx = OpIdx++; 640 } 641 642 // Copy the predicate operands. 643 MIB.add(MI.getOperand(OpIdx++)); 644 MIB.add(MI.getOperand(OpIdx++)); 645 646 // Copy the super-register source operand used for double-spaced subregs over 647 // to the new instruction as an implicit operand. 648 if (SrcOpIdx != 0) { 649 MachineOperand MO = MI.getOperand(SrcOpIdx); 650 MO.setImplicit(true); 651 MIB.add(MO); 652 } 653 // Add an implicit def for the super-register. 654 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 655 TransferImpOps(MI, MIB, MIB); 656 657 // Transfer memoperands. 658 MIB.cloneMemRefs(MI); 659 MI.eraseFromParent(); 660 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 661 } 662 663 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 664 /// operands to real VST instructions with D register operands. 665 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 666 MachineInstr &MI = *MBBI; 667 MachineBasicBlock &MBB = *MI.getParent(); 668 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 669 670 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 671 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 672 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 673 unsigned NumRegs = TableEntry->NumRegs; 674 675 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 676 TII->get(TableEntry->RealOpc)); 677 unsigned OpIdx = 0; 678 if (TableEntry->isUpdating) 679 MIB.add(MI.getOperand(OpIdx++)); 680 681 // Copy the addrmode6 operands. 682 MIB.add(MI.getOperand(OpIdx++)); 683 MIB.add(MI.getOperand(OpIdx++)); 684 685 if (TableEntry->hasWritebackOperand) { 686 // TODO: The writing-back pseudo instructions we translate here are all 687 // defined to take am6offset nodes that are capable to represent both fixed 688 // and register forms. Some real instructions, however, do not rely on 689 // am6offset and have separate definitions for such forms. When this is the 690 // case, fixed forms do not take any offset nodes, so here we skip them for 691 // such instructions. Once all real and pseudo writing-back instructions are 692 // rewritten without use of am6offset nodes, this code will go away. 693 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++); 694 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed || 695 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed || 696 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed || 697 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed || 698 TableEntry->RealOpc == ARM::VST1d8Twb_fixed || 699 TableEntry->RealOpc == ARM::VST1d16Twb_fixed || 700 TableEntry->RealOpc == ARM::VST1d32Twb_fixed || 701 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) { 702 assert(AM6Offset.getReg() == 0 && 703 "A fixed writing-back pseudo instruction provides an offset " 704 "register!"); 705 } else { 706 MIB.add(AM6Offset); 707 } 708 } 709 710 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 711 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef(); 712 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 713 unsigned D0, D1, D2, D3; 714 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 715 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); 716 if (NumRegs > 1 && TableEntry->copyAllListRegs) 717 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); 718 if (NumRegs > 2 && TableEntry->copyAllListRegs) 719 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); 720 if (NumRegs > 3 && TableEntry->copyAllListRegs) 721 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); 722 723 // Copy the predicate operands. 724 MIB.add(MI.getOperand(OpIdx++)); 725 MIB.add(MI.getOperand(OpIdx++)); 726 727 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg. 728 MIB->addRegisterKilled(SrcReg, TRI, true); 729 else if (!SrcIsUndef) 730 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. 731 TransferImpOps(MI, MIB, MIB); 732 733 // Transfer memoperands. 734 MIB.cloneMemRefs(MI); 735 MI.eraseFromParent(); 736 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 737 } 738 739 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 740 /// register operands to real instructions with D register operands. 741 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 742 MachineInstr &MI = *MBBI; 743 MachineBasicBlock &MBB = *MI.getParent(); 744 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 745 746 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 747 assert(TableEntry && "NEONLdStTable lookup failed"); 748 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 749 unsigned NumRegs = TableEntry->NumRegs; 750 unsigned RegElts = TableEntry->RegElts; 751 752 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 753 TII->get(TableEntry->RealOpc)); 754 unsigned OpIdx = 0; 755 // The lane operand is always the 3rd from last operand, before the 2 756 // predicate operands. 757 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 758 759 // Adjust the lane and spacing as needed for Q registers. 760 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 761 if (RegSpc == EvenDblSpc && Lane >= RegElts) { 762 RegSpc = OddDblSpc; 763 Lane -= RegElts; 764 } 765 assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 766 767 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; 768 unsigned DstReg = 0; 769 bool DstIsDead = false; 770 if (TableEntry->IsLoad) { 771 DstIsDead = MI.getOperand(OpIdx).isDead(); 772 DstReg = MI.getOperand(OpIdx++).getReg(); 773 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 774 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 775 if (NumRegs > 1) 776 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 777 if (NumRegs > 2) 778 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 779 if (NumRegs > 3) 780 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 781 } 782 783 if (TableEntry->isUpdating) 784 MIB.add(MI.getOperand(OpIdx++)); 785 786 // Copy the addrmode6 operands. 787 MIB.add(MI.getOperand(OpIdx++)); 788 MIB.add(MI.getOperand(OpIdx++)); 789 // Copy the am6offset operand. 790 if (TableEntry->hasWritebackOperand) 791 MIB.add(MI.getOperand(OpIdx++)); 792 793 // Grab the super-register source. 794 MachineOperand MO = MI.getOperand(OpIdx++); 795 if (!TableEntry->IsLoad) 796 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 797 798 // Add the subregs as sources of the new instruction. 799 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 800 getKillRegState(MO.isKill())); 801 MIB.addReg(D0, SrcFlags); 802 if (NumRegs > 1) 803 MIB.addReg(D1, SrcFlags); 804 if (NumRegs > 2) 805 MIB.addReg(D2, SrcFlags); 806 if (NumRegs > 3) 807 MIB.addReg(D3, SrcFlags); 808 809 // Add the lane number operand. 810 MIB.addImm(Lane); 811 OpIdx += 1; 812 813 // Copy the predicate operands. 814 MIB.add(MI.getOperand(OpIdx++)); 815 MIB.add(MI.getOperand(OpIdx++)); 816 817 // Copy the super-register source to be an implicit source. 818 MO.setImplicit(true); 819 MIB.add(MO); 820 if (TableEntry->IsLoad) 821 // Add an implicit def for the super-register. 822 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 823 TransferImpOps(MI, MIB, MIB); 824 // Transfer memoperands. 825 MIB.cloneMemRefs(MI); 826 MI.eraseFromParent(); 827 } 828 829 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 830 /// register operands to real instructions with D register operands. 831 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 832 unsigned Opc, bool IsExt) { 833 MachineInstr &MI = *MBBI; 834 MachineBasicBlock &MBB = *MI.getParent(); 835 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 836 837 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 838 unsigned OpIdx = 0; 839 840 // Transfer the destination register operand. 841 MIB.add(MI.getOperand(OpIdx++)); 842 if (IsExt) { 843 MachineOperand VdSrc(MI.getOperand(OpIdx++)); 844 MIB.add(VdSrc); 845 } 846 847 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 848 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 849 unsigned D0, D1, D2, D3; 850 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 851 MIB.addReg(D0); 852 853 // Copy the other source register operand. 854 MachineOperand VmSrc(MI.getOperand(OpIdx++)); 855 MIB.add(VmSrc); 856 857 // Copy the predicate operands. 858 MIB.add(MI.getOperand(OpIdx++)); 859 MIB.add(MI.getOperand(OpIdx++)); 860 861 // Add an implicit kill and use for the super-reg. 862 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); 863 TransferImpOps(MI, MIB, MIB); 864 MI.eraseFromParent(); 865 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); 866 } 867 868 static bool IsAnAddressOperand(const MachineOperand &MO) { 869 // This check is overly conservative. Unless we are certain that the machine 870 // operand is not a symbol reference, we return that it is a symbol reference. 871 // This is important as the load pair may not be split up Windows. 872 switch (MO.getType()) { 873 case MachineOperand::MO_Register: 874 case MachineOperand::MO_Immediate: 875 case MachineOperand::MO_CImmediate: 876 case MachineOperand::MO_FPImmediate: 877 case MachineOperand::MO_ShuffleMask: 878 return false; 879 case MachineOperand::MO_MachineBasicBlock: 880 return true; 881 case MachineOperand::MO_FrameIndex: 882 return false; 883 case MachineOperand::MO_ConstantPoolIndex: 884 case MachineOperand::MO_TargetIndex: 885 case MachineOperand::MO_JumpTableIndex: 886 case MachineOperand::MO_ExternalSymbol: 887 case MachineOperand::MO_GlobalAddress: 888 case MachineOperand::MO_BlockAddress: 889 return true; 890 case MachineOperand::MO_RegisterMask: 891 case MachineOperand::MO_RegisterLiveOut: 892 return false; 893 case MachineOperand::MO_Metadata: 894 case MachineOperand::MO_MCSymbol: 895 return true; 896 case MachineOperand::MO_CFIIndex: 897 return false; 898 case MachineOperand::MO_IntrinsicID: 899 case MachineOperand::MO_Predicate: 900 llvm_unreachable("should not exist post-isel"); 901 } 902 llvm_unreachable("unhandled machine operand type"); 903 } 904 905 static MachineOperand makeImplicit(const MachineOperand &MO) { 906 MachineOperand NewMO = MO; 907 NewMO.setImplicit(); 908 return NewMO; 909 } 910 911 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, 912 MachineBasicBlock::iterator &MBBI) { 913 MachineInstr &MI = *MBBI; 914 unsigned Opcode = MI.getOpcode(); 915 Register PredReg; 916 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 917 Register DstReg = MI.getOperand(0).getReg(); 918 bool DstIsDead = MI.getOperand(0).isDead(); 919 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; 920 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); 921 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO); 922 MachineInstrBuilder LO16, HI16; 923 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump()); 924 925 if (!STI->hasV6T2Ops() && 926 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { 927 // FIXME Windows CE supports older ARM CPUs 928 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+"); 929 930 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); 931 unsigned ImmVal = (unsigned)MO.getImm(); 932 unsigned SOImmValV1 = 0, SOImmValV2 = 0; 933 934 if (ARM_AM::isSOImmTwoPartVal(ImmVal)) { // Expand into a movi + orr. 935 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 936 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) 937 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 938 .addReg(DstReg); 939 SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 940 SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 941 } else { // Expand into a mvn + sub. 942 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg); 943 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri)) 944 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 945 .addReg(DstReg); 946 SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(-ImmVal); 947 SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(-ImmVal); 948 SOImmValV1 = ~(-SOImmValV1); 949 } 950 951 unsigned MIFlags = MI.getFlags(); 952 LO16 = LO16.addImm(SOImmValV1); 953 HI16 = HI16.addImm(SOImmValV2); 954 LO16.cloneMemRefs(MI); 955 HI16.cloneMemRefs(MI); 956 LO16.setMIFlags(MIFlags); 957 HI16.setMIFlags(MIFlags); 958 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp()); 959 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp()); 960 if (isCC) 961 LO16.add(makeImplicit(MI.getOperand(1))); 962 TransferImpOps(MI, LO16, HI16); 963 MI.eraseFromParent(); 964 return; 965 } 966 967 unsigned LO16Opc = 0; 968 unsigned HI16Opc = 0; 969 unsigned MIFlags = MI.getFlags(); 970 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { 971 LO16Opc = ARM::t2MOVi16; 972 HI16Opc = ARM::t2MOVTi16; 973 } else { 974 LO16Opc = ARM::MOVi16; 975 HI16Opc = ARM::MOVTi16; 976 } 977 978 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); 979 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) 980 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 981 .addReg(DstReg); 982 983 LO16.setMIFlags(MIFlags); 984 HI16.setMIFlags(MIFlags); 985 986 switch (MO.getType()) { 987 case MachineOperand::MO_Immediate: { 988 unsigned Imm = MO.getImm(); 989 unsigned Lo16 = Imm & 0xffff; 990 unsigned Hi16 = (Imm >> 16) & 0xffff; 991 LO16 = LO16.addImm(Lo16); 992 HI16 = HI16.addImm(Hi16); 993 break; 994 } 995 case MachineOperand::MO_ExternalSymbol: { 996 const char *ES = MO.getSymbolName(); 997 unsigned TF = MO.getTargetFlags(); 998 LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16); 999 HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16); 1000 break; 1001 } 1002 default: { 1003 const GlobalValue *GV = MO.getGlobal(); 1004 unsigned TF = MO.getTargetFlags(); 1005 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 1006 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 1007 break; 1008 } 1009 } 1010 1011 LO16.cloneMemRefs(MI); 1012 HI16.cloneMemRefs(MI); 1013 LO16.addImm(Pred).addReg(PredReg); 1014 HI16.addImm(Pred).addReg(PredReg); 1015 1016 if (RequiresBundling) 1017 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator()); 1018 1019 if (isCC) 1020 LO16.add(makeImplicit(MI.getOperand(1))); 1021 TransferImpOps(MI, LO16, HI16); 1022 MI.eraseFromParent(); 1023 LLVM_DEBUG(dbgs() << "To: "; LO16.getInstr()->dump();); 1024 LLVM_DEBUG(dbgs() << "And: "; HI16.getInstr()->dump();); 1025 } 1026 1027 // The size of the area, accessed by that VLSTM/VLLDM 1028 // S0-S31 + FPSCR + 8 more bytes (VPR + pad, or just pad) 1029 static const int CMSE_FP_SAVE_SIZE = 136; 1030 1031 static void determineGPRegsToClear(const MachineInstr &MI, 1032 const std::initializer_list<unsigned> &Regs, 1033 SmallVectorImpl<unsigned> &ClearRegs) { 1034 SmallVector<unsigned, 4> OpRegs; 1035 for (const MachineOperand &Op : MI.operands()) { 1036 if (!Op.isReg() || !Op.isUse()) 1037 continue; 1038 OpRegs.push_back(Op.getReg()); 1039 } 1040 llvm::sort(OpRegs); 1041 1042 std::set_difference(Regs.begin(), Regs.end(), OpRegs.begin(), OpRegs.end(), 1043 std::back_inserter(ClearRegs)); 1044 } 1045 1046 void ARMExpandPseudo::CMSEClearGPRegs( 1047 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 1048 const DebugLoc &DL, const SmallVectorImpl<unsigned> &ClearRegs, 1049 unsigned ClobberReg) { 1050 1051 if (STI->hasV8_1MMainlineOps()) { 1052 // Clear the registers using the CLRM instruction. 1053 MachineInstrBuilder CLRM = 1054 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2CLRM)).add(predOps(ARMCC::AL)); 1055 for (unsigned R : ClearRegs) 1056 CLRM.addReg(R, RegState::Define); 1057 CLRM.addReg(ARM::APSR, RegState::Define); 1058 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); 1059 } else { 1060 // Clear the registers and flags by copying ClobberReg into them. 1061 // (Baseline can't do a high register clear in one instruction). 1062 for (unsigned Reg : ClearRegs) { 1063 if (Reg == ClobberReg) 1064 continue; 1065 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVr), Reg) 1066 .addReg(ClobberReg) 1067 .add(predOps(ARMCC::AL)); 1068 } 1069 1070 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2MSR_M)) 1071 .addImm(STI->hasDSP() ? 0xc00 : 0x800) 1072 .addReg(ClobberReg) 1073 .add(predOps(ARMCC::AL)); 1074 } 1075 } 1076 1077 // Find which FP registers need to be cleared. The parameter `ClearRegs` is 1078 // initialised with all elements set to true, and this function resets all the 1079 // bits, which correspond to register uses. Returns true if any floating point 1080 // register is defined, false otherwise. 1081 static bool determineFPRegsToClear(const MachineInstr &MI, 1082 BitVector &ClearRegs) { 1083 bool DefFP = false; 1084 for (const MachineOperand &Op : MI.operands()) { 1085 if (!Op.isReg()) 1086 continue; 1087 1088 unsigned Reg = Op.getReg(); 1089 if (Op.isDef()) { 1090 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || 1091 (Reg >= ARM::D0 && Reg <= ARM::D15) || 1092 (Reg >= ARM::S0 && Reg <= ARM::S31)) 1093 DefFP = true; 1094 continue; 1095 } 1096 1097 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) { 1098 int R = Reg - ARM::Q0; 1099 ClearRegs.reset(R * 4, (R + 1) * 4); 1100 } else if (Reg >= ARM::D0 && Reg <= ARM::D15) { 1101 int R = Reg - ARM::D0; 1102 ClearRegs.reset(R * 2, (R + 1) * 2); 1103 } else if (Reg >= ARM::S0 && Reg <= ARM::S31) { 1104 ClearRegs[Reg - ARM::S0] = false; 1105 } 1106 } 1107 return DefFP; 1108 } 1109 1110 MachineBasicBlock & 1111 ARMExpandPseudo::CMSEClearFPRegs(MachineBasicBlock &MBB, 1112 MachineBasicBlock::iterator MBBI) { 1113 BitVector ClearRegs(16, true); 1114 (void)determineFPRegsToClear(*MBBI, ClearRegs); 1115 1116 if (STI->hasV8_1MMainlineOps()) 1117 return CMSEClearFPRegsV81(MBB, MBBI, ClearRegs); 1118 else 1119 return CMSEClearFPRegsV8(MBB, MBBI, ClearRegs); 1120 } 1121 1122 // Clear the FP registers for v8.0-M, by copying over the content 1123 // of LR. Uses R12 as a scratch register. 1124 MachineBasicBlock & 1125 ARMExpandPseudo::CMSEClearFPRegsV8(MachineBasicBlock &MBB, 1126 MachineBasicBlock::iterator MBBI, 1127 const BitVector &ClearRegs) { 1128 if (!STI->hasFPRegs()) 1129 return MBB; 1130 1131 auto &RetI = *MBBI; 1132 const DebugLoc &DL = RetI.getDebugLoc(); 1133 1134 // If optimising for minimum size, clear FP registers unconditionally. 1135 // Otherwise, check the CONTROL.SFPA (Secure Floating-Point Active) bit and 1136 // don't clear them if they belong to the non-secure state. 1137 MachineBasicBlock *ClearBB, *DoneBB; 1138 if (STI->hasMinSize()) { 1139 ClearBB = DoneBB = &MBB; 1140 } else { 1141 MachineFunction *MF = MBB.getParent(); 1142 ClearBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1143 DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1144 1145 MF->insert(++MBB.getIterator(), ClearBB); 1146 MF->insert(++ClearBB->getIterator(), DoneBB); 1147 1148 DoneBB->splice(DoneBB->end(), &MBB, MBBI, MBB.end()); 1149 DoneBB->transferSuccessors(&MBB); 1150 MBB.addSuccessor(ClearBB); 1151 MBB.addSuccessor(DoneBB); 1152 ClearBB->addSuccessor(DoneBB); 1153 1154 // At the new basic blocks we need to have live-in the registers, used 1155 // for the return value as well as LR, used to clear registers. 1156 for (const MachineOperand &Op : RetI.operands()) { 1157 if (!Op.isReg()) 1158 continue; 1159 Register Reg = Op.getReg(); 1160 if (Reg == ARM::NoRegister || Reg == ARM::LR) 1161 continue; 1162 assert(Register::isPhysicalRegister(Reg) && "Unallocated register"); 1163 ClearBB->addLiveIn(Reg); 1164 DoneBB->addLiveIn(Reg); 1165 } 1166 ClearBB->addLiveIn(ARM::LR); 1167 DoneBB->addLiveIn(ARM::LR); 1168 1169 // Read the CONTROL register. 1170 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2MRS_M), ARM::R12) 1171 .addImm(20) 1172 .add(predOps(ARMCC::AL)); 1173 // Check bit 3 (SFPA). 1174 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2TSTri)) 1175 .addReg(ARM::R12) 1176 .addImm(8) 1177 .add(predOps(ARMCC::AL)); 1178 // If SFPA is clear, jump over ClearBB to DoneBB. 1179 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::tBcc)) 1180 .addMBB(DoneBB) 1181 .addImm(ARMCC::EQ) 1182 .addReg(ARM::CPSR, RegState::Kill); 1183 } 1184 1185 // Emit the clearing sequence 1186 for (unsigned D = 0; D < 8; D++) { 1187 // Attempt to clear as double 1188 if (ClearRegs[D * 2 + 0] && ClearRegs[D * 2 + 1]) { 1189 unsigned Reg = ARM::D0 + D; 1190 BuildMI(ClearBB, DL, TII->get(ARM::VMOVDRR), Reg) 1191 .addReg(ARM::LR) 1192 .addReg(ARM::LR) 1193 .add(predOps(ARMCC::AL)); 1194 } else { 1195 // Clear first part as single 1196 if (ClearRegs[D * 2 + 0]) { 1197 unsigned Reg = ARM::S0 + D * 2; 1198 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) 1199 .addReg(ARM::LR) 1200 .add(predOps(ARMCC::AL)); 1201 } 1202 // Clear second part as single 1203 if (ClearRegs[D * 2 + 1]) { 1204 unsigned Reg = ARM::S0 + D * 2 + 1; 1205 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) 1206 .addReg(ARM::LR) 1207 .add(predOps(ARMCC::AL)); 1208 } 1209 } 1210 } 1211 1212 // Clear FPSCR bits 0-4, 7, 28-31 1213 // The other bits are program global according to the AAPCS 1214 BuildMI(ClearBB, DL, TII->get(ARM::VMRS), ARM::R12) 1215 .add(predOps(ARMCC::AL)); 1216 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) 1217 .addReg(ARM::R12) 1218 .addImm(0x0000009F) 1219 .add(predOps(ARMCC::AL)) 1220 .add(condCodeOp()); 1221 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) 1222 .addReg(ARM::R12) 1223 .addImm(0xF0000000) 1224 .add(predOps(ARMCC::AL)) 1225 .add(condCodeOp()); 1226 BuildMI(ClearBB, DL, TII->get(ARM::VMSR)) 1227 .addReg(ARM::R12) 1228 .add(predOps(ARMCC::AL)); 1229 1230 return *DoneBB; 1231 } 1232 1233 MachineBasicBlock & 1234 ARMExpandPseudo::CMSEClearFPRegsV81(MachineBasicBlock &MBB, 1235 MachineBasicBlock::iterator MBBI, 1236 const BitVector &ClearRegs) { 1237 auto &RetI = *MBBI; 1238 1239 // Emit a sequence of VSCCLRM <sreglist> instructions, one instruction for 1240 // each contiguous sequence of S-registers. 1241 int Start = -1, End = -1; 1242 for (int S = 0, E = ClearRegs.size(); S != E; ++S) { 1243 if (ClearRegs[S] && S == End + 1) { 1244 End = S; // extend range 1245 continue; 1246 } 1247 // Emit current range. 1248 if (Start < End) { 1249 MachineInstrBuilder VSCCLRM = 1250 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) 1251 .add(predOps(ARMCC::AL)); 1252 while (++Start <= End) 1253 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); 1254 VSCCLRM.addReg(ARM::VPR, RegState::Define); 1255 } 1256 Start = End = S; 1257 } 1258 // Emit last range. 1259 if (Start < End) { 1260 MachineInstrBuilder VSCCLRM = 1261 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) 1262 .add(predOps(ARMCC::AL)); 1263 while (++Start <= End) 1264 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); 1265 VSCCLRM.addReg(ARM::VPR, RegState::Define); 1266 } 1267 1268 return MBB; 1269 } 1270 1271 void ARMExpandPseudo::CMSESaveClearFPRegs( 1272 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1273 const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) { 1274 if (STI->hasV8_1MMainlineOps()) 1275 CMSESaveClearFPRegsV81(MBB, MBBI, DL, LiveRegs); 1276 else 1277 CMSESaveClearFPRegsV8(MBB, MBBI, DL, LiveRegs, ScratchRegs); 1278 } 1279 1280 // Save and clear FP registers if present 1281 void ARMExpandPseudo::CMSESaveClearFPRegsV8( 1282 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1283 const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) { 1284 if (!STI->hasFPRegs()) 1285 return; 1286 1287 // Store an available register for FPSCR clearing 1288 assert(!ScratchRegs.empty()); 1289 unsigned SpareReg = ScratchRegs.front(); 1290 1291 // save space on stack for VLSTM 1292 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) 1293 .addReg(ARM::SP) 1294 .addImm(CMSE_FP_SAVE_SIZE >> 2) 1295 .add(predOps(ARMCC::AL)); 1296 1297 // Use ScratchRegs to store the fp regs 1298 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs; 1299 std::vector<unsigned> NonclearedFPRegs; 1300 for (const MachineOperand &Op : MBBI->operands()) { 1301 if (Op.isReg() && Op.isUse()) { 1302 unsigned Reg = Op.getReg(); 1303 assert(!ARM::DPRRegClass.contains(Reg) || 1304 ARM::DPR_VFP2RegClass.contains(Reg)); 1305 assert(!ARM::QPRRegClass.contains(Reg)); 1306 if (ARM::DPR_VFP2RegClass.contains(Reg)) { 1307 if (ScratchRegs.size() >= 2) { 1308 unsigned SaveReg2 = ScratchRegs.pop_back_val(); 1309 unsigned SaveReg1 = ScratchRegs.pop_back_val(); 1310 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2); 1311 1312 // Save the fp register to the normal registers 1313 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) 1314 .addReg(SaveReg1, RegState::Define) 1315 .addReg(SaveReg2, RegState::Define) 1316 .addReg(Reg) 1317 .add(predOps(ARMCC::AL)); 1318 } else { 1319 NonclearedFPRegs.push_back(Reg); 1320 } 1321 } else if (ARM::SPRRegClass.contains(Reg)) { 1322 if (ScratchRegs.size() >= 1) { 1323 unsigned SaveReg = ScratchRegs.pop_back_val(); 1324 ClearedFPRegs.emplace_back(Reg, SaveReg, 0); 1325 1326 // Save the fp register to the normal registers 1327 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) 1328 .addReg(Reg) 1329 .add(predOps(ARMCC::AL)); 1330 } else { 1331 NonclearedFPRegs.push_back(Reg); 1332 } 1333 } 1334 } 1335 } 1336 1337 bool passesFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty()); 1338 1339 // Lazy store all fp registers to the stack 1340 MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) 1341 .addReg(ARM::SP) 1342 .add(predOps(ARMCC::AL)); 1343 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, 1344 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) 1345 VLSTM.addReg(R, RegState::Implicit | 1346 (LiveRegs.contains(R) ? 0 : RegState::Undef)); 1347 1348 // Restore all arguments 1349 for (const auto &Regs : ClearedFPRegs) { 1350 unsigned Reg, SaveReg1, SaveReg2; 1351 std::tie(Reg, SaveReg1, SaveReg2) = Regs; 1352 if (ARM::DPR_VFP2RegClass.contains(Reg)) 1353 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) 1354 .addReg(SaveReg1) 1355 .addReg(SaveReg2) 1356 .add(predOps(ARMCC::AL)); 1357 else if (ARM::SPRRegClass.contains(Reg)) 1358 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) 1359 .addReg(SaveReg1) 1360 .add(predOps(ARMCC::AL)); 1361 } 1362 1363 for (unsigned Reg : NonclearedFPRegs) { 1364 if (ARM::DPR_VFP2RegClass.contains(Reg)) { 1365 if (STI->isLittle()) { 1366 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRD), Reg) 1367 .addReg(ARM::SP) 1368 .addImm((Reg - ARM::D0) * 2) 1369 .add(predOps(ARMCC::AL)); 1370 } else { 1371 // For big-endian targets we need to load the two subregisters of Reg 1372 // manually because VLDRD would load them in wrong order 1373 unsigned SReg0 = TRI->getSubReg(Reg, ARM::ssub_0); 1374 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0) 1375 .addReg(ARM::SP) 1376 .addImm((Reg - ARM::D0) * 2) 1377 .add(predOps(ARMCC::AL)); 1378 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0 + 1) 1379 .addReg(ARM::SP) 1380 .addImm((Reg - ARM::D0) * 2 + 1) 1381 .add(predOps(ARMCC::AL)); 1382 } 1383 } else if (ARM::SPRRegClass.contains(Reg)) { 1384 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), Reg) 1385 .addReg(ARM::SP) 1386 .addImm(Reg - ARM::S0) 1387 .add(predOps(ARMCC::AL)); 1388 } 1389 } 1390 // restore FPSCR from stack and clear bits 0-4, 7, 28-31 1391 // The other bits are program global according to the AAPCS 1392 if (passesFPReg) { 1393 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2LDRi8), SpareReg) 1394 .addReg(ARM::SP) 1395 .addImm(0x40) 1396 .add(predOps(ARMCC::AL)); 1397 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) 1398 .addReg(SpareReg) 1399 .addImm(0x0000009F) 1400 .add(predOps(ARMCC::AL)) 1401 .add(condCodeOp()); 1402 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) 1403 .addReg(SpareReg) 1404 .addImm(0xF0000000) 1405 .add(predOps(ARMCC::AL)) 1406 .add(condCodeOp()); 1407 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMSR)) 1408 .addReg(SpareReg) 1409 .add(predOps(ARMCC::AL)); 1410 // The ldr must happen after a floating point instruction. To prevent the 1411 // post-ra scheduler to mess with the order, we create a bundle. 1412 finalizeBundle(MBB, VLSTM->getIterator(), MBBI->getIterator()); 1413 } 1414 } 1415 1416 void ARMExpandPseudo::CMSESaveClearFPRegsV81(MachineBasicBlock &MBB, 1417 MachineBasicBlock::iterator MBBI, 1418 DebugLoc &DL, 1419 const LivePhysRegs &LiveRegs) { 1420 BitVector ClearRegs(32, true); 1421 bool DefFP = determineFPRegsToClear(*MBBI, ClearRegs); 1422 1423 // If the instruction does not write to a FP register and no elements were 1424 // removed from the set, then no FP registers were used to pass 1425 // arguments/returns. 1426 if (!DefFP && ClearRegs.count() == ClearRegs.size()) { 1427 // save space on stack for VLSTM 1428 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) 1429 .addReg(ARM::SP) 1430 .addImm(CMSE_FP_SAVE_SIZE >> 2) 1431 .add(predOps(ARMCC::AL)); 1432 1433 // Lazy store all FP registers to the stack 1434 MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) 1435 .addReg(ARM::SP) 1436 .add(predOps(ARMCC::AL)); 1437 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, 1438 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) 1439 VLSTM.addReg(R, RegState::Implicit | 1440 (LiveRegs.contains(R) ? 0 : RegState::Undef)); 1441 } else { 1442 // Push all the callee-saved registers (s16-s31). 1443 MachineInstrBuilder VPUSH = 1444 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP) 1445 .addReg(ARM::SP) 1446 .add(predOps(ARMCC::AL)); 1447 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) 1448 VPUSH.addReg(Reg); 1449 1450 // Clear FP registers with a VSCCLRM. 1451 (void)CMSEClearFPRegsV81(MBB, MBBI, ClearRegs); 1452 1453 // Save floating-point context. 1454 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTR_FPCXTS_pre), ARM::SP) 1455 .addReg(ARM::SP) 1456 .addImm(-8) 1457 .add(predOps(ARMCC::AL)); 1458 } 1459 } 1460 1461 // Restore FP registers if present 1462 void ARMExpandPseudo::CMSERestoreFPRegs( 1463 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1464 SmallVectorImpl<unsigned> &AvailableRegs) { 1465 if (STI->hasV8_1MMainlineOps()) 1466 CMSERestoreFPRegsV81(MBB, MBBI, DL, AvailableRegs); 1467 else 1468 CMSERestoreFPRegsV8(MBB, MBBI, DL, AvailableRegs); 1469 } 1470 1471 void ARMExpandPseudo::CMSERestoreFPRegsV8( 1472 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1473 SmallVectorImpl<unsigned> &AvailableRegs) { 1474 if (!STI->hasFPRegs()) 1475 return; 1476 1477 // Use AvailableRegs to store the fp regs 1478 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs; 1479 std::vector<unsigned> NonclearedFPRegs; 1480 for (const MachineOperand &Op : MBBI->operands()) { 1481 if (Op.isReg() && Op.isDef()) { 1482 unsigned Reg = Op.getReg(); 1483 assert(!ARM::DPRRegClass.contains(Reg) || 1484 ARM::DPR_VFP2RegClass.contains(Reg)); 1485 assert(!ARM::QPRRegClass.contains(Reg)); 1486 if (ARM::DPR_VFP2RegClass.contains(Reg)) { 1487 if (AvailableRegs.size() >= 2) { 1488 unsigned SaveReg2 = AvailableRegs.pop_back_val(); 1489 unsigned SaveReg1 = AvailableRegs.pop_back_val(); 1490 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2); 1491 1492 // Save the fp register to the normal registers 1493 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) 1494 .addReg(SaveReg1, RegState::Define) 1495 .addReg(SaveReg2, RegState::Define) 1496 .addReg(Reg) 1497 .add(predOps(ARMCC::AL)); 1498 } else { 1499 NonclearedFPRegs.push_back(Reg); 1500 } 1501 } else if (ARM::SPRRegClass.contains(Reg)) { 1502 if (AvailableRegs.size() >= 1) { 1503 unsigned SaveReg = AvailableRegs.pop_back_val(); 1504 ClearedFPRegs.emplace_back(Reg, SaveReg, 0); 1505 1506 // Save the fp register to the normal registers 1507 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) 1508 .addReg(Reg) 1509 .add(predOps(ARMCC::AL)); 1510 } else { 1511 NonclearedFPRegs.push_back(Reg); 1512 } 1513 } 1514 } 1515 } 1516 1517 // Push FP regs that cannot be restored via normal registers on the stack 1518 for (unsigned Reg : NonclearedFPRegs) { 1519 if (ARM::DPR_VFP2RegClass.contains(Reg)) 1520 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRD), Reg) 1521 .addReg(ARM::SP) 1522 .addImm((Reg - ARM::D0) * 2) 1523 .add(predOps(ARMCC::AL)); 1524 else if (ARM::SPRRegClass.contains(Reg)) 1525 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRS), Reg) 1526 .addReg(ARM::SP) 1527 .addImm(Reg - ARM::S0) 1528 .add(predOps(ARMCC::AL)); 1529 } 1530 1531 // Lazy load fp regs from stack 1532 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) 1533 .addReg(ARM::SP) 1534 .add(predOps(ARMCC::AL)); 1535 1536 // Restore all FP registers via normal registers 1537 for (const auto &Regs : ClearedFPRegs) { 1538 unsigned Reg, SaveReg1, SaveReg2; 1539 std::tie(Reg, SaveReg1, SaveReg2) = Regs; 1540 if (ARM::DPR_VFP2RegClass.contains(Reg)) 1541 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) 1542 .addReg(SaveReg1) 1543 .addReg(SaveReg2) 1544 .add(predOps(ARMCC::AL)); 1545 else if (ARM::SPRRegClass.contains(Reg)) 1546 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) 1547 .addReg(SaveReg1) 1548 .add(predOps(ARMCC::AL)); 1549 } 1550 1551 // Pop the stack space 1552 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) 1553 .addReg(ARM::SP) 1554 .addImm(CMSE_FP_SAVE_SIZE >> 2) 1555 .add(predOps(ARMCC::AL)); 1556 } 1557 1558 static bool definesOrUsesFPReg(const MachineInstr &MI) { 1559 for (const MachineOperand &Op : MI.operands()) { 1560 if (!Op.isReg()) 1561 continue; 1562 unsigned Reg = Op.getReg(); 1563 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || 1564 (Reg >= ARM::D0 && Reg <= ARM::D15) || 1565 (Reg >= ARM::S0 && Reg <= ARM::S31)) 1566 return true; 1567 } 1568 return false; 1569 } 1570 1571 void ARMExpandPseudo::CMSERestoreFPRegsV81( 1572 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL, 1573 SmallVectorImpl<unsigned> &AvailableRegs) { 1574 if (!definesOrUsesFPReg(*MBBI)) { 1575 // Load FP registers from stack. 1576 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) 1577 .addReg(ARM::SP) 1578 .add(predOps(ARMCC::AL)); 1579 1580 // Pop the stack space 1581 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) 1582 .addReg(ARM::SP) 1583 .addImm(CMSE_FP_SAVE_SIZE >> 2) 1584 .add(predOps(ARMCC::AL)); 1585 } else { 1586 // Restore the floating point context. 1587 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::VLDR_FPCXTS_post), 1588 ARM::SP) 1589 .addReg(ARM::SP) 1590 .addImm(8) 1591 .add(predOps(ARMCC::AL)); 1592 1593 // Pop all the callee-saved registers (s16-s31). 1594 MachineInstrBuilder VPOP = 1595 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDMSIA_UPD), ARM::SP) 1596 .addReg(ARM::SP) 1597 .add(predOps(ARMCC::AL)); 1598 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) 1599 VPOP.addReg(Reg, RegState::Define); 1600 } 1601 } 1602 1603 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as 1604 /// possible. This only gets used at -O0 so we don't care about efficiency of 1605 /// the generated code. 1606 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB, 1607 MachineBasicBlock::iterator MBBI, 1608 unsigned LdrexOp, unsigned StrexOp, 1609 unsigned UxtOp, 1610 MachineBasicBlock::iterator &NextMBBI) { 1611 bool IsThumb = STI->isThumb(); 1612 MachineInstr &MI = *MBBI; 1613 DebugLoc DL = MI.getDebugLoc(); 1614 const MachineOperand &Dest = MI.getOperand(0); 1615 Register TempReg = MI.getOperand(1).getReg(); 1616 // Duplicating undef operands into 2 instructions does not guarantee the same 1617 // value on both; However undef should be replaced by xzr anyway. 1618 assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); 1619 Register AddrReg = MI.getOperand(2).getReg(); 1620 Register DesiredReg = MI.getOperand(3).getReg(); 1621 Register NewReg = MI.getOperand(4).getReg(); 1622 1623 if (IsThumb) { 1624 assert(STI->hasV8MBaselineOps() && 1625 "CMP_SWAP not expected to be custom expanded for Thumb1"); 1626 assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) && 1627 "ARMv8-M.baseline does not have t2UXTB/t2UXTH"); 1628 assert(ARM::tGPRRegClass.contains(DesiredReg) && 1629 "DesiredReg used for UXT op must be tGPR"); 1630 } 1631 1632 MachineFunction *MF = MBB.getParent(); 1633 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1634 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1635 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1636 1637 MF->insert(++MBB.getIterator(), LoadCmpBB); 1638 MF->insert(++LoadCmpBB->getIterator(), StoreBB); 1639 MF->insert(++StoreBB->getIterator(), DoneBB); 1640 1641 if (UxtOp) { 1642 MachineInstrBuilder MIB = 1643 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg) 1644 .addReg(DesiredReg, RegState::Kill); 1645 if (!IsThumb) 1646 MIB.addImm(0); 1647 MIB.add(predOps(ARMCC::AL)); 1648 } 1649 1650 // .Lloadcmp: 1651 // ldrex rDest, [rAddr] 1652 // cmp rDest, rDesired 1653 // bne .Ldone 1654 1655 MachineInstrBuilder MIB; 1656 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg()); 1657 MIB.addReg(AddrReg); 1658 if (LdrexOp == ARM::t2LDREX) 1659 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset. 1660 MIB.add(predOps(ARMCC::AL)); 1661 1662 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; 1663 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 1664 .addReg(Dest.getReg(), getKillRegState(Dest.isDead())) 1665 .addReg(DesiredReg) 1666 .add(predOps(ARMCC::AL)); 1667 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; 1668 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) 1669 .addMBB(DoneBB) 1670 .addImm(ARMCC::NE) 1671 .addReg(ARM::CPSR, RegState::Kill); 1672 LoadCmpBB->addSuccessor(DoneBB); 1673 LoadCmpBB->addSuccessor(StoreBB); 1674 1675 // .Lstore: 1676 // strex rTempReg, rNew, [rAddr] 1677 // cmp rTempReg, #0 1678 // bne .Lloadcmp 1679 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg) 1680 .addReg(NewReg) 1681 .addReg(AddrReg); 1682 if (StrexOp == ARM::t2STREX) 1683 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset. 1684 MIB.add(predOps(ARMCC::AL)); 1685 1686 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; 1687 BuildMI(StoreBB, DL, TII->get(CMPri)) 1688 .addReg(TempReg, RegState::Kill) 1689 .addImm(0) 1690 .add(predOps(ARMCC::AL)); 1691 BuildMI(StoreBB, DL, TII->get(Bcc)) 1692 .addMBB(LoadCmpBB) 1693 .addImm(ARMCC::NE) 1694 .addReg(ARM::CPSR, RegState::Kill); 1695 StoreBB->addSuccessor(LoadCmpBB); 1696 StoreBB->addSuccessor(DoneBB); 1697 1698 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); 1699 DoneBB->transferSuccessors(&MBB); 1700 1701 MBB.addSuccessor(LoadCmpBB); 1702 1703 NextMBBI = MBB.end(); 1704 MI.eraseFromParent(); 1705 1706 // Recompute livein lists. 1707 LivePhysRegs LiveRegs; 1708 computeAndAddLiveIns(LiveRegs, *DoneBB); 1709 computeAndAddLiveIns(LiveRegs, *StoreBB); 1710 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1711 // Do an extra pass around the loop to get loop carried registers right. 1712 StoreBB->clearLiveIns(); 1713 computeAndAddLiveIns(LiveRegs, *StoreBB); 1714 LoadCmpBB->clearLiveIns(); 1715 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1716 1717 return true; 1718 } 1719 1720 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a 1721 /// single GPRPair register), Thumb's take two separate registers so we need to 1722 /// extract the subregs from the pair. 1723 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, 1724 unsigned Flags, bool IsThumb, 1725 const TargetRegisterInfo *TRI) { 1726 if (IsThumb) { 1727 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); 1728 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); 1729 MIB.addReg(RegLo, Flags); 1730 MIB.addReg(RegHi, Flags); 1731 } else 1732 MIB.addReg(Reg.getReg(), Flags); 1733 } 1734 1735 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop. 1736 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB, 1737 MachineBasicBlock::iterator MBBI, 1738 MachineBasicBlock::iterator &NextMBBI) { 1739 bool IsThumb = STI->isThumb(); 1740 MachineInstr &MI = *MBBI; 1741 DebugLoc DL = MI.getDebugLoc(); 1742 MachineOperand &Dest = MI.getOperand(0); 1743 Register TempReg = MI.getOperand(1).getReg(); 1744 // Duplicating undef operands into 2 instructions does not guarantee the same 1745 // value on both; However undef should be replaced by xzr anyway. 1746 assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); 1747 Register AddrReg = MI.getOperand(2).getReg(); 1748 Register DesiredReg = MI.getOperand(3).getReg(); 1749 MachineOperand New = MI.getOperand(4); 1750 New.setIsKill(false); 1751 1752 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); 1753 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); 1754 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); 1755 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); 1756 1757 MachineFunction *MF = MBB.getParent(); 1758 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1759 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1760 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); 1761 1762 MF->insert(++MBB.getIterator(), LoadCmpBB); 1763 MF->insert(++LoadCmpBB->getIterator(), StoreBB); 1764 MF->insert(++StoreBB->getIterator(), DoneBB); 1765 1766 // .Lloadcmp: 1767 // ldrexd rDestLo, rDestHi, [rAddr] 1768 // cmp rDestLo, rDesiredLo 1769 // sbcs dead rTempReg, rDestHi, rDesiredHi 1770 // bne .Ldone 1771 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD; 1772 MachineInstrBuilder MIB; 1773 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD)); 1774 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI); 1775 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); 1776 1777 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; 1778 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 1779 .addReg(DestLo, getKillRegState(Dest.isDead())) 1780 .addReg(DesiredLo) 1781 .add(predOps(ARMCC::AL)); 1782 1783 BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) 1784 .addReg(DestHi, getKillRegState(Dest.isDead())) 1785 .addReg(DesiredHi) 1786 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); 1787 1788 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; 1789 BuildMI(LoadCmpBB, DL, TII->get(Bcc)) 1790 .addMBB(DoneBB) 1791 .addImm(ARMCC::NE) 1792 .addReg(ARM::CPSR, RegState::Kill); 1793 LoadCmpBB->addSuccessor(DoneBB); 1794 LoadCmpBB->addSuccessor(StoreBB); 1795 1796 // .Lstore: 1797 // strexd rTempReg, rNewLo, rNewHi, [rAddr] 1798 // cmp rTempReg, #0 1799 // bne .Lloadcmp 1800 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; 1801 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); 1802 unsigned Flags = getKillRegState(New.isDead()); 1803 addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI); 1804 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); 1805 1806 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; 1807 BuildMI(StoreBB, DL, TII->get(CMPri)) 1808 .addReg(TempReg, RegState::Kill) 1809 .addImm(0) 1810 .add(predOps(ARMCC::AL)); 1811 BuildMI(StoreBB, DL, TII->get(Bcc)) 1812 .addMBB(LoadCmpBB) 1813 .addImm(ARMCC::NE) 1814 .addReg(ARM::CPSR, RegState::Kill); 1815 StoreBB->addSuccessor(LoadCmpBB); 1816 StoreBB->addSuccessor(DoneBB); 1817 1818 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end()); 1819 DoneBB->transferSuccessors(&MBB); 1820 1821 MBB.addSuccessor(LoadCmpBB); 1822 1823 NextMBBI = MBB.end(); 1824 MI.eraseFromParent(); 1825 1826 // Recompute livein lists. 1827 LivePhysRegs LiveRegs; 1828 computeAndAddLiveIns(LiveRegs, *DoneBB); 1829 computeAndAddLiveIns(LiveRegs, *StoreBB); 1830 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1831 // Do an extra pass around the loop to get loop carried registers right. 1832 StoreBB->clearLiveIns(); 1833 computeAndAddLiveIns(LiveRegs, *StoreBB); 1834 LoadCmpBB->clearLiveIns(); 1835 computeAndAddLiveIns(LiveRegs, *LoadCmpBB); 1836 1837 return true; 1838 } 1839 1840 static void CMSEPushCalleeSaves(const TargetInstrInfo &TII, 1841 MachineBasicBlock &MBB, 1842 MachineBasicBlock::iterator MBBI, int JumpReg, 1843 const LivePhysRegs &LiveRegs, bool Thumb1Only) { 1844 const DebugLoc &DL = MBBI->getDebugLoc(); 1845 if (Thumb1Only) { // push Lo and Hi regs separately 1846 MachineInstrBuilder PushMIB = 1847 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); 1848 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) { 1849 PushMIB.addReg( 1850 Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef); 1851 } 1852 1853 // Thumb1 can only tPUSH low regs, so we copy the high regs to the low 1854 // regs that we just saved and push the low regs again, taking care to 1855 // not clobber JumpReg. If JumpReg is one of the low registers, push first 1856 // the values of r9-r11, and then r8. That would leave them ordered in 1857 // memory, and allow us to later pop them with a single instructions. 1858 // FIXME: Could also use any of r0-r3 that are free (including in the 1859 // first PUSH above). 1860 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { 1861 if (JumpReg == LoReg) 1862 continue; 1863 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) 1864 .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef) 1865 .add(predOps(ARMCC::AL)); 1866 --HiReg; 1867 } 1868 MachineInstrBuilder PushMIB2 = 1869 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); 1870 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) { 1871 if (Reg == JumpReg) 1872 continue; 1873 PushMIB2.addReg(Reg, RegState::Kill); 1874 } 1875 1876 // If we couldn't use a low register for temporary storage (because it was 1877 // the JumpReg), use r4 or r5, whichever is not JumpReg. It has already been 1878 // saved. 1879 if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) { 1880 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; 1881 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) 1882 .addReg(ARM::R8, LiveRegs.contains(ARM::R8) ? 0 : RegState::Undef) 1883 .add(predOps(ARMCC::AL)); 1884 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)) 1885 .add(predOps(ARMCC::AL)) 1886 .addReg(LoReg, RegState::Kill); 1887 } 1888 } else { // push Lo and Hi registers with a single instruction 1889 MachineInstrBuilder PushMIB = 1890 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP) 1891 .addReg(ARM::SP) 1892 .add(predOps(ARMCC::AL)); 1893 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) { 1894 PushMIB.addReg( 1895 Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef); 1896 } 1897 } 1898 } 1899 1900 static void CMSEPopCalleeSaves(const TargetInstrInfo &TII, 1901 MachineBasicBlock &MBB, 1902 MachineBasicBlock::iterator MBBI, int JumpReg, 1903 bool Thumb1Only) { 1904 const DebugLoc &DL = MBBI->getDebugLoc(); 1905 if (Thumb1Only) { 1906 MachineInstrBuilder PopMIB = 1907 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); 1908 for (int R = 0; R < 4; ++R) { 1909 PopMIB.addReg(ARM::R4 + R, RegState::Define); 1910 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), ARM::R8 + R) 1911 .addReg(ARM::R4 + R, RegState::Kill) 1912 .add(predOps(ARMCC::AL)); 1913 } 1914 MachineInstrBuilder PopMIB2 = 1915 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); 1916 for (int R = 0; R < 4; ++R) 1917 PopMIB2.addReg(ARM::R4 + R, RegState::Define); 1918 } else { // pop Lo and Hi registers with a single instruction 1919 MachineInstrBuilder PopMIB = 1920 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2LDMIA_UPD), ARM::SP) 1921 .addReg(ARM::SP) 1922 .add(predOps(ARMCC::AL)); 1923 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) 1924 PopMIB.addReg(Reg, RegState::Define); 1925 } 1926 } 1927 1928 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, 1929 MachineBasicBlock::iterator MBBI, 1930 MachineBasicBlock::iterator &NextMBBI) { 1931 MachineInstr &MI = *MBBI; 1932 unsigned Opcode = MI.getOpcode(); 1933 switch (Opcode) { 1934 default: 1935 return false; 1936 1937 case ARM::VBSPd: 1938 case ARM::VBSPq: { 1939 Register DstReg = MI.getOperand(0).getReg(); 1940 if (DstReg == MI.getOperand(3).getReg()) { 1941 // Expand to VBIT 1942 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq; 1943 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) 1944 .add(MI.getOperand(0)) 1945 .add(MI.getOperand(3)) 1946 .add(MI.getOperand(2)) 1947 .add(MI.getOperand(1)) 1948 .addImm(MI.getOperand(4).getImm()) 1949 .add(MI.getOperand(5)); 1950 } else if (DstReg == MI.getOperand(2).getReg()) { 1951 // Expand to VBIF 1952 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq; 1953 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) 1954 .add(MI.getOperand(0)) 1955 .add(MI.getOperand(2)) 1956 .add(MI.getOperand(3)) 1957 .add(MI.getOperand(1)) 1958 .addImm(MI.getOperand(4).getImm()) 1959 .add(MI.getOperand(5)); 1960 } else { 1961 // Expand to VBSL 1962 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq; 1963 if (DstReg == MI.getOperand(1).getReg()) { 1964 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) 1965 .add(MI.getOperand(0)) 1966 .add(MI.getOperand(1)) 1967 .add(MI.getOperand(2)) 1968 .add(MI.getOperand(3)) 1969 .addImm(MI.getOperand(4).getImm()) 1970 .add(MI.getOperand(5)); 1971 } else { 1972 // Use move to satisfy constraints 1973 unsigned MoveOpc = Opcode == ARM::VBSPd ? ARM::VORRd : ARM::VORRq; 1974 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MoveOpc)) 1975 .addReg(DstReg, 1976 RegState::Define | 1977 getRenamableRegState(MI.getOperand(0).isRenamable())) 1978 .add(MI.getOperand(1)) 1979 .add(MI.getOperand(1)) 1980 .addImm(MI.getOperand(4).getImm()) 1981 .add(MI.getOperand(5)); 1982 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) 1983 .add(MI.getOperand(0)) 1984 .addReg(DstReg, 1985 RegState::Kill | 1986 getRenamableRegState(MI.getOperand(0).isRenamable())) 1987 .add(MI.getOperand(2)) 1988 .add(MI.getOperand(3)) 1989 .addImm(MI.getOperand(4).getImm()) 1990 .add(MI.getOperand(5)); 1991 } 1992 } 1993 MI.eraseFromParent(); 1994 return true; 1995 } 1996 1997 case ARM::TCRETURNdi: 1998 case ARM::TCRETURNri: { 1999 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 2000 assert(MBBI->isReturn() && 2001 "Can only insert epilog into returning blocks"); 2002 unsigned RetOpcode = MBBI->getOpcode(); 2003 DebugLoc dl = MBBI->getDebugLoc(); 2004 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>( 2005 MBB.getParent()->getSubtarget().getInstrInfo()); 2006 2007 // Tail call return: adjust the stack pointer and jump to callee. 2008 MBBI = MBB.getLastNonDebugInstr(); 2009 MachineOperand &JumpTarget = MBBI->getOperand(0); 2010 2011 // Jump to label or value in register. 2012 if (RetOpcode == ARM::TCRETURNdi) { 2013 unsigned TCOpcode = 2014 STI->isThumb() 2015 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) 2016 : ARM::TAILJMPd; 2017 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); 2018 if (JumpTarget.isGlobal()) 2019 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 2020 JumpTarget.getTargetFlags()); 2021 else { 2022 assert(JumpTarget.isSymbol()); 2023 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 2024 JumpTarget.getTargetFlags()); 2025 } 2026 2027 // Add the default predicate in Thumb mode. 2028 if (STI->isThumb()) 2029 MIB.add(predOps(ARMCC::AL)); 2030 } else if (RetOpcode == ARM::TCRETURNri) { 2031 unsigned Opcode = 2032 STI->isThumb() ? ARM::tTAILJMPr 2033 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4); 2034 BuildMI(MBB, MBBI, dl, 2035 TII.get(Opcode)) 2036 .addReg(JumpTarget.getReg(), RegState::Kill); 2037 } 2038 2039 auto NewMI = std::prev(MBBI); 2040 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i) 2041 NewMI->addOperand(MBBI->getOperand(i)); 2042 2043 2044 // Update call site info and delete the pseudo instruction TCRETURN. 2045 if (MI.isCandidateForCallSiteEntry()) 2046 MI.getMF()->moveCallSiteInfo(&MI, &*NewMI); 2047 MBB.erase(MBBI); 2048 2049 MBBI = NewMI; 2050 return true; 2051 } 2052 case ARM::tBXNS_RET: { 2053 MachineBasicBlock &AfterBB = CMSEClearFPRegs(MBB, MBBI); 2054 2055 if (STI->hasV8_1MMainlineOps()) { 2056 // Restore the non-secure floating point context. 2057 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), 2058 TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP) 2059 .addReg(ARM::SP) 2060 .addImm(4) 2061 .add(predOps(ARMCC::AL)); 2062 } 2063 2064 // Clear all GPR that are not a use of the return instruction. 2065 assert(llvm::all_of(MBBI->operands(), [](const MachineOperand &Op) { 2066 return !Op.isReg() || Op.getReg() != ARM::R12; 2067 })); 2068 SmallVector<unsigned, 5> ClearRegs; 2069 determineGPRegsToClear( 2070 *MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs); 2071 CMSEClearGPRegs(AfterBB, AfterBB.end(), MBBI->getDebugLoc(), ClearRegs, 2072 ARM::LR); 2073 2074 MachineInstrBuilder NewMI = 2075 BuildMI(AfterBB, AfterBB.end(), MBBI->getDebugLoc(), 2076 TII->get(ARM::tBXNS)) 2077 .addReg(ARM::LR) 2078 .add(predOps(ARMCC::AL)); 2079 for (const MachineOperand &Op : MI.operands()) 2080 NewMI->addOperand(Op); 2081 MI.eraseFromParent(); 2082 return true; 2083 } 2084 case ARM::tBLXNS_CALL: { 2085 DebugLoc DL = MBBI->getDebugLoc(); 2086 unsigned JumpReg = MBBI->getOperand(0).getReg(); 2087 2088 // Figure out which registers are live at the point immediately before the 2089 // call. When we indiscriminately push a set of registers, the live 2090 // registers are added as ordinary use operands, whereas dead registers 2091 // are "undef". 2092 LivePhysRegs LiveRegs(*TRI); 2093 LiveRegs.addLiveOuts(MBB); 2094 for (const MachineInstr &MI : make_range(MBB.rbegin(), MBBI.getReverse())) 2095 LiveRegs.stepBackward(MI); 2096 LiveRegs.stepBackward(*MBBI); 2097 2098 CMSEPushCalleeSaves(*TII, MBB, MBBI, JumpReg, LiveRegs, 2099 AFI->isThumb1OnlyFunction()); 2100 2101 SmallVector<unsigned, 16> ClearRegs; 2102 determineGPRegsToClear(*MBBI, 2103 {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, 2104 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, 2105 ARM::R10, ARM::R11, ARM::R12}, 2106 ClearRegs); 2107 auto OriginalClearRegs = ClearRegs; 2108 2109 // Get the first cleared register as a scratch (to use later with tBIC). 2110 // We need to use the first so we can ensure it is a low register. 2111 unsigned ScratchReg = ClearRegs.front(); 2112 2113 // Clear LSB of JumpReg 2114 if (AFI->isThumb2Function()) { 2115 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), JumpReg) 2116 .addReg(JumpReg) 2117 .addImm(1) 2118 .add(predOps(ARMCC::AL)) 2119 .add(condCodeOp()); 2120 } else { 2121 // We need to use an extra register to cope with 8M Baseline, 2122 // since we have saved all of the registers we are ok to trash a non 2123 // argument register here. 2124 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVi8), ScratchReg) 2125 .add(condCodeOp()) 2126 .addImm(1) 2127 .add(predOps(ARMCC::AL)); 2128 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBIC), JumpReg) 2129 .addReg(ARM::CPSR, RegState::Define) 2130 .addReg(JumpReg) 2131 .addReg(ScratchReg) 2132 .add(predOps(ARMCC::AL)); 2133 } 2134 2135 CMSESaveClearFPRegs(MBB, MBBI, DL, LiveRegs, 2136 ClearRegs); // save+clear FP regs with ClearRegs 2137 CMSEClearGPRegs(MBB, MBBI, DL, ClearRegs, JumpReg); 2138 2139 const MachineInstrBuilder NewCall = 2140 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBLXNSr)) 2141 .add(predOps(ARMCC::AL)) 2142 .addReg(JumpReg, RegState::Kill); 2143 2144 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) 2145 NewCall->addOperand(MI.getOperand(I)); 2146 if (MI.isCandidateForCallSiteEntry()) 2147 MI.getMF()->moveCallSiteInfo(&MI, NewCall.getInstr()); 2148 2149 CMSERestoreFPRegs(MBB, MBBI, DL, OriginalClearRegs); // restore FP registers 2150 2151 CMSEPopCalleeSaves(*TII, MBB, MBBI, JumpReg, AFI->isThumb1OnlyFunction()); 2152 2153 MI.eraseFromParent(); 2154 return true; 2155 } 2156 case ARM::VMOVHcc: 2157 case ARM::VMOVScc: 2158 case ARM::VMOVDcc: { 2159 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD; 2160 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), 2161 MI.getOperand(1).getReg()) 2162 .add(MI.getOperand(2)) 2163 .addImm(MI.getOperand(3).getImm()) // 'pred' 2164 .add(MI.getOperand(4)) 2165 .add(makeImplicit(MI.getOperand(1))); 2166 2167 MI.eraseFromParent(); 2168 return true; 2169 } 2170 case ARM::t2MOVCCr: 2171 case ARM::MOVCCr: { 2172 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; 2173 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 2174 MI.getOperand(1).getReg()) 2175 .add(MI.getOperand(2)) 2176 .addImm(MI.getOperand(3).getImm()) // 'pred' 2177 .add(MI.getOperand(4)) 2178 .add(condCodeOp()) // 's' bit 2179 .add(makeImplicit(MI.getOperand(1))); 2180 2181 MI.eraseFromParent(); 2182 return true; 2183 } 2184 case ARM::MOVCCsi: { 2185 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 2186 (MI.getOperand(1).getReg())) 2187 .add(MI.getOperand(2)) 2188 .addImm(MI.getOperand(3).getImm()) 2189 .addImm(MI.getOperand(4).getImm()) // 'pred' 2190 .add(MI.getOperand(5)) 2191 .add(condCodeOp()) // 's' bit 2192 .add(makeImplicit(MI.getOperand(1))); 2193 2194 MI.eraseFromParent(); 2195 return true; 2196 } 2197 case ARM::MOVCCsr: { 2198 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), 2199 (MI.getOperand(1).getReg())) 2200 .add(MI.getOperand(2)) 2201 .add(MI.getOperand(3)) 2202 .addImm(MI.getOperand(4).getImm()) 2203 .addImm(MI.getOperand(5).getImm()) // 'pred' 2204 .add(MI.getOperand(6)) 2205 .add(condCodeOp()) // 's' bit 2206 .add(makeImplicit(MI.getOperand(1))); 2207 2208 MI.eraseFromParent(); 2209 return true; 2210 } 2211 case ARM::t2MOVCCi16: 2212 case ARM::MOVCCi16: { 2213 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; 2214 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 2215 MI.getOperand(1).getReg()) 2216 .addImm(MI.getOperand(2).getImm()) 2217 .addImm(MI.getOperand(3).getImm()) // 'pred' 2218 .add(MI.getOperand(4)) 2219 .add(makeImplicit(MI.getOperand(1))); 2220 MI.eraseFromParent(); 2221 return true; 2222 } 2223 case ARM::t2MOVCCi: 2224 case ARM::MOVCCi: { 2225 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; 2226 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 2227 MI.getOperand(1).getReg()) 2228 .addImm(MI.getOperand(2).getImm()) 2229 .addImm(MI.getOperand(3).getImm()) // 'pred' 2230 .add(MI.getOperand(4)) 2231 .add(condCodeOp()) // 's' bit 2232 .add(makeImplicit(MI.getOperand(1))); 2233 2234 MI.eraseFromParent(); 2235 return true; 2236 } 2237 case ARM::t2MVNCCi: 2238 case ARM::MVNCCi: { 2239 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; 2240 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 2241 MI.getOperand(1).getReg()) 2242 .addImm(MI.getOperand(2).getImm()) 2243 .addImm(MI.getOperand(3).getImm()) // 'pred' 2244 .add(MI.getOperand(4)) 2245 .add(condCodeOp()) // 's' bit 2246 .add(makeImplicit(MI.getOperand(1))); 2247 2248 MI.eraseFromParent(); 2249 return true; 2250 } 2251 case ARM::t2MOVCClsl: 2252 case ARM::t2MOVCClsr: 2253 case ARM::t2MOVCCasr: 2254 case ARM::t2MOVCCror: { 2255 unsigned NewOpc; 2256 switch (Opcode) { 2257 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; 2258 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; 2259 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; 2260 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; 2261 default: llvm_unreachable("unexpeced conditional move"); 2262 } 2263 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 2264 MI.getOperand(1).getReg()) 2265 .add(MI.getOperand(2)) 2266 .addImm(MI.getOperand(3).getImm()) 2267 .addImm(MI.getOperand(4).getImm()) // 'pred' 2268 .add(MI.getOperand(5)) 2269 .add(condCodeOp()) // 's' bit 2270 .add(makeImplicit(MI.getOperand(1))); 2271 MI.eraseFromParent(); 2272 return true; 2273 } 2274 case ARM::Int_eh_sjlj_dispatchsetup: { 2275 MachineFunction &MF = *MI.getParent()->getParent(); 2276 const ARMBaseInstrInfo *AII = 2277 static_cast<const ARMBaseInstrInfo*>(TII); 2278 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 2279 // For functions using a base pointer, we rematerialize it (via the frame 2280 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it 2281 // for us. Otherwise, expand to nothing. 2282 if (RI.hasBasePointer(MF)) { 2283 int32_t NumBytes = AFI->getFramePtrSpillOffset(); 2284 Register FramePtr = RI.getFrameRegister(MF); 2285 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) && 2286 "base pointer without frame pointer?"); 2287 2288 if (AFI->isThumb2Function()) { 2289 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 2290 FramePtr, -NumBytes, ARMCC::AL, 0, *TII); 2291 } else if (AFI->isThumbFunction()) { 2292 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 2293 FramePtr, -NumBytes, *TII, RI); 2294 } else { 2295 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 2296 FramePtr, -NumBytes, ARMCC::AL, 0, 2297 *TII); 2298 } 2299 // If there's dynamic realignment, adjust for it. 2300 if (RI.hasStackRealignment(MF)) { 2301 MachineFrameInfo &MFI = MF.getFrameInfo(); 2302 Align MaxAlign = MFI.getMaxAlign(); 2303 assert (!AFI->isThumb1OnlyFunction()); 2304 // Emit bic r6, r6, MaxAlign 2305 assert(MaxAlign <= Align(256) && 2306 "The BIC instruction cannot encode " 2307 "immediates larger than 256 with all lower " 2308 "bits set."); 2309 unsigned bicOpc = AFI->isThumbFunction() ? 2310 ARM::t2BICri : ARM::BICri; 2311 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6) 2312 .addReg(ARM::R6, RegState::Kill) 2313 .addImm(MaxAlign.value() - 1) 2314 .add(predOps(ARMCC::AL)) 2315 .add(condCodeOp()); 2316 } 2317 } 2318 MI.eraseFromParent(); 2319 return true; 2320 } 2321 2322 case ARM::MOVsrl_flag: 2323 case ARM::MOVsra_flag: { 2324 // These are just fancy MOVs instructions. 2325 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 2326 MI.getOperand(0).getReg()) 2327 .add(MI.getOperand(1)) 2328 .addImm(ARM_AM::getSORegOpc( 2329 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1)) 2330 .add(predOps(ARMCC::AL)) 2331 .addReg(ARM::CPSR, RegState::Define); 2332 MI.eraseFromParent(); 2333 return true; 2334 } 2335 case ARM::RRX: { 2336 // This encodes as "MOVs Rd, Rm, rrx 2337 MachineInstrBuilder MIB = 2338 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 2339 MI.getOperand(0).getReg()) 2340 .add(MI.getOperand(1)) 2341 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)) 2342 .add(predOps(ARMCC::AL)) 2343 .add(condCodeOp()); 2344 TransferImpOps(MI, MIB, MIB); 2345 MI.eraseFromParent(); 2346 return true; 2347 } 2348 case ARM::tTPsoft: 2349 case ARM::TPsoft: { 2350 const bool Thumb = Opcode == ARM::tTPsoft; 2351 2352 MachineInstrBuilder MIB; 2353 MachineFunction *MF = MBB.getParent(); 2354 if (STI->genLongCalls()) { 2355 MachineConstantPool *MCP = MF->getConstantPool(); 2356 unsigned PCLabelID = AFI->createPICLabelUId(); 2357 MachineConstantPoolValue *CPV = 2358 ARMConstantPoolSymbol::Create(MF->getFunction().getContext(), 2359 "__aeabi_read_tp", PCLabelID, 0); 2360 Register Reg = MI.getOperand(0).getReg(); 2361 MIB = 2362 BuildMI(MBB, MBBI, MI.getDebugLoc(), 2363 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg) 2364 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, Align(4))); 2365 if (!Thumb) 2366 MIB.addImm(0); 2367 MIB.add(predOps(ARMCC::AL)); 2368 2369 MIB = 2370 BuildMI(MBB, MBBI, MI.getDebugLoc(), 2371 TII->get(Thumb ? gettBLXrOpcode(*MF) : getBLXOpcode(*MF))); 2372 if (Thumb) 2373 MIB.add(predOps(ARMCC::AL)); 2374 MIB.addReg(Reg, RegState::Kill); 2375 } else { 2376 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 2377 TII->get(Thumb ? ARM::tBL : ARM::BL)); 2378 if (Thumb) 2379 MIB.add(predOps(ARMCC::AL)); 2380 MIB.addExternalSymbol("__aeabi_read_tp", 0); 2381 } 2382 2383 MIB.cloneMemRefs(MI); 2384 TransferImpOps(MI, MIB, MIB); 2385 // Update the call site info. 2386 if (MI.isCandidateForCallSiteEntry()) 2387 MF->moveCallSiteInfo(&MI, &*MIB); 2388 MI.eraseFromParent(); 2389 return true; 2390 } 2391 case ARM::tLDRpci_pic: 2392 case ARM::t2LDRpci_pic: { 2393 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 2394 ? ARM::tLDRpci : ARM::t2LDRpci; 2395 Register DstReg = MI.getOperand(0).getReg(); 2396 bool DstIsDead = MI.getOperand(0).isDead(); 2397 MachineInstrBuilder MIB1 = 2398 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg) 2399 .add(MI.getOperand(1)) 2400 .add(predOps(ARMCC::AL)); 2401 MIB1.cloneMemRefs(MI); 2402 MachineInstrBuilder MIB2 = 2403 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) 2404 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 2405 .addReg(DstReg) 2406 .add(MI.getOperand(2)); 2407 TransferImpOps(MI, MIB1, MIB2); 2408 MI.eraseFromParent(); 2409 return true; 2410 } 2411 2412 case ARM::LDRLIT_ga_abs: 2413 case ARM::LDRLIT_ga_pcrel: 2414 case ARM::LDRLIT_ga_pcrel_ldr: 2415 case ARM::tLDRLIT_ga_abs: 2416 case ARM::tLDRLIT_ga_pcrel: { 2417 Register DstReg = MI.getOperand(0).getReg(); 2418 bool DstIsDead = MI.getOperand(0).isDead(); 2419 const MachineOperand &MO1 = MI.getOperand(1); 2420 auto Flags = MO1.getTargetFlags(); 2421 const GlobalValue *GV = MO1.getGlobal(); 2422 bool IsARM = 2423 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs; 2424 bool IsPIC = 2425 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; 2426 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; 2427 unsigned PICAddOpc = 2428 IsARM 2429 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 2430 : ARM::tPICADD; 2431 2432 // We need a new const-pool entry to load from. 2433 MachineConstantPool *MCP = MBB.getParent()->getConstantPool(); 2434 unsigned ARMPCLabelIndex = 0; 2435 MachineConstantPoolValue *CPV; 2436 2437 if (IsPIC) { 2438 unsigned PCAdj = IsARM ? 8 : 4; 2439 auto Modifier = (Flags & ARMII::MO_GOT) 2440 ? ARMCP::GOT_PREL 2441 : ARMCP::no_modifier; 2442 ARMPCLabelIndex = AFI->createPICLabelUId(); 2443 CPV = ARMConstantPoolConstant::Create( 2444 GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj, Modifier, 2445 /*AddCurrentAddr*/ Modifier == ARMCP::GOT_PREL); 2446 } else 2447 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier); 2448 2449 MachineInstrBuilder MIB = 2450 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg) 2451 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, Align(4))); 2452 if (IsARM) 2453 MIB.addImm(0); 2454 MIB.add(predOps(ARMCC::AL)); 2455 2456 if (IsPIC) { 2457 MachineInstrBuilder MIB = 2458 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc)) 2459 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 2460 .addReg(DstReg) 2461 .addImm(ARMPCLabelIndex); 2462 2463 if (IsARM) 2464 MIB.add(predOps(ARMCC::AL)); 2465 } 2466 2467 MI.eraseFromParent(); 2468 return true; 2469 } 2470 case ARM::MOV_ga_pcrel: 2471 case ARM::MOV_ga_pcrel_ldr: 2472 case ARM::t2MOV_ga_pcrel: { 2473 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode. 2474 unsigned LabelId = AFI->createPICLabelUId(); 2475 Register DstReg = MI.getOperand(0).getReg(); 2476 bool DstIsDead = MI.getOperand(0).isDead(); 2477 const MachineOperand &MO1 = MI.getOperand(1); 2478 const GlobalValue *GV = MO1.getGlobal(); 2479 unsigned TF = MO1.getTargetFlags(); 2480 bool isARM = Opcode != ARM::t2MOV_ga_pcrel; 2481 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; 2482 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; 2483 unsigned LO16TF = TF | ARMII::MO_LO16; 2484 unsigned HI16TF = TF | ARMII::MO_HI16; 2485 unsigned PICAddOpc = isARM 2486 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 2487 : ARM::tPICADD; 2488 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 2489 TII->get(LO16Opc), DstReg) 2490 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) 2491 .addImm(LabelId); 2492 2493 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg) 2494 .addReg(DstReg) 2495 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) 2496 .addImm(LabelId); 2497 2498 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 2499 TII->get(PICAddOpc)) 2500 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 2501 .addReg(DstReg).addImm(LabelId); 2502 if (isARM) { 2503 MIB3.add(predOps(ARMCC::AL)); 2504 if (Opcode == ARM::MOV_ga_pcrel_ldr) 2505 MIB3.cloneMemRefs(MI); 2506 } 2507 TransferImpOps(MI, MIB1, MIB3); 2508 MI.eraseFromParent(); 2509 return true; 2510 } 2511 2512 case ARM::MOVi32imm: 2513 case ARM::MOVCCi32imm: 2514 case ARM::t2MOVi32imm: 2515 case ARM::t2MOVCCi32imm: 2516 ExpandMOV32BitImm(MBB, MBBI); 2517 return true; 2518 2519 case ARM::SUBS_PC_LR: { 2520 MachineInstrBuilder MIB = 2521 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) 2522 .addReg(ARM::LR) 2523 .add(MI.getOperand(0)) 2524 .add(MI.getOperand(1)) 2525 .add(MI.getOperand(2)) 2526 .addReg(ARM::CPSR, RegState::Undef); 2527 TransferImpOps(MI, MIB, MIB); 2528 MI.eraseFromParent(); 2529 return true; 2530 } 2531 case ARM::VLDMQIA: { 2532 unsigned NewOpc = ARM::VLDMDIA; 2533 MachineInstrBuilder MIB = 2534 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 2535 unsigned OpIdx = 0; 2536 2537 // Grab the Q register destination. 2538 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 2539 Register DstReg = MI.getOperand(OpIdx++).getReg(); 2540 2541 // Copy the source register. 2542 MIB.add(MI.getOperand(OpIdx++)); 2543 2544 // Copy the predicate operands. 2545 MIB.add(MI.getOperand(OpIdx++)); 2546 MIB.add(MI.getOperand(OpIdx++)); 2547 2548 // Add the destination operands (D subregs). 2549 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0); 2550 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1); 2551 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 2552 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 2553 2554 // Add an implicit def for the super-register. 2555 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 2556 TransferImpOps(MI, MIB, MIB); 2557 MIB.cloneMemRefs(MI); 2558 MI.eraseFromParent(); 2559 return true; 2560 } 2561 2562 case ARM::VSTMQIA: { 2563 unsigned NewOpc = ARM::VSTMDIA; 2564 MachineInstrBuilder MIB = 2565 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 2566 unsigned OpIdx = 0; 2567 2568 // Grab the Q register source. 2569 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 2570 Register SrcReg = MI.getOperand(OpIdx++).getReg(); 2571 2572 // Copy the destination register. 2573 MachineOperand Dst(MI.getOperand(OpIdx++)); 2574 MIB.add(Dst); 2575 2576 // Copy the predicate operands. 2577 MIB.add(MI.getOperand(OpIdx++)); 2578 MIB.add(MI.getOperand(OpIdx++)); 2579 2580 // Add the source operands (D subregs). 2581 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); 2582 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); 2583 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) 2584 .addReg(D1, SrcIsKill ? RegState::Kill : 0); 2585 2586 if (SrcIsKill) // Add an implicit kill for the Q register. 2587 MIB->addRegisterKilled(SrcReg, TRI, true); 2588 2589 TransferImpOps(MI, MIB, MIB); 2590 MIB.cloneMemRefs(MI); 2591 MI.eraseFromParent(); 2592 return true; 2593 } 2594 2595 case ARM::VLD2q8Pseudo: 2596 case ARM::VLD2q16Pseudo: 2597 case ARM::VLD2q32Pseudo: 2598 case ARM::VLD2q8PseudoWB_fixed: 2599 case ARM::VLD2q16PseudoWB_fixed: 2600 case ARM::VLD2q32PseudoWB_fixed: 2601 case ARM::VLD2q8PseudoWB_register: 2602 case ARM::VLD2q16PseudoWB_register: 2603 case ARM::VLD2q32PseudoWB_register: 2604 case ARM::VLD3d8Pseudo: 2605 case ARM::VLD3d16Pseudo: 2606 case ARM::VLD3d32Pseudo: 2607 case ARM::VLD1d8TPseudo: 2608 case ARM::VLD1d8TPseudoWB_fixed: 2609 case ARM::VLD1d8TPseudoWB_register: 2610 case ARM::VLD1d16TPseudo: 2611 case ARM::VLD1d16TPseudoWB_fixed: 2612 case ARM::VLD1d16TPseudoWB_register: 2613 case ARM::VLD1d32TPseudo: 2614 case ARM::VLD1d32TPseudoWB_fixed: 2615 case ARM::VLD1d32TPseudoWB_register: 2616 case ARM::VLD1d64TPseudo: 2617 case ARM::VLD1d64TPseudoWB_fixed: 2618 case ARM::VLD1d64TPseudoWB_register: 2619 case ARM::VLD3d8Pseudo_UPD: 2620 case ARM::VLD3d16Pseudo_UPD: 2621 case ARM::VLD3d32Pseudo_UPD: 2622 case ARM::VLD3q8Pseudo_UPD: 2623 case ARM::VLD3q16Pseudo_UPD: 2624 case ARM::VLD3q32Pseudo_UPD: 2625 case ARM::VLD3q8oddPseudo: 2626 case ARM::VLD3q16oddPseudo: 2627 case ARM::VLD3q32oddPseudo: 2628 case ARM::VLD3q8oddPseudo_UPD: 2629 case ARM::VLD3q16oddPseudo_UPD: 2630 case ARM::VLD3q32oddPseudo_UPD: 2631 case ARM::VLD4d8Pseudo: 2632 case ARM::VLD4d16Pseudo: 2633 case ARM::VLD4d32Pseudo: 2634 case ARM::VLD1d8QPseudo: 2635 case ARM::VLD1d8QPseudoWB_fixed: 2636 case ARM::VLD1d8QPseudoWB_register: 2637 case ARM::VLD1d16QPseudo: 2638 case ARM::VLD1d16QPseudoWB_fixed: 2639 case ARM::VLD1d16QPseudoWB_register: 2640 case ARM::VLD1d32QPseudo: 2641 case ARM::VLD1d32QPseudoWB_fixed: 2642 case ARM::VLD1d32QPseudoWB_register: 2643 case ARM::VLD1d64QPseudo: 2644 case ARM::VLD1d64QPseudoWB_fixed: 2645 case ARM::VLD1d64QPseudoWB_register: 2646 case ARM::VLD1q8HighQPseudo: 2647 case ARM::VLD1q8HighQPseudo_UPD: 2648 case ARM::VLD1q8LowQPseudo_UPD: 2649 case ARM::VLD1q8HighTPseudo: 2650 case ARM::VLD1q8HighTPseudo_UPD: 2651 case ARM::VLD1q8LowTPseudo_UPD: 2652 case ARM::VLD1q16HighQPseudo: 2653 case ARM::VLD1q16HighQPseudo_UPD: 2654 case ARM::VLD1q16LowQPseudo_UPD: 2655 case ARM::VLD1q16HighTPseudo: 2656 case ARM::VLD1q16HighTPseudo_UPD: 2657 case ARM::VLD1q16LowTPseudo_UPD: 2658 case ARM::VLD1q32HighQPseudo: 2659 case ARM::VLD1q32HighQPseudo_UPD: 2660 case ARM::VLD1q32LowQPseudo_UPD: 2661 case ARM::VLD1q32HighTPseudo: 2662 case ARM::VLD1q32HighTPseudo_UPD: 2663 case ARM::VLD1q32LowTPseudo_UPD: 2664 case ARM::VLD1q64HighQPseudo: 2665 case ARM::VLD1q64HighQPseudo_UPD: 2666 case ARM::VLD1q64LowQPseudo_UPD: 2667 case ARM::VLD1q64HighTPseudo: 2668 case ARM::VLD1q64HighTPseudo_UPD: 2669 case ARM::VLD1q64LowTPseudo_UPD: 2670 case ARM::VLD4d8Pseudo_UPD: 2671 case ARM::VLD4d16Pseudo_UPD: 2672 case ARM::VLD4d32Pseudo_UPD: 2673 case ARM::VLD4q8Pseudo_UPD: 2674 case ARM::VLD4q16Pseudo_UPD: 2675 case ARM::VLD4q32Pseudo_UPD: 2676 case ARM::VLD4q8oddPseudo: 2677 case ARM::VLD4q16oddPseudo: 2678 case ARM::VLD4q32oddPseudo: 2679 case ARM::VLD4q8oddPseudo_UPD: 2680 case ARM::VLD4q16oddPseudo_UPD: 2681 case ARM::VLD4q32oddPseudo_UPD: 2682 case ARM::VLD3DUPd8Pseudo: 2683 case ARM::VLD3DUPd16Pseudo: 2684 case ARM::VLD3DUPd32Pseudo: 2685 case ARM::VLD3DUPd8Pseudo_UPD: 2686 case ARM::VLD3DUPd16Pseudo_UPD: 2687 case ARM::VLD3DUPd32Pseudo_UPD: 2688 case ARM::VLD4DUPd8Pseudo: 2689 case ARM::VLD4DUPd16Pseudo: 2690 case ARM::VLD4DUPd32Pseudo: 2691 case ARM::VLD4DUPd8Pseudo_UPD: 2692 case ARM::VLD4DUPd16Pseudo_UPD: 2693 case ARM::VLD4DUPd32Pseudo_UPD: 2694 case ARM::VLD2DUPq8EvenPseudo: 2695 case ARM::VLD2DUPq8OddPseudo: 2696 case ARM::VLD2DUPq16EvenPseudo: 2697 case ARM::VLD2DUPq16OddPseudo: 2698 case ARM::VLD2DUPq32EvenPseudo: 2699 case ARM::VLD2DUPq32OddPseudo: 2700 case ARM::VLD3DUPq8EvenPseudo: 2701 case ARM::VLD3DUPq8OddPseudo: 2702 case ARM::VLD3DUPq16EvenPseudo: 2703 case ARM::VLD3DUPq16OddPseudo: 2704 case ARM::VLD3DUPq32EvenPseudo: 2705 case ARM::VLD3DUPq32OddPseudo: 2706 case ARM::VLD4DUPq8EvenPseudo: 2707 case ARM::VLD4DUPq8OddPseudo: 2708 case ARM::VLD4DUPq16EvenPseudo: 2709 case ARM::VLD4DUPq16OddPseudo: 2710 case ARM::VLD4DUPq32EvenPseudo: 2711 case ARM::VLD4DUPq32OddPseudo: 2712 ExpandVLD(MBBI); 2713 return true; 2714 2715 case ARM::VST2q8Pseudo: 2716 case ARM::VST2q16Pseudo: 2717 case ARM::VST2q32Pseudo: 2718 case ARM::VST2q8PseudoWB_fixed: 2719 case ARM::VST2q16PseudoWB_fixed: 2720 case ARM::VST2q32PseudoWB_fixed: 2721 case ARM::VST2q8PseudoWB_register: 2722 case ARM::VST2q16PseudoWB_register: 2723 case ARM::VST2q32PseudoWB_register: 2724 case ARM::VST3d8Pseudo: 2725 case ARM::VST3d16Pseudo: 2726 case ARM::VST3d32Pseudo: 2727 case ARM::VST1d8TPseudo: 2728 case ARM::VST1d8TPseudoWB_fixed: 2729 case ARM::VST1d8TPseudoWB_register: 2730 case ARM::VST1d16TPseudo: 2731 case ARM::VST1d16TPseudoWB_fixed: 2732 case ARM::VST1d16TPseudoWB_register: 2733 case ARM::VST1d32TPseudo: 2734 case ARM::VST1d32TPseudoWB_fixed: 2735 case ARM::VST1d32TPseudoWB_register: 2736 case ARM::VST1d64TPseudo: 2737 case ARM::VST1d64TPseudoWB_fixed: 2738 case ARM::VST1d64TPseudoWB_register: 2739 case ARM::VST3d8Pseudo_UPD: 2740 case ARM::VST3d16Pseudo_UPD: 2741 case ARM::VST3d32Pseudo_UPD: 2742 case ARM::VST3q8Pseudo_UPD: 2743 case ARM::VST3q16Pseudo_UPD: 2744 case ARM::VST3q32Pseudo_UPD: 2745 case ARM::VST3q8oddPseudo: 2746 case ARM::VST3q16oddPseudo: 2747 case ARM::VST3q32oddPseudo: 2748 case ARM::VST3q8oddPseudo_UPD: 2749 case ARM::VST3q16oddPseudo_UPD: 2750 case ARM::VST3q32oddPseudo_UPD: 2751 case ARM::VST4d8Pseudo: 2752 case ARM::VST4d16Pseudo: 2753 case ARM::VST4d32Pseudo: 2754 case ARM::VST1d8QPseudo: 2755 case ARM::VST1d8QPseudoWB_fixed: 2756 case ARM::VST1d8QPseudoWB_register: 2757 case ARM::VST1d16QPseudo: 2758 case ARM::VST1d16QPseudoWB_fixed: 2759 case ARM::VST1d16QPseudoWB_register: 2760 case ARM::VST1d32QPseudo: 2761 case ARM::VST1d32QPseudoWB_fixed: 2762 case ARM::VST1d32QPseudoWB_register: 2763 case ARM::VST1d64QPseudo: 2764 case ARM::VST1d64QPseudoWB_fixed: 2765 case ARM::VST1d64QPseudoWB_register: 2766 case ARM::VST4d8Pseudo_UPD: 2767 case ARM::VST4d16Pseudo_UPD: 2768 case ARM::VST4d32Pseudo_UPD: 2769 case ARM::VST1q8HighQPseudo: 2770 case ARM::VST1q8LowQPseudo_UPD: 2771 case ARM::VST1q8HighTPseudo: 2772 case ARM::VST1q8LowTPseudo_UPD: 2773 case ARM::VST1q16HighQPseudo: 2774 case ARM::VST1q16LowQPseudo_UPD: 2775 case ARM::VST1q16HighTPseudo: 2776 case ARM::VST1q16LowTPseudo_UPD: 2777 case ARM::VST1q32HighQPseudo: 2778 case ARM::VST1q32LowQPseudo_UPD: 2779 case ARM::VST1q32HighTPseudo: 2780 case ARM::VST1q32LowTPseudo_UPD: 2781 case ARM::VST1q64HighQPseudo: 2782 case ARM::VST1q64LowQPseudo_UPD: 2783 case ARM::VST1q64HighTPseudo: 2784 case ARM::VST1q64LowTPseudo_UPD: 2785 case ARM::VST1q8HighTPseudo_UPD: 2786 case ARM::VST1q16HighTPseudo_UPD: 2787 case ARM::VST1q32HighTPseudo_UPD: 2788 case ARM::VST1q64HighTPseudo_UPD: 2789 case ARM::VST1q8HighQPseudo_UPD: 2790 case ARM::VST1q16HighQPseudo_UPD: 2791 case ARM::VST1q32HighQPseudo_UPD: 2792 case ARM::VST1q64HighQPseudo_UPD: 2793 case ARM::VST4q8Pseudo_UPD: 2794 case ARM::VST4q16Pseudo_UPD: 2795 case ARM::VST4q32Pseudo_UPD: 2796 case ARM::VST4q8oddPseudo: 2797 case ARM::VST4q16oddPseudo: 2798 case ARM::VST4q32oddPseudo: 2799 case ARM::VST4q8oddPseudo_UPD: 2800 case ARM::VST4q16oddPseudo_UPD: 2801 case ARM::VST4q32oddPseudo_UPD: 2802 ExpandVST(MBBI); 2803 return true; 2804 2805 case ARM::VLD1LNq8Pseudo: 2806 case ARM::VLD1LNq16Pseudo: 2807 case ARM::VLD1LNq32Pseudo: 2808 case ARM::VLD1LNq8Pseudo_UPD: 2809 case ARM::VLD1LNq16Pseudo_UPD: 2810 case ARM::VLD1LNq32Pseudo_UPD: 2811 case ARM::VLD2LNd8Pseudo: 2812 case ARM::VLD2LNd16Pseudo: 2813 case ARM::VLD2LNd32Pseudo: 2814 case ARM::VLD2LNq16Pseudo: 2815 case ARM::VLD2LNq32Pseudo: 2816 case ARM::VLD2LNd8Pseudo_UPD: 2817 case ARM::VLD2LNd16Pseudo_UPD: 2818 case ARM::VLD2LNd32Pseudo_UPD: 2819 case ARM::VLD2LNq16Pseudo_UPD: 2820 case ARM::VLD2LNq32Pseudo_UPD: 2821 case ARM::VLD3LNd8Pseudo: 2822 case ARM::VLD3LNd16Pseudo: 2823 case ARM::VLD3LNd32Pseudo: 2824 case ARM::VLD3LNq16Pseudo: 2825 case ARM::VLD3LNq32Pseudo: 2826 case ARM::VLD3LNd8Pseudo_UPD: 2827 case ARM::VLD3LNd16Pseudo_UPD: 2828 case ARM::VLD3LNd32Pseudo_UPD: 2829 case ARM::VLD3LNq16Pseudo_UPD: 2830 case ARM::VLD3LNq32Pseudo_UPD: 2831 case ARM::VLD4LNd8Pseudo: 2832 case ARM::VLD4LNd16Pseudo: 2833 case ARM::VLD4LNd32Pseudo: 2834 case ARM::VLD4LNq16Pseudo: 2835 case ARM::VLD4LNq32Pseudo: 2836 case ARM::VLD4LNd8Pseudo_UPD: 2837 case ARM::VLD4LNd16Pseudo_UPD: 2838 case ARM::VLD4LNd32Pseudo_UPD: 2839 case ARM::VLD4LNq16Pseudo_UPD: 2840 case ARM::VLD4LNq32Pseudo_UPD: 2841 case ARM::VST1LNq8Pseudo: 2842 case ARM::VST1LNq16Pseudo: 2843 case ARM::VST1LNq32Pseudo: 2844 case ARM::VST1LNq8Pseudo_UPD: 2845 case ARM::VST1LNq16Pseudo_UPD: 2846 case ARM::VST1LNq32Pseudo_UPD: 2847 case ARM::VST2LNd8Pseudo: 2848 case ARM::VST2LNd16Pseudo: 2849 case ARM::VST2LNd32Pseudo: 2850 case ARM::VST2LNq16Pseudo: 2851 case ARM::VST2LNq32Pseudo: 2852 case ARM::VST2LNd8Pseudo_UPD: 2853 case ARM::VST2LNd16Pseudo_UPD: 2854 case ARM::VST2LNd32Pseudo_UPD: 2855 case ARM::VST2LNq16Pseudo_UPD: 2856 case ARM::VST2LNq32Pseudo_UPD: 2857 case ARM::VST3LNd8Pseudo: 2858 case ARM::VST3LNd16Pseudo: 2859 case ARM::VST3LNd32Pseudo: 2860 case ARM::VST3LNq16Pseudo: 2861 case ARM::VST3LNq32Pseudo: 2862 case ARM::VST3LNd8Pseudo_UPD: 2863 case ARM::VST3LNd16Pseudo_UPD: 2864 case ARM::VST3LNd32Pseudo_UPD: 2865 case ARM::VST3LNq16Pseudo_UPD: 2866 case ARM::VST3LNq32Pseudo_UPD: 2867 case ARM::VST4LNd8Pseudo: 2868 case ARM::VST4LNd16Pseudo: 2869 case ARM::VST4LNd32Pseudo: 2870 case ARM::VST4LNq16Pseudo: 2871 case ARM::VST4LNq32Pseudo: 2872 case ARM::VST4LNd8Pseudo_UPD: 2873 case ARM::VST4LNd16Pseudo_UPD: 2874 case ARM::VST4LNd32Pseudo_UPD: 2875 case ARM::VST4LNq16Pseudo_UPD: 2876 case ARM::VST4LNq32Pseudo_UPD: 2877 ExpandLaneOp(MBBI); 2878 return true; 2879 2880 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; 2881 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; 2882 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; 2883 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; 2884 2885 case ARM::tCMP_SWAP_8: 2886 assert(STI->isThumb()); 2887 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, ARM::tUXTB, 2888 NextMBBI); 2889 case ARM::tCMP_SWAP_16: 2890 assert(STI->isThumb()); 2891 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, ARM::tUXTH, 2892 NextMBBI); 2893 2894 case ARM::CMP_SWAP_8: 2895 assert(!STI->isThumb()); 2896 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, ARM::UXTB, 2897 NextMBBI); 2898 case ARM::CMP_SWAP_16: 2899 assert(!STI->isThumb()); 2900 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, ARM::UXTH, 2901 NextMBBI); 2902 case ARM::CMP_SWAP_32: 2903 if (STI->isThumb()) 2904 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, 2905 NextMBBI); 2906 else 2907 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); 2908 2909 case ARM::CMP_SWAP_64: 2910 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI); 2911 2912 case ARM::tBL_PUSHLR: 2913 case ARM::BL_PUSHLR: { 2914 const bool Thumb = Opcode == ARM::tBL_PUSHLR; 2915 Register Reg = MI.getOperand(0).getReg(); 2916 assert(Reg == ARM::LR && "expect LR register!"); 2917 MachineInstrBuilder MIB; 2918 if (Thumb) { 2919 // push {lr} 2920 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH)) 2921 .add(predOps(ARMCC::AL)) 2922 .addReg(Reg); 2923 2924 // bl __gnu_mcount_nc 2925 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL)); 2926 } else { 2927 // stmdb sp!, {lr} 2928 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD)) 2929 .addReg(ARM::SP, RegState::Define) 2930 .addReg(ARM::SP) 2931 .add(predOps(ARMCC::AL)) 2932 .addReg(Reg); 2933 2934 // bl __gnu_mcount_nc 2935 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL)); 2936 } 2937 MIB.cloneMemRefs(MI); 2938 for (unsigned i = 1; i < MI.getNumOperands(); ++i) MIB.add(MI.getOperand(i)); 2939 MI.eraseFromParent(); 2940 return true; 2941 } 2942 case ARM::LOADDUAL: 2943 case ARM::STOREDUAL: { 2944 Register PairReg = MI.getOperand(0).getReg(); 2945 2946 MachineInstrBuilder MIB = 2947 BuildMI(MBB, MBBI, MI.getDebugLoc(), 2948 TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD)) 2949 .addReg(TRI->getSubReg(PairReg, ARM::gsub_0), 2950 Opcode == ARM::LOADDUAL ? RegState::Define : 0) 2951 .addReg(TRI->getSubReg(PairReg, ARM::gsub_1), 2952 Opcode == ARM::LOADDUAL ? RegState::Define : 0); 2953 for (unsigned i = 1; i < MI.getNumOperands(); i++) 2954 MIB.add(MI.getOperand(i)); 2955 MIB.add(predOps(ARMCC::AL)); 2956 MIB.cloneMemRefs(MI); 2957 MI.eraseFromParent(); 2958 return true; 2959 } 2960 } 2961 } 2962 2963 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 2964 bool Modified = false; 2965 2966 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 2967 while (MBBI != E) { 2968 MachineBasicBlock::iterator NMBBI = std::next(MBBI); 2969 Modified |= ExpandMI(MBB, MBBI, NMBBI); 2970 MBBI = NMBBI; 2971 } 2972 2973 return Modified; 2974 } 2975 2976 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 2977 STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget()); 2978 TII = STI->getInstrInfo(); 2979 TRI = STI->getRegisterInfo(); 2980 AFI = MF.getInfo<ARMFunctionInfo>(); 2981 2982 LLVM_DEBUG(dbgs() << "********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n" 2983 << "********** Function: " << MF.getName() << '\n'); 2984 2985 bool Modified = false; 2986 for (MachineBasicBlock &MBB : MF) 2987 Modified |= ExpandMBB(MBB); 2988 if (VerifyARMPseudo) 2989 MF.verify(this, "After expanding ARM pseudo instructions."); 2990 2991 LLVM_DEBUG(dbgs() << "***************************************************\n"); 2992 return Modified; 2993 } 2994 2995 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction 2996 /// expansion pass. 2997 FunctionPass *llvm::createARMExpandPseudoPass() { 2998 return new ARMExpandPseudo(); 2999 } 3000