1 //===----------------------- SIFrameLowering.cpp --------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //==-----------------------------------------------------------------------===//
9 
10 #include "SIFrameLowering.h"
11 #include "SIInstrInfo.h"
12 #include "SIMachineFunctionInfo.h"
13 #include "SIRegisterInfo.h"
14 #include "llvm/CodeGen/MachineFrameInfo.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/RegisterScavenging.h"
18 
19 using namespace llvm;
20 
21 
22 static bool hasOnlySGPRSpills(const SIMachineFunctionInfo *FuncInfo,
23                               const MachineFrameInfo *FrameInfo) {
24   if (!FuncInfo->hasSpilledSGPRs())
25     return false;
26 
27   if (FuncInfo->hasSpilledVGPRs())
28     return false;
29 
30   for (int I = FrameInfo->getObjectIndexBegin(),
31          E = FrameInfo->getObjectIndexEnd(); I != E; ++I) {
32     if (!FrameInfo->isSpillSlotObjectIndex(I))
33       return false;
34   }
35 
36   return true;
37 }
38 
39 static ArrayRef<MCPhysReg> getAllSGPR128() {
40   return makeArrayRef(AMDGPU::SReg_128RegClass.begin(),
41                       AMDGPU::SReg_128RegClass.getNumRegs());
42 }
43 
44 static ArrayRef<MCPhysReg> getAllSGPRs() {
45   return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(),
46                       AMDGPU::SGPR_32RegClass.getNumRegs());
47 }
48 
49 void SIFrameLowering::emitPrologue(MachineFunction &MF,
50                                    MachineBasicBlock &MBB) const {
51   if (!MF.getFrameInfo()->hasStackObjects())
52     return;
53 
54   assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
55 
56   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
57 
58   // If we only have SGPR spills, we won't actually be using scratch memory
59   // since these spill to VGPRs.
60   //
61   // FIXME: We should be cleaning up these unused SGPR spill frame indices
62   // somewhere.
63   if (hasOnlySGPRSpills(MFI, MF.getFrameInfo()))
64     return;
65 
66   const SIInstrInfo *TII =
67       static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
68   const SIRegisterInfo *TRI = &TII->getRegisterInfo();
69   const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
70 
71   // We need to insert initialization of the scratch resource descriptor.
72   unsigned ScratchRsrcReg = MFI->getScratchRSrcReg();
73   assert(ScratchRsrcReg != AMDGPU::NoRegister);
74 
75   unsigned ScratchWaveOffsetReg = MFI->getScratchWaveOffsetReg();
76   assert(ScratchWaveOffsetReg != AMDGPU::NoRegister);
77 
78   unsigned PreloadedScratchWaveOffsetReg = TRI->getPreloadedValue(
79     MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
80 
81   unsigned PreloadedPrivateBufferReg = AMDGPU::NoRegister;
82   if (ST.isAmdHsaOS()) {
83     PreloadedPrivateBufferReg = TRI->getPreloadedValue(
84       MF, SIRegisterInfo::PRIVATE_SEGMENT_BUFFER);
85   }
86 
87   // If we reserved the original input registers, we don't need to copy to the
88   // reserved registers.
89   if (ScratchRsrcReg == PreloadedPrivateBufferReg) {
90     // We should always reserve these 5 registers at the same time.
91     assert(ScratchWaveOffsetReg == PreloadedScratchWaveOffsetReg &&
92            "scratch wave offset and private segment buffer inconsistent");
93     return;
94   }
95 
96 
97   // We added live-ins during argument lowering, but since they were not used
98   // they were deleted. We're adding the uses now, so add them back.
99   MachineRegisterInfo &MRI = MF.getRegInfo();
100   MRI.addLiveIn(PreloadedScratchWaveOffsetReg);
101   MBB.addLiveIn(PreloadedScratchWaveOffsetReg);
102 
103   if (ST.isAmdHsaOS()) {
104     MRI.addLiveIn(PreloadedPrivateBufferReg);
105     MBB.addLiveIn(PreloadedPrivateBufferReg);
106   }
107 
108   if (!ST.hasSGPRInitBug()) {
109     // We reserved the last registers for this. Shift it down to the end of those
110     // which were actually used.
111     //
112     // FIXME: It might be safer to use a pseudoregister before replacement.
113 
114     // FIXME: We should be able to eliminate unused input registers. We only
115     // cannot do this for the resources required for scratch access. For now we
116     // skip over user SGPRs and may leave unused holes.
117 
118     // We find the resource first because it has an alignment requirement.
119     if (ScratchRsrcReg == TRI->reservedPrivateSegmentBufferReg(MF)) {
120       MachineRegisterInfo &MRI = MF.getRegInfo();
121 
122       unsigned NumPreloaded = MFI->getNumPreloadedSGPRs() / 4;
123       // Skip the last 2 elements because the last one is reserved for VCC, and
124       // this is the 2nd to last element already.
125       for (MCPhysReg Reg : getAllSGPR128().drop_back(2).slice(NumPreloaded)) {
126         // Pick the first unallocated one. Make sure we don't clobber the other
127         // reserved input we needed.
128         if (!MRI.isPhysRegUsed(Reg)) {
129           assert(MRI.isAllocatable(Reg));
130           MRI.replaceRegWith(ScratchRsrcReg, Reg);
131           ScratchRsrcReg = Reg;
132           MFI->setScratchRSrcReg(ScratchRsrcReg);
133           break;
134         }
135       }
136     }
137 
138     if (ScratchWaveOffsetReg == TRI->reservedPrivateSegmentWaveByteOffsetReg(MF)) {
139       MachineRegisterInfo &MRI = MF.getRegInfo();
140       // Skip the last 2 elements because the last one is reserved for VCC, and
141       // this is the 2nd to last element already.
142       unsigned NumPreloaded = MFI->getNumPreloadedSGPRs();
143       for (MCPhysReg Reg : getAllSGPRs().drop_back(6).slice(NumPreloaded)) {
144         // Pick the first unallocated SGPR. Be careful not to pick an alias of the
145         // scratch descriptor, since we haven’t added its uses yet.
146         if (!MRI.isPhysRegUsed(Reg)) {
147           assert(MRI.isAllocatable(Reg) &&
148                 !TRI->isSubRegisterEq(ScratchRsrcReg, Reg));
149 
150           MRI.replaceRegWith(ScratchWaveOffsetReg, Reg);
151           ScratchWaveOffsetReg = Reg;
152           MFI->setScratchWaveOffsetReg(ScratchWaveOffsetReg);
153           break;
154         }
155       }
156     }
157   }
158 
159 
160   assert(!TRI->isSubRegister(ScratchRsrcReg, ScratchWaveOffsetReg));
161 
162   const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
163   MachineBasicBlock::iterator I = MBB.begin();
164   DebugLoc DL;
165 
166   if (PreloadedScratchWaveOffsetReg != ScratchWaveOffsetReg) {
167     // Make sure we emit the copy for the offset first. We may have chosen to copy
168     // the buffer resource into a register that aliases the input offset register.
169     BuildMI(MBB, I, DL, SMovB32, ScratchWaveOffsetReg)
170       .addReg(PreloadedScratchWaveOffsetReg, RegState::Kill);
171   }
172 
173   if (ST.isAmdHsaOS()) {
174     // Insert copies from argument register.
175     assert(
176       !TRI->isSubRegisterEq(PreloadedPrivateBufferReg, ScratchRsrcReg) &&
177       !TRI->isSubRegisterEq(PreloadedPrivateBufferReg, ScratchWaveOffsetReg));
178 
179     unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
180     unsigned Rsrc23 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2_sub3);
181 
182     unsigned Lo = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub0_sub1);
183     unsigned Hi = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub2_sub3);
184 
185     const MCInstrDesc &SMovB64 = TII->get(AMDGPU::S_MOV_B64);
186 
187     BuildMI(MBB, I, DL, SMovB64, Rsrc01)
188       .addReg(Lo, RegState::Kill);
189     BuildMI(MBB, I, DL, SMovB64, Rsrc23)
190       .addReg(Hi, RegState::Kill);
191   } else {
192     unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
193     unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
194     unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
195     unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
196 
197     // Use relocations to get the pointer, and setup the other bits manually.
198     uint64_t Rsrc23 = TII->getScratchRsrcWords23();
199     BuildMI(MBB, I, DL, SMovB32, Rsrc0)
200       .addExternalSymbol("SCRATCH_RSRC_DWORD0")
201       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
202 
203     BuildMI(MBB, I, DL, SMovB32, Rsrc1)
204       .addExternalSymbol("SCRATCH_RSRC_DWORD1")
205       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
206 
207     BuildMI(MBB, I, DL, SMovB32, Rsrc2)
208       .addImm(Rsrc23 & 0xffffffff)
209       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
210 
211     BuildMI(MBB, I, DL, SMovB32, Rsrc3)
212       .addImm(Rsrc23 >> 32)
213       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
214   }
215 
216   // Make the register selected live throughout the function.
217   for (MachineBasicBlock &OtherBB : MF) {
218     if (&OtherBB == &MBB)
219       continue;
220 
221     OtherBB.addLiveIn(ScratchRsrcReg);
222     OtherBB.addLiveIn(ScratchWaveOffsetReg);
223   }
224 }
225 
226 void SIFrameLowering::processFunctionBeforeFrameFinalized(
227   MachineFunction &MF,
228   RegScavenger *RS) const {
229   MachineFrameInfo *MFI = MF.getFrameInfo();
230 
231   if (!MFI->hasStackObjects())
232     return;
233 
234   bool MayNeedScavengingEmergencySlot = MFI->hasStackObjects();
235 
236   assert((RS || !MayNeedScavengingEmergencySlot) &&
237          "RegScavenger required if spilling");
238 
239   if (MayNeedScavengingEmergencySlot) {
240     int ScavengeFI = MFI->CreateSpillStackObject(
241       AMDGPU::SGPR_32RegClass.getSize(),
242       AMDGPU::SGPR_32RegClass.getAlignment());
243     RS->addScavengingFrameIndex(ScavengeFI);
244   }
245 }
246