1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPU.h" 15 #include "SIDefines.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/ADT/Twine.h" 19 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/IR/Constants.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/IR/Metadata.h" 24 #include "llvm/IR/Module.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCELFStreamer.h" 27 #include "llvm/MC/MCObjectFileInfo.h" 28 #include "llvm/MC/MCSectionELF.h" 29 #include "llvm/Support/FormattedStream.h" 30 #include "llvm/Support/TargetParser.h" 31 32 namespace llvm { 33 #include "AMDGPUPTNote.h" 34 } 35 36 using namespace llvm; 37 using namespace llvm::AMDGPU; 38 using namespace llvm::AMDGPU::HSAMD; 39 40 //===----------------------------------------------------------------------===// 41 // AMDGPUTargetStreamer 42 //===----------------------------------------------------------------------===// 43 44 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 45 HSAMD::Metadata HSAMetadata; 46 if (HSAMD::fromString(std::string(HSAMetadataString), HSAMetadata)) 47 return false; 48 49 return EmitHSAMetadata(HSAMetadata); 50 } 51 52 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 53 msgpack::Document HSAMetadataDoc; 54 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 55 return false; 56 return EmitHSAMetadata(HSAMetadataDoc, false); 57 } 58 59 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 60 AMDGPU::GPUKind AK; 61 62 switch (ElfMach) { 63 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type"); 64 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 65 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 66 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 67 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 68 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 69 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 70 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 71 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 72 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 73 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 74 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 75 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 76 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 77 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 78 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 79 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 80 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 81 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 82 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break; 106 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 107 } 108 109 StringRef GPUName = getArchNameAMDGCN(AK); 110 if (GPUName != "") 111 return GPUName; 112 return getArchNameR600(AK); 113 } 114 115 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 116 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 117 if (AK == AMDGPU::GPUKind::GK_NONE) 118 AK = parseArchR600(GPU); 119 120 switch (AK) { 121 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 122 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 123 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 124 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 125 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 126 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 127 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 128 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 129 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 130 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 131 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 132 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 133 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 134 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 135 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 136 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 137 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 138 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 139 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602; 140 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 141 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 142 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 143 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 144 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 145 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705; 146 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 147 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 148 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 149 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805; 150 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 151 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 152 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 153 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 154 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 155 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 156 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 157 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 158 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 159 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 160 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 161 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 162 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032; 163 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 164 } 165 166 llvm_unreachable("unknown GPU"); 167 } 168 169 //===----------------------------------------------------------------------===// 170 // AMDGPUTargetAsmStreamer 171 //===----------------------------------------------------------------------===// 172 173 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 174 formatted_raw_ostream &OS) 175 : AMDGPUTargetStreamer(S), OS(OS) { } 176 177 // A hook for emitting stuff at the end. 178 // We use it for emitting the accumulated PAL metadata as directives. 179 // The PAL metadata is reset after it is emitted. 180 void AMDGPUTargetAsmStreamer::finish() { 181 std::string S; 182 getPALMetadata()->toString(S); 183 OS << S; 184 185 // Reset the pal metadata so its data will not affect a compilation that 186 // reuses this object. 187 getPALMetadata()->reset(); 188 } 189 190 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) { 191 OS << "\t.amdgcn_target \"" << Target << "\"\n"; 192 } 193 194 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 195 uint32_t Major, uint32_t Minor) { 196 OS << "\t.hsa_code_object_version " << 197 Twine(Major) << "," << Twine(Minor) << '\n'; 198 } 199 200 void 201 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 202 uint32_t Minor, 203 uint32_t Stepping, 204 StringRef VendorName, 205 StringRef ArchName) { 206 OS << "\t.hsa_code_object_isa " << 207 Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) << 208 ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 209 210 } 211 212 void 213 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 214 OS << "\t.amd_kernel_code_t\n"; 215 dumpAmdKernelCode(&Header, OS, "\t\t"); 216 OS << "\t.end_amd_kernel_code_t\n"; 217 } 218 219 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 220 unsigned Type) { 221 switch (Type) { 222 default: llvm_unreachable("Invalid AMDGPU symbol type"); 223 case ELF::STT_AMDGPU_HSA_KERNEL: 224 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 225 break; 226 } 227 } 228 229 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 230 Align Alignment) { 231 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 232 << Alignment.value() << '\n'; 233 } 234 235 bool AMDGPUTargetAsmStreamer::EmitISAVersion(StringRef IsaVersionString) { 236 OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n"; 237 return true; 238 } 239 240 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 241 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 242 std::string HSAMetadataString; 243 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 244 return false; 245 246 OS << '\t' << AssemblerDirectiveBegin << '\n'; 247 OS << HSAMetadataString << '\n'; 248 OS << '\t' << AssemblerDirectiveEnd << '\n'; 249 return true; 250 } 251 252 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 253 msgpack::Document &HSAMetadataDoc, bool Strict) { 254 V3::MetadataVerifier Verifier(Strict); 255 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 256 return false; 257 258 std::string HSAMetadataString; 259 raw_string_ostream StrOS(HSAMetadataString); 260 HSAMetadataDoc.toYAML(StrOS); 261 262 OS << '\t' << V3::AssemblerDirectiveBegin << '\n'; 263 OS << StrOS.str() << '\n'; 264 OS << '\t' << V3::AssemblerDirectiveEnd << '\n'; 265 return true; 266 } 267 268 bool AMDGPUTargetAsmStreamer::EmitCodeEnd() { 269 const uint32_t Encoded_s_code_end = 0xbf9f0000; 270 OS << "\t.p2alignl 6, " << Encoded_s_code_end << '\n'; 271 OS << "\t.fill 48, 4, " << Encoded_s_code_end << '\n'; 272 return true; 273 } 274 275 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 276 const MCSubtargetInfo &STI, StringRef KernelName, 277 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 278 bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) { 279 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 280 281 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 282 283 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 284 STREAM << "\t\t" << DIRECTIVE << " " \ 285 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 286 287 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 288 << '\n'; 289 OS << "\t\t.amdhsa_private_segment_fixed_size " 290 << KD.private_segment_fixed_size << '\n'; 291 292 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 293 kernel_code_properties, 294 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 295 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 296 kernel_code_properties, 297 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 298 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 299 kernel_code_properties, 300 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 301 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 302 kernel_code_properties, 303 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 304 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 305 kernel_code_properties, 306 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 307 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 308 kernel_code_properties, 309 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 310 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 311 kernel_code_properties, 312 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 313 if (IVersion.Major >= 10) 314 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 315 kernel_code_properties, 316 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 317 PRINT_FIELD( 318 OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, 319 compute_pgm_rsrc2, 320 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET); 321 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 322 compute_pgm_rsrc2, 323 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 324 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 325 compute_pgm_rsrc2, 326 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 327 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 328 compute_pgm_rsrc2, 329 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 330 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 331 compute_pgm_rsrc2, 332 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 333 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 334 compute_pgm_rsrc2, 335 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 336 337 // These directives are required. 338 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 339 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 340 341 if (!ReserveVCC) 342 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 343 if (IVersion.Major >= 7 && !ReserveFlatScr) 344 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 345 if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI)) 346 OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n'; 347 348 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 349 compute_pgm_rsrc1, 350 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 351 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 352 compute_pgm_rsrc1, 353 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 354 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 355 compute_pgm_rsrc1, 356 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 357 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 358 compute_pgm_rsrc1, 359 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 360 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 361 compute_pgm_rsrc1, 362 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 363 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 364 compute_pgm_rsrc1, 365 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 366 if (IVersion.Major >= 9) 367 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 368 compute_pgm_rsrc1, 369 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 370 if (IVersion.Major >= 10) { 371 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 372 compute_pgm_rsrc1, 373 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 374 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 375 compute_pgm_rsrc1, 376 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 377 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 378 compute_pgm_rsrc1, 379 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 380 } 381 PRINT_FIELD( 382 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 383 compute_pgm_rsrc2, 384 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 385 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 386 compute_pgm_rsrc2, 387 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 388 PRINT_FIELD( 389 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 390 compute_pgm_rsrc2, 391 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 392 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 393 compute_pgm_rsrc2, 394 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 395 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 396 compute_pgm_rsrc2, 397 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 398 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 399 compute_pgm_rsrc2, 400 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 401 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 402 compute_pgm_rsrc2, 403 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 404 #undef PRINT_FIELD 405 406 OS << "\t.end_amdhsa_kernel\n"; 407 } 408 409 //===----------------------------------------------------------------------===// 410 // AMDGPUTargetELFStreamer 411 //===----------------------------------------------------------------------===// 412 413 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 414 const MCSubtargetInfo &STI) 415 : AMDGPUTargetStreamer(S), Streamer(S), Os(STI.getTargetTriple().getOS()) { 416 MCAssembler &MCA = getStreamer().getAssembler(); 417 unsigned EFlags = MCA.getELFHeaderEFlags(); 418 419 EFlags &= ~ELF::EF_AMDGPU_MACH; 420 EFlags |= getElfMach(STI.getCPU()); 421 422 EFlags &= ~ELF::EF_AMDGPU_XNACK; 423 if (AMDGPU::hasXNACK(STI)) 424 EFlags |= ELF::EF_AMDGPU_XNACK; 425 426 EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC; 427 if (AMDGPU::hasSRAMECC(STI)) 428 EFlags |= ELF::EF_AMDGPU_SRAM_ECC; 429 430 MCA.setELFHeaderEFlags(EFlags); 431 } 432 433 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 434 return static_cast<MCELFStreamer &>(Streamer); 435 } 436 437 // A hook for emitting stuff at the end. 438 // We use it for emitting the accumulated PAL metadata as a .note record. 439 // The PAL metadata is reset after it is emitted. 440 void AMDGPUTargetELFStreamer::finish() { 441 std::string Blob; 442 const char *Vendor = getPALMetadata()->getVendor(); 443 unsigned Type = getPALMetadata()->getType(); 444 getPALMetadata()->toBlob(Type, Blob); 445 if (Blob.empty()) 446 return; 447 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 448 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 449 450 // Reset the pal metadata so its data will not affect a compilation that 451 // reuses this object. 452 getPALMetadata()->reset(); 453 } 454 455 void AMDGPUTargetELFStreamer::EmitNote( 456 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 457 function_ref<void(MCELFStreamer &)> EmitDesc) { 458 auto &S = getStreamer(); 459 auto &Context = S.getContext(); 460 461 auto NameSZ = Name.size() + 1; 462 463 unsigned NoteFlags = 0; 464 // TODO Apparently, this is currently needed for OpenCL as mentioned in 465 // https://reviews.llvm.org/D74995 466 if (Os == Triple::AMDHSA) 467 NoteFlags = ELF::SHF_ALLOC; 468 469 S.PushSection(); 470 S.SwitchSection( 471 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 472 S.emitInt32(NameSZ); // namesz 473 S.emitValue(DescSZ, 4); // descz 474 S.emitInt32(NoteType); // type 475 S.emitBytes(Name); // name 476 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 477 EmitDesc(S); // desc 478 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 479 S.PopSection(); 480 } 481 482 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {} 483 484 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 485 uint32_t Major, uint32_t Minor) { 486 487 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 488 ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 489 OS.emitInt32(Major); 490 OS.emitInt32(Minor); 491 }); 492 } 493 494 void 495 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 496 uint32_t Minor, 497 uint32_t Stepping, 498 StringRef VendorName, 499 StringRef ArchName) { 500 uint16_t VendorNameSize = VendorName.size() + 1; 501 uint16_t ArchNameSize = ArchName.size() + 1; 502 503 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 504 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 505 VendorNameSize + ArchNameSize; 506 507 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 508 ElfNote::NT_AMDGPU_HSA_ISA, [&](MCELFStreamer &OS) { 509 OS.emitInt16(VendorNameSize); 510 OS.emitInt16(ArchNameSize); 511 OS.emitInt32(Major); 512 OS.emitInt32(Minor); 513 OS.emitInt32(Stepping); 514 OS.emitBytes(VendorName); 515 OS.emitInt8(0); // NULL terminate VendorName 516 OS.emitBytes(ArchName); 517 OS.emitInt8(0); // NULL terminte ArchName 518 }); 519 } 520 521 void 522 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 523 524 MCStreamer &OS = getStreamer(); 525 OS.PushSection(); 526 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 527 OS.PopSection(); 528 } 529 530 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 531 unsigned Type) { 532 MCSymbolELF *Symbol = cast<MCSymbolELF>( 533 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 534 Symbol->setType(Type); 535 } 536 537 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 538 Align Alignment) { 539 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 540 SymbolELF->setType(ELF::STT_OBJECT); 541 542 if (!SymbolELF->isBindingSet()) { 543 SymbolELF->setBinding(ELF::STB_GLOBAL); 544 SymbolELF->setExternal(true); 545 } 546 547 if (SymbolELF->declareCommon(Size, Alignment.value(), true)) { 548 report_fatal_error("Symbol: " + Symbol->getName() + 549 " redeclared as different type"); 550 } 551 552 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 553 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 554 } 555 556 bool AMDGPUTargetELFStreamer::EmitISAVersion(StringRef IsaVersionString) { 557 // Create two labels to mark the beginning and end of the desc field 558 // and a MCExpr to calculate the size of the desc field. 559 auto &Context = getContext(); 560 auto *DescBegin = Context.createTempSymbol(); 561 auto *DescEnd = Context.createTempSymbol(); 562 auto *DescSZ = MCBinaryExpr::createSub( 563 MCSymbolRefExpr::create(DescEnd, Context), 564 MCSymbolRefExpr::create(DescBegin, Context), Context); 565 566 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_ISA, 567 [&](MCELFStreamer &OS) { 568 OS.emitLabel(DescBegin); 569 OS.emitBytes(IsaVersionString); 570 OS.emitLabel(DescEnd); 571 }); 572 return true; 573 } 574 575 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 576 bool Strict) { 577 V3::MetadataVerifier Verifier(Strict); 578 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 579 return false; 580 581 std::string HSAMetadataString; 582 HSAMetadataDoc.writeToBlob(HSAMetadataString); 583 584 // Create two labels to mark the beginning and end of the desc field 585 // and a MCExpr to calculate the size of the desc field. 586 auto &Context = getContext(); 587 auto *DescBegin = Context.createTempSymbol(); 588 auto *DescEnd = Context.createTempSymbol(); 589 auto *DescSZ = MCBinaryExpr::createSub( 590 MCSymbolRefExpr::create(DescEnd, Context), 591 MCSymbolRefExpr::create(DescBegin, Context), Context); 592 593 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 594 [&](MCELFStreamer &OS) { 595 OS.emitLabel(DescBegin); 596 OS.emitBytes(HSAMetadataString); 597 OS.emitLabel(DescEnd); 598 }); 599 return true; 600 } 601 602 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 603 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 604 std::string HSAMetadataString; 605 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 606 return false; 607 608 // Create two labels to mark the beginning and end of the desc field 609 // and a MCExpr to calculate the size of the desc field. 610 auto &Context = getContext(); 611 auto *DescBegin = Context.createTempSymbol(); 612 auto *DescEnd = Context.createTempSymbol(); 613 auto *DescSZ = MCBinaryExpr::createSub( 614 MCSymbolRefExpr::create(DescEnd, Context), 615 MCSymbolRefExpr::create(DescBegin, Context), Context); 616 617 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_HSA_METADATA, 618 [&](MCELFStreamer &OS) { 619 OS.emitLabel(DescBegin); 620 OS.emitBytes(HSAMetadataString); 621 OS.emitLabel(DescEnd); 622 }); 623 return true; 624 } 625 626 bool AMDGPUTargetELFStreamer::EmitCodeEnd() { 627 const uint32_t Encoded_s_code_end = 0xbf9f0000; 628 629 MCStreamer &OS = getStreamer(); 630 OS.PushSection(); 631 OS.emitValueToAlignment(64, Encoded_s_code_end, 4); 632 for (unsigned I = 0; I < 48; ++I) 633 OS.emitInt32(Encoded_s_code_end); 634 OS.PopSection(); 635 return true; 636 } 637 638 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 639 const MCSubtargetInfo &STI, StringRef KernelName, 640 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 641 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, 642 bool ReserveXNACK) { 643 auto &Streamer = getStreamer(); 644 auto &Context = Streamer.getContext(); 645 646 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 647 Context.getOrCreateSymbol(Twine(KernelName))); 648 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 649 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 650 651 // Copy kernel descriptor symbol's binding, other and visibility from the 652 // kernel code symbol. 653 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 654 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 655 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 656 // Kernel descriptor symbol's type and size are fixed. 657 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 658 KernelDescriptorSymbol->setSize( 659 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 660 661 // The visibility of the kernel code symbol must be protected or less to allow 662 // static relocations from the kernel descriptor to be used. 663 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 664 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 665 666 Streamer.emitLabel(KernelDescriptorSymbol); 667 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size); 668 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size); 669 for (uint8_t Res : KernelDescriptor.reserved0) 670 Streamer.emitInt8(Res); 671 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 672 // expression being created is: 673 // (start of kernel code) - (start of kernel descriptor) 674 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 675 Streamer.emitValue(MCBinaryExpr::createSub( 676 MCSymbolRefExpr::create( 677 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 678 MCSymbolRefExpr::create( 679 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 680 Context), 681 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 682 for (uint8_t Res : KernelDescriptor.reserved1) 683 Streamer.emitInt8(Res); 684 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3); 685 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1); 686 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2); 687 Streamer.emitInt16(KernelDescriptor.kernel_code_properties); 688 for (uint8_t Res : KernelDescriptor.reserved2) 689 Streamer.emitInt8(Res); 690 } 691