1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPU.h" 15 #include "SIDefines.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/ADT/Twine.h" 19 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/BinaryFormat/MsgPackTypes.h" 22 #include "llvm/IR/Constants.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/IR/Metadata.h" 25 #include "llvm/IR/Module.h" 26 #include "llvm/MC/MCContext.h" 27 #include "llvm/MC/MCELFStreamer.h" 28 #include "llvm/MC/MCObjectFileInfo.h" 29 #include "llvm/MC/MCSectionELF.h" 30 #include "llvm/Support/FormattedStream.h" 31 #include "llvm/Support/TargetParser.h" 32 33 namespace llvm { 34 #include "AMDGPUPTNote.h" 35 } 36 37 using namespace llvm; 38 using namespace llvm::AMDGPU; 39 using namespace llvm::AMDGPU::HSAMD; 40 41 //===----------------------------------------------------------------------===// 42 // AMDGPUTargetStreamer 43 //===----------------------------------------------------------------------===// 44 45 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 46 HSAMD::Metadata HSAMetadata; 47 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 48 return false; 49 50 return EmitHSAMetadata(HSAMetadata); 51 } 52 53 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 54 std::shared_ptr<msgpack::Node> HSAMetadataRoot; 55 yaml::Input YIn(HSAMetadataString); 56 YIn >> HSAMetadataRoot; 57 if (YIn.error()) 58 return false; 59 return EmitHSAMetadata(HSAMetadataRoot, false); 60 } 61 62 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 63 AMDGPU::GPUKind AK; 64 65 switch (ElfMach) { 66 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 67 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 68 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 69 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 70 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 71 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 72 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 73 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 74 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 75 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 76 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 77 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 78 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 79 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 80 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 81 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 82 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 98 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 99 } 100 101 StringRef GPUName = getArchNameAMDGCN(AK); 102 if (GPUName != "") 103 return GPUName; 104 return getArchNameR600(AK); 105 } 106 107 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 108 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 109 if (AK == AMDGPU::GPUKind::GK_NONE) 110 AK = parseArchR600(GPU); 111 112 switch (AK) { 113 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 114 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 115 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 116 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 117 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 118 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 119 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 120 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 121 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 122 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 123 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 124 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 125 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 126 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 127 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 128 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 129 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 130 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 131 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 132 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 133 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 134 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 135 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 136 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 137 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 138 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 139 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 140 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 141 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 142 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 143 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 144 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 145 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 146 } 147 148 llvm_unreachable("unknown GPU"); 149 } 150 151 //===----------------------------------------------------------------------===// 152 // AMDGPUTargetAsmStreamer 153 //===----------------------------------------------------------------------===// 154 155 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 156 formatted_raw_ostream &OS) 157 : AMDGPUTargetStreamer(S), OS(OS) { } 158 159 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) { 160 OS << "\t.amdgcn_target \"" << Target << "\"\n"; 161 } 162 163 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 164 uint32_t Major, uint32_t Minor) { 165 OS << "\t.hsa_code_object_version " << 166 Twine(Major) << "," << Twine(Minor) << '\n'; 167 } 168 169 void 170 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 171 uint32_t Minor, 172 uint32_t Stepping, 173 StringRef VendorName, 174 StringRef ArchName) { 175 OS << "\t.hsa_code_object_isa " << 176 Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) << 177 ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 178 179 } 180 181 void 182 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 183 OS << "\t.amd_kernel_code_t\n"; 184 dumpAmdKernelCode(&Header, OS, "\t\t"); 185 OS << "\t.end_amd_kernel_code_t\n"; 186 } 187 188 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 189 unsigned Type) { 190 switch (Type) { 191 default: llvm_unreachable("Invalid AMDGPU symbol type"); 192 case ELF::STT_AMDGPU_HSA_KERNEL: 193 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 194 break; 195 } 196 } 197 198 bool AMDGPUTargetAsmStreamer::EmitISAVersion(StringRef IsaVersionString) { 199 OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n"; 200 return true; 201 } 202 203 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 204 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 205 std::string HSAMetadataString; 206 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 207 return false; 208 209 OS << '\t' << AssemblerDirectiveBegin << '\n'; 210 OS << HSAMetadataString << '\n'; 211 OS << '\t' << AssemblerDirectiveEnd << '\n'; 212 return true; 213 } 214 215 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 216 std::shared_ptr<msgpack::Node> &HSAMetadataRoot, bool Strict) { 217 V3::MetadataVerifier Verifier(Strict); 218 if (!Verifier.verify(*HSAMetadataRoot)) 219 return false; 220 221 std::string HSAMetadataString; 222 raw_string_ostream StrOS(HSAMetadataString); 223 yaml::Output YOut(StrOS); 224 YOut << HSAMetadataRoot; 225 226 OS << '\t' << V3::AssemblerDirectiveBegin << '\n'; 227 OS << StrOS.str() << '\n'; 228 OS << '\t' << V3::AssemblerDirectiveEnd << '\n'; 229 return true; 230 } 231 232 bool AMDGPUTargetAsmStreamer::EmitPALMetadata( 233 const PALMD::Metadata &PALMetadata) { 234 std::string PALMetadataString; 235 if (PALMD::toString(PALMetadata, PALMetadataString)) 236 return false; 237 238 OS << '\t' << PALMD::AssemblerDirective << PALMetadataString << '\n'; 239 return true; 240 } 241 242 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 243 const MCSubtargetInfo &STI, StringRef KernelName, 244 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 245 bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) { 246 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 247 248 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 249 250 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 251 STREAM << "\t\t" << DIRECTIVE << " " \ 252 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 253 254 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 255 << '\n'; 256 OS << "\t\t.amdhsa_private_segment_fixed_size " 257 << KD.private_segment_fixed_size << '\n'; 258 259 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 260 kernel_code_properties, 261 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 262 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 263 kernel_code_properties, 264 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 265 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 266 kernel_code_properties, 267 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 268 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 269 kernel_code_properties, 270 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 271 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 272 kernel_code_properties, 273 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 274 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 275 kernel_code_properties, 276 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 277 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 278 kernel_code_properties, 279 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 280 PRINT_FIELD( 281 OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, 282 compute_pgm_rsrc2, 283 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET); 284 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 285 compute_pgm_rsrc2, 286 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 287 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 288 compute_pgm_rsrc2, 289 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 290 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 291 compute_pgm_rsrc2, 292 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 293 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 294 compute_pgm_rsrc2, 295 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 296 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 297 compute_pgm_rsrc2, 298 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 299 300 // These directives are required. 301 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 302 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 303 304 if (!ReserveVCC) 305 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 306 if (IVersion.Major >= 7 && !ReserveFlatScr) 307 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 308 if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI)) 309 OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n'; 310 311 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 312 compute_pgm_rsrc1, 313 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 314 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 315 compute_pgm_rsrc1, 316 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 317 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 318 compute_pgm_rsrc1, 319 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 320 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 321 compute_pgm_rsrc1, 322 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 323 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 324 compute_pgm_rsrc1, 325 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 326 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 327 compute_pgm_rsrc1, 328 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 329 if (IVersion.Major >= 9) 330 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 331 compute_pgm_rsrc1, 332 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 333 PRINT_FIELD( 334 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 335 compute_pgm_rsrc2, 336 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 337 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 338 compute_pgm_rsrc2, 339 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 340 PRINT_FIELD( 341 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 342 compute_pgm_rsrc2, 343 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 344 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 345 compute_pgm_rsrc2, 346 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 347 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 348 compute_pgm_rsrc2, 349 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 350 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 351 compute_pgm_rsrc2, 352 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 353 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 354 compute_pgm_rsrc2, 355 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 356 #undef PRINT_FIELD 357 358 OS << "\t.end_amdhsa_kernel\n"; 359 } 360 361 //===----------------------------------------------------------------------===// 362 // AMDGPUTargetELFStreamer 363 //===----------------------------------------------------------------------===// 364 365 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer( 366 MCStreamer &S, const MCSubtargetInfo &STI) 367 : AMDGPUTargetStreamer(S), Streamer(S) { 368 MCAssembler &MCA = getStreamer().getAssembler(); 369 unsigned EFlags = MCA.getELFHeaderEFlags(); 370 371 EFlags &= ~ELF::EF_AMDGPU_MACH; 372 EFlags |= getElfMach(STI.getCPU()); 373 374 EFlags &= ~ELF::EF_AMDGPU_XNACK; 375 if (AMDGPU::hasXNACK(STI)) 376 EFlags |= ELF::EF_AMDGPU_XNACK; 377 378 EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC; 379 if (AMDGPU::hasSRAMECC(STI)) 380 EFlags |= ELF::EF_AMDGPU_SRAM_ECC; 381 382 MCA.setELFHeaderEFlags(EFlags); 383 } 384 385 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 386 return static_cast<MCELFStreamer &>(Streamer); 387 } 388 389 void AMDGPUTargetELFStreamer::EmitNote( 390 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 391 function_ref<void(MCELFStreamer &)> EmitDesc) { 392 auto &S = getStreamer(); 393 auto &Context = S.getContext(); 394 395 auto NameSZ = Name.size() + 1; 396 397 S.PushSection(); 398 S.SwitchSection(Context.getELFSection( 399 ElfNote::SectionName, ELF::SHT_NOTE, ELF::SHF_ALLOC)); 400 S.EmitIntValue(NameSZ, 4); // namesz 401 S.EmitValue(DescSZ, 4); // descz 402 S.EmitIntValue(NoteType, 4); // type 403 S.EmitBytes(Name); // name 404 S.EmitValueToAlignment(4, 0, 1, 0); // padding 0 405 EmitDesc(S); // desc 406 S.EmitValueToAlignment(4, 0, 1, 0); // padding 0 407 S.PopSection(); 408 } 409 410 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {} 411 412 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 413 uint32_t Major, uint32_t Minor) { 414 415 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 416 ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 417 OS.EmitIntValue(Major, 4); 418 OS.EmitIntValue(Minor, 4); 419 }); 420 } 421 422 void 423 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 424 uint32_t Minor, 425 uint32_t Stepping, 426 StringRef VendorName, 427 StringRef ArchName) { 428 uint16_t VendorNameSize = VendorName.size() + 1; 429 uint16_t ArchNameSize = ArchName.size() + 1; 430 431 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 432 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 433 VendorNameSize + ArchNameSize; 434 435 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 436 ElfNote::NT_AMDGPU_HSA_ISA, [&](MCELFStreamer &OS) { 437 OS.EmitIntValue(VendorNameSize, 2); 438 OS.EmitIntValue(ArchNameSize, 2); 439 OS.EmitIntValue(Major, 4); 440 OS.EmitIntValue(Minor, 4); 441 OS.EmitIntValue(Stepping, 4); 442 OS.EmitBytes(VendorName); 443 OS.EmitIntValue(0, 1); // NULL terminate VendorName 444 OS.EmitBytes(ArchName); 445 OS.EmitIntValue(0, 1); // NULL terminte ArchName 446 }); 447 } 448 449 void 450 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 451 452 MCStreamer &OS = getStreamer(); 453 OS.PushSection(); 454 OS.EmitBytes(StringRef((const char*)&Header, sizeof(Header))); 455 OS.PopSection(); 456 } 457 458 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 459 unsigned Type) { 460 MCSymbolELF *Symbol = cast<MCSymbolELF>( 461 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 462 Symbol->setType(Type); 463 } 464 465 bool AMDGPUTargetELFStreamer::EmitISAVersion(StringRef IsaVersionString) { 466 // Create two labels to mark the beginning and end of the desc field 467 // and a MCExpr to calculate the size of the desc field. 468 auto &Context = getContext(); 469 auto *DescBegin = Context.createTempSymbol(); 470 auto *DescEnd = Context.createTempSymbol(); 471 auto *DescSZ = MCBinaryExpr::createSub( 472 MCSymbolRefExpr::create(DescEnd, Context), 473 MCSymbolRefExpr::create(DescBegin, Context), Context); 474 475 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_ISA, 476 [&](MCELFStreamer &OS) { 477 OS.EmitLabel(DescBegin); 478 OS.EmitBytes(IsaVersionString); 479 OS.EmitLabel(DescEnd); 480 }); 481 return true; 482 } 483 484 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 485 std::shared_ptr<msgpack::Node> &HSAMetadataRoot, bool Strict) { 486 V3::MetadataVerifier Verifier(Strict); 487 if (!Verifier.verify(*HSAMetadataRoot)) 488 return false; 489 490 std::string HSAMetadataString; 491 raw_string_ostream StrOS(HSAMetadataString); 492 msgpack::Writer MPWriter(StrOS); 493 HSAMetadataRoot->write(MPWriter); 494 495 // Create two labels to mark the beginning and end of the desc field 496 // and a MCExpr to calculate the size of the desc field. 497 auto &Context = getContext(); 498 auto *DescBegin = Context.createTempSymbol(); 499 auto *DescEnd = Context.createTempSymbol(); 500 auto *DescSZ = MCBinaryExpr::createSub( 501 MCSymbolRefExpr::create(DescEnd, Context), 502 MCSymbolRefExpr::create(DescBegin, Context), Context); 503 504 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 505 [&](MCELFStreamer &OS) { 506 OS.EmitLabel(DescBegin); 507 OS.EmitBytes(StrOS.str()); 508 OS.EmitLabel(DescEnd); 509 }); 510 return true; 511 } 512 513 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 514 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 515 std::string HSAMetadataString; 516 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 517 return false; 518 519 // Create two labels to mark the beginning and end of the desc field 520 // and a MCExpr to calculate the size of the desc field. 521 auto &Context = getContext(); 522 auto *DescBegin = Context.createTempSymbol(); 523 auto *DescEnd = Context.createTempSymbol(); 524 auto *DescSZ = MCBinaryExpr::createSub( 525 MCSymbolRefExpr::create(DescEnd, Context), 526 MCSymbolRefExpr::create(DescBegin, Context), Context); 527 528 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_HSA_METADATA, 529 [&](MCELFStreamer &OS) { 530 OS.EmitLabel(DescBegin); 531 OS.EmitBytes(HSAMetadataString); 532 OS.EmitLabel(DescEnd); 533 }); 534 return true; 535 } 536 537 bool AMDGPUTargetELFStreamer::EmitPALMetadata( 538 const PALMD::Metadata &PALMetadata) { 539 EmitNote(ElfNote::NoteNameV2, 540 MCConstantExpr::create(PALMetadata.size() * sizeof(uint32_t), 541 getContext()), 542 ELF::NT_AMD_AMDGPU_PAL_METADATA, [&](MCELFStreamer &OS) { 543 for (auto I : PALMetadata) 544 OS.EmitIntValue(I, sizeof(uint32_t)); 545 }); 546 return true; 547 } 548 549 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 550 const MCSubtargetInfo &STI, StringRef KernelName, 551 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 552 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, 553 bool ReserveXNACK) { 554 auto &Streamer = getStreamer(); 555 auto &Context = Streamer.getContext(); 556 557 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 558 Context.getOrCreateSymbol(Twine(KernelName))); 559 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 560 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 561 562 // Copy kernel descriptor symbol's binding, other and visibility from the 563 // kernel code symbol. 564 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 565 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 566 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 567 // Kernel descriptor symbol's type and size are fixed. 568 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 569 KernelDescriptorSymbol->setSize( 570 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 571 572 // The visibility of the kernel code symbol must be protected or less to allow 573 // static relocations from the kernel descriptor to be used. 574 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 575 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 576 577 Streamer.EmitLabel(KernelDescriptorSymbol); 578 Streamer.EmitBytes(StringRef( 579 (const char*)&(KernelDescriptor), 580 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset))); 581 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 582 // expression being created is: 583 // (start of kernel code) - (start of kernel descriptor) 584 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 585 Streamer.EmitValue(MCBinaryExpr::createSub( 586 MCSymbolRefExpr::create( 587 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 588 MCSymbolRefExpr::create( 589 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 590 Context), 591 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 592 Streamer.EmitBytes(StringRef( 593 (const char*)&(KernelDescriptor) + 594 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) + 595 sizeof(KernelDescriptor.kernel_code_entry_byte_offset), 596 sizeof(KernelDescriptor) - 597 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) - 598 sizeof(KernelDescriptor.kernel_code_entry_byte_offset))); 599 } 600