1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPU.h" 15 #include "SIDefines.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/ADT/Twine.h" 19 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/IR/Constants.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/IR/Metadata.h" 24 #include "llvm/IR/Module.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCELFStreamer.h" 27 #include "llvm/MC/MCObjectFileInfo.h" 28 #include "llvm/MC/MCSectionELF.h" 29 #include "llvm/Support/FormattedStream.h" 30 #include "llvm/Support/TargetParser.h" 31 32 namespace llvm { 33 #include "AMDGPUPTNote.h" 34 } 35 36 using namespace llvm; 37 using namespace llvm::AMDGPU; 38 using namespace llvm::AMDGPU::HSAMD; 39 40 //===----------------------------------------------------------------------===// 41 // AMDGPUTargetStreamer 42 //===----------------------------------------------------------------------===// 43 44 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 45 HSAMD::Metadata HSAMetadata; 46 if (HSAMD::fromString(std::string(HSAMetadataString), HSAMetadata)) 47 return false; 48 49 return EmitHSAMetadata(HSAMetadata); 50 } 51 52 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 53 msgpack::Document HSAMetadataDoc; 54 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 55 return false; 56 return EmitHSAMetadata(HSAMetadataDoc, false); 57 } 58 59 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 60 AMDGPU::GPUKind AK; 61 62 switch (ElfMach) { 63 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type"); 64 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 65 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 66 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 67 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 68 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 69 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 70 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 71 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 72 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 73 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 74 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 75 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 76 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 77 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 78 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 79 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 80 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 81 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 82 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 102 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 103 } 104 105 StringRef GPUName = getArchNameAMDGCN(AK); 106 if (GPUName != "") 107 return GPUName; 108 return getArchNameR600(AK); 109 } 110 111 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 112 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 113 if (AK == AMDGPU::GPUKind::GK_NONE) 114 AK = parseArchR600(GPU); 115 116 switch (AK) { 117 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 118 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 119 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 120 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 121 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 122 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 123 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 124 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 125 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 126 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 127 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 128 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 129 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 130 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 131 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 132 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 133 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 134 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 135 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 136 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 137 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 138 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 139 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 140 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 141 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 142 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 143 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 144 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 145 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 146 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 147 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 148 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 149 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 150 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 151 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 152 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 153 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 154 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 155 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 156 } 157 158 llvm_unreachable("unknown GPU"); 159 } 160 161 //===----------------------------------------------------------------------===// 162 // AMDGPUTargetAsmStreamer 163 //===----------------------------------------------------------------------===// 164 165 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 166 formatted_raw_ostream &OS) 167 : AMDGPUTargetStreamer(S), OS(OS) { } 168 169 // A hook for emitting stuff at the end. 170 // We use it for emitting the accumulated PAL metadata as directives. 171 void AMDGPUTargetAsmStreamer::finish() { 172 std::string S; 173 getPALMetadata()->toString(S); 174 OS << S; 175 } 176 177 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) { 178 OS << "\t.amdgcn_target \"" << Target << "\"\n"; 179 } 180 181 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 182 uint32_t Major, uint32_t Minor) { 183 OS << "\t.hsa_code_object_version " << 184 Twine(Major) << "," << Twine(Minor) << '\n'; 185 } 186 187 void 188 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 189 uint32_t Minor, 190 uint32_t Stepping, 191 StringRef VendorName, 192 StringRef ArchName) { 193 OS << "\t.hsa_code_object_isa " << 194 Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) << 195 ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 196 197 } 198 199 void 200 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 201 OS << "\t.amd_kernel_code_t\n"; 202 dumpAmdKernelCode(&Header, OS, "\t\t"); 203 OS << "\t.end_amd_kernel_code_t\n"; 204 } 205 206 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 207 unsigned Type) { 208 switch (Type) { 209 default: llvm_unreachable("Invalid AMDGPU symbol type"); 210 case ELF::STT_AMDGPU_HSA_KERNEL: 211 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 212 break; 213 } 214 } 215 216 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 217 Align Alignment) { 218 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 219 << Alignment.value() << '\n'; 220 } 221 222 bool AMDGPUTargetAsmStreamer::EmitISAVersion(StringRef IsaVersionString) { 223 OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n"; 224 return true; 225 } 226 227 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 228 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 229 std::string HSAMetadataString; 230 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 231 return false; 232 233 OS << '\t' << AssemblerDirectiveBegin << '\n'; 234 OS << HSAMetadataString << '\n'; 235 OS << '\t' << AssemblerDirectiveEnd << '\n'; 236 return true; 237 } 238 239 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 240 msgpack::Document &HSAMetadataDoc, bool Strict) { 241 V3::MetadataVerifier Verifier(Strict); 242 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 243 return false; 244 245 std::string HSAMetadataString; 246 raw_string_ostream StrOS(HSAMetadataString); 247 HSAMetadataDoc.toYAML(StrOS); 248 249 OS << '\t' << V3::AssemblerDirectiveBegin << '\n'; 250 OS << StrOS.str() << '\n'; 251 OS << '\t' << V3::AssemblerDirectiveEnd << '\n'; 252 return true; 253 } 254 255 bool AMDGPUTargetAsmStreamer::EmitCodeEnd() { 256 const uint32_t Encoded_s_code_end = 0xbf9f0000; 257 OS << "\t.p2alignl 6, " << Encoded_s_code_end << '\n'; 258 OS << "\t.fill 48, 4, " << Encoded_s_code_end << '\n'; 259 return true; 260 } 261 262 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 263 const MCSubtargetInfo &STI, StringRef KernelName, 264 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 265 bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) { 266 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 267 268 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 269 270 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 271 STREAM << "\t\t" << DIRECTIVE << " " \ 272 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 273 274 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 275 << '\n'; 276 OS << "\t\t.amdhsa_private_segment_fixed_size " 277 << KD.private_segment_fixed_size << '\n'; 278 279 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 280 kernel_code_properties, 281 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 282 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 283 kernel_code_properties, 284 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 285 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 286 kernel_code_properties, 287 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 288 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 289 kernel_code_properties, 290 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 291 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 292 kernel_code_properties, 293 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 294 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 295 kernel_code_properties, 296 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 297 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 298 kernel_code_properties, 299 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 300 if (IVersion.Major >= 10) 301 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 302 kernel_code_properties, 303 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 304 PRINT_FIELD( 305 OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, 306 compute_pgm_rsrc2, 307 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET); 308 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 309 compute_pgm_rsrc2, 310 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 311 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 312 compute_pgm_rsrc2, 313 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 314 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 315 compute_pgm_rsrc2, 316 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 317 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 318 compute_pgm_rsrc2, 319 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 320 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 321 compute_pgm_rsrc2, 322 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 323 324 // These directives are required. 325 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 326 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 327 328 if (!ReserveVCC) 329 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 330 if (IVersion.Major >= 7 && !ReserveFlatScr) 331 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 332 if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI)) 333 OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n'; 334 335 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 336 compute_pgm_rsrc1, 337 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 338 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 339 compute_pgm_rsrc1, 340 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 341 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 342 compute_pgm_rsrc1, 343 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 344 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 345 compute_pgm_rsrc1, 346 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 347 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 348 compute_pgm_rsrc1, 349 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 350 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 351 compute_pgm_rsrc1, 352 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 353 if (IVersion.Major >= 9) 354 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 355 compute_pgm_rsrc1, 356 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 357 if (IVersion.Major >= 10) { 358 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 359 compute_pgm_rsrc1, 360 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 361 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 362 compute_pgm_rsrc1, 363 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 364 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 365 compute_pgm_rsrc1, 366 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 367 } 368 PRINT_FIELD( 369 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 370 compute_pgm_rsrc2, 371 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 372 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 373 compute_pgm_rsrc2, 374 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 375 PRINT_FIELD( 376 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 377 compute_pgm_rsrc2, 378 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 379 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 380 compute_pgm_rsrc2, 381 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 382 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 383 compute_pgm_rsrc2, 384 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 385 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 386 compute_pgm_rsrc2, 387 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 388 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 389 compute_pgm_rsrc2, 390 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 391 #undef PRINT_FIELD 392 393 OS << "\t.end_amdhsa_kernel\n"; 394 } 395 396 //===----------------------------------------------------------------------===// 397 // AMDGPUTargetELFStreamer 398 //===----------------------------------------------------------------------===// 399 400 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 401 const MCSubtargetInfo &STI) 402 : AMDGPUTargetStreamer(S), Streamer(S), Os(STI.getTargetTriple().getOS()) { 403 MCAssembler &MCA = getStreamer().getAssembler(); 404 unsigned EFlags = MCA.getELFHeaderEFlags(); 405 406 EFlags &= ~ELF::EF_AMDGPU_MACH; 407 EFlags |= getElfMach(STI.getCPU()); 408 409 EFlags &= ~ELF::EF_AMDGPU_XNACK; 410 if (AMDGPU::hasXNACK(STI)) 411 EFlags |= ELF::EF_AMDGPU_XNACK; 412 413 EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC; 414 if (AMDGPU::hasSRAMECC(STI)) 415 EFlags |= ELF::EF_AMDGPU_SRAM_ECC; 416 417 MCA.setELFHeaderEFlags(EFlags); 418 } 419 420 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 421 return static_cast<MCELFStreamer &>(Streamer); 422 } 423 424 // A hook for emitting stuff at the end. 425 // We use it for emitting the accumulated PAL metadata as a .note record. 426 void AMDGPUTargetELFStreamer::finish() { 427 std::string Blob; 428 const char *Vendor = getPALMetadata()->getVendor(); 429 unsigned Type = getPALMetadata()->getType(); 430 getPALMetadata()->toBlob(Type, Blob); 431 if (Blob.empty()) 432 return; 433 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 434 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 435 } 436 437 void AMDGPUTargetELFStreamer::EmitNote( 438 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 439 function_ref<void(MCELFStreamer &)> EmitDesc) { 440 auto &S = getStreamer(); 441 auto &Context = S.getContext(); 442 443 auto NameSZ = Name.size() + 1; 444 445 unsigned NoteFlags = 0; 446 // TODO Apparently, this is currently needed for OpenCL as mentioned in 447 // https://reviews.llvm.org/D74995 448 if (Os == Triple::AMDHSA) 449 NoteFlags = ELF::SHF_ALLOC; 450 451 S.PushSection(); 452 S.SwitchSection( 453 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 454 S.emitInt32(NameSZ); // namesz 455 S.emitValue(DescSZ, 4); // descz 456 S.emitInt32(NoteType); // type 457 S.emitBytes(Name); // name 458 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 459 EmitDesc(S); // desc 460 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 461 S.PopSection(); 462 } 463 464 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {} 465 466 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 467 uint32_t Major, uint32_t Minor) { 468 469 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 470 ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 471 OS.emitInt32(Major); 472 OS.emitInt32(Minor); 473 }); 474 } 475 476 void 477 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 478 uint32_t Minor, 479 uint32_t Stepping, 480 StringRef VendorName, 481 StringRef ArchName) { 482 uint16_t VendorNameSize = VendorName.size() + 1; 483 uint16_t ArchNameSize = ArchName.size() + 1; 484 485 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 486 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 487 VendorNameSize + ArchNameSize; 488 489 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 490 ElfNote::NT_AMDGPU_HSA_ISA, [&](MCELFStreamer &OS) { 491 OS.emitInt16(VendorNameSize); 492 OS.emitInt16(ArchNameSize); 493 OS.emitInt32(Major); 494 OS.emitInt32(Minor); 495 OS.emitInt32(Stepping); 496 OS.emitBytes(VendorName); 497 OS.emitInt8(0); // NULL terminate VendorName 498 OS.emitBytes(ArchName); 499 OS.emitInt8(0); // NULL terminte ArchName 500 }); 501 } 502 503 void 504 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 505 506 MCStreamer &OS = getStreamer(); 507 OS.PushSection(); 508 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 509 OS.PopSection(); 510 } 511 512 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 513 unsigned Type) { 514 MCSymbolELF *Symbol = cast<MCSymbolELF>( 515 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 516 Symbol->setType(Type); 517 } 518 519 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 520 Align Alignment) { 521 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 522 SymbolELF->setType(ELF::STT_OBJECT); 523 524 if (!SymbolELF->isBindingSet()) { 525 SymbolELF->setBinding(ELF::STB_GLOBAL); 526 SymbolELF->setExternal(true); 527 } 528 529 if (SymbolELF->declareCommon(Size, Alignment.value(), true)) { 530 report_fatal_error("Symbol: " + Symbol->getName() + 531 " redeclared as different type"); 532 } 533 534 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 535 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 536 } 537 538 bool AMDGPUTargetELFStreamer::EmitISAVersion(StringRef IsaVersionString) { 539 // Create two labels to mark the beginning and end of the desc field 540 // and a MCExpr to calculate the size of the desc field. 541 auto &Context = getContext(); 542 auto *DescBegin = Context.createTempSymbol(); 543 auto *DescEnd = Context.createTempSymbol(); 544 auto *DescSZ = MCBinaryExpr::createSub( 545 MCSymbolRefExpr::create(DescEnd, Context), 546 MCSymbolRefExpr::create(DescBegin, Context), Context); 547 548 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_ISA, 549 [&](MCELFStreamer &OS) { 550 OS.emitLabel(DescBegin); 551 OS.emitBytes(IsaVersionString); 552 OS.emitLabel(DescEnd); 553 }); 554 return true; 555 } 556 557 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 558 bool Strict) { 559 V3::MetadataVerifier Verifier(Strict); 560 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 561 return false; 562 563 std::string HSAMetadataString; 564 HSAMetadataDoc.writeToBlob(HSAMetadataString); 565 566 // Create two labels to mark the beginning and end of the desc field 567 // and a MCExpr to calculate the size of the desc field. 568 auto &Context = getContext(); 569 auto *DescBegin = Context.createTempSymbol(); 570 auto *DescEnd = Context.createTempSymbol(); 571 auto *DescSZ = MCBinaryExpr::createSub( 572 MCSymbolRefExpr::create(DescEnd, Context), 573 MCSymbolRefExpr::create(DescBegin, Context), Context); 574 575 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 576 [&](MCELFStreamer &OS) { 577 OS.emitLabel(DescBegin); 578 OS.emitBytes(HSAMetadataString); 579 OS.emitLabel(DescEnd); 580 }); 581 return true; 582 } 583 584 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 585 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 586 std::string HSAMetadataString; 587 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 588 return false; 589 590 // Create two labels to mark the beginning and end of the desc field 591 // and a MCExpr to calculate the size of the desc field. 592 auto &Context = getContext(); 593 auto *DescBegin = Context.createTempSymbol(); 594 auto *DescEnd = Context.createTempSymbol(); 595 auto *DescSZ = MCBinaryExpr::createSub( 596 MCSymbolRefExpr::create(DescEnd, Context), 597 MCSymbolRefExpr::create(DescBegin, Context), Context); 598 599 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_HSA_METADATA, 600 [&](MCELFStreamer &OS) { 601 OS.emitLabel(DescBegin); 602 OS.emitBytes(HSAMetadataString); 603 OS.emitLabel(DescEnd); 604 }); 605 return true; 606 } 607 608 bool AMDGPUTargetELFStreamer::EmitCodeEnd() { 609 const uint32_t Encoded_s_code_end = 0xbf9f0000; 610 611 MCStreamer &OS = getStreamer(); 612 OS.PushSection(); 613 OS.emitValueToAlignment(64, Encoded_s_code_end, 4); 614 for (unsigned I = 0; I < 48; ++I) 615 OS.emitInt32(Encoded_s_code_end); 616 OS.PopSection(); 617 return true; 618 } 619 620 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 621 const MCSubtargetInfo &STI, StringRef KernelName, 622 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 623 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, 624 bool ReserveXNACK) { 625 auto &Streamer = getStreamer(); 626 auto &Context = Streamer.getContext(); 627 628 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 629 Context.getOrCreateSymbol(Twine(KernelName))); 630 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 631 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 632 633 // Copy kernel descriptor symbol's binding, other and visibility from the 634 // kernel code symbol. 635 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 636 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 637 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 638 // Kernel descriptor symbol's type and size are fixed. 639 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 640 KernelDescriptorSymbol->setSize( 641 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 642 643 // The visibility of the kernel code symbol must be protected or less to allow 644 // static relocations from the kernel descriptor to be used. 645 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 646 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 647 648 Streamer.emitLabel(KernelDescriptorSymbol); 649 Streamer.emitBytes(StringRef( 650 (const char*)&(KernelDescriptor), 651 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset))); 652 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 653 // expression being created is: 654 // (start of kernel code) - (start of kernel descriptor) 655 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 656 Streamer.emitValue(MCBinaryExpr::createSub( 657 MCSymbolRefExpr::create( 658 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 659 MCSymbolRefExpr::create( 660 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 661 Context), 662 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 663 Streamer.emitBytes(StringRef( 664 (const char*)&(KernelDescriptor) + 665 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) + 666 sizeof(KernelDescriptor.kernel_code_entry_byte_offset), 667 sizeof(KernelDescriptor) - 668 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) - 669 sizeof(KernelDescriptor.kernel_code_entry_byte_offset))); 670 } 671