1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPU.h" 15 #include "SIDefines.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/ADT/Twine.h" 19 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/IR/Constants.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/IR/Metadata.h" 24 #include "llvm/IR/Module.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCELFStreamer.h" 27 #include "llvm/MC/MCObjectFileInfo.h" 28 #include "llvm/MC/MCSectionELF.h" 29 #include "llvm/Support/FormattedStream.h" 30 #include "llvm/Support/TargetParser.h" 31 32 namespace llvm { 33 #include "AMDGPUPTNote.h" 34 } 35 36 using namespace llvm; 37 using namespace llvm::AMDGPU; 38 using namespace llvm::AMDGPU::HSAMD; 39 40 //===----------------------------------------------------------------------===// 41 // AMDGPUTargetStreamer 42 //===----------------------------------------------------------------------===// 43 44 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 45 HSAMD::Metadata HSAMetadata; 46 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 47 return false; 48 49 return EmitHSAMetadata(HSAMetadata); 50 } 51 52 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 53 msgpack::Document HSAMetadataDoc; 54 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 55 return false; 56 return EmitHSAMetadata(HSAMetadataDoc, false); 57 } 58 59 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 60 AMDGPU::GPUKind AK; 61 62 switch (ElfMach) { 63 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 64 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 65 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 66 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 67 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 68 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 69 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 70 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 71 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 72 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 73 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 74 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 75 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 76 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 77 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 78 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 79 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 80 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 81 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 82 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 96 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 97 } 98 99 StringRef GPUName = getArchNameAMDGCN(AK); 100 if (GPUName != "") 101 return GPUName; 102 return getArchNameR600(AK); 103 } 104 105 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 106 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 107 if (AK == AMDGPU::GPUKind::GK_NONE) 108 AK = parseArchR600(GPU); 109 110 switch (AK) { 111 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 112 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 113 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 114 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 115 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 116 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 117 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 118 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 119 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 120 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 121 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 122 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 123 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 124 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 125 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 126 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 127 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 128 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 129 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 130 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 131 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 132 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 133 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 134 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 135 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 136 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 137 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 138 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 139 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 140 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 141 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 142 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 143 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 144 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 145 } 146 147 llvm_unreachable("unknown GPU"); 148 } 149 150 //===----------------------------------------------------------------------===// 151 // AMDGPUTargetAsmStreamer 152 //===----------------------------------------------------------------------===// 153 154 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 155 formatted_raw_ostream &OS) 156 : AMDGPUTargetStreamer(S), OS(OS) { } 157 158 // A hook for emitting stuff at the end. 159 // We use it for emitting the accumulated PAL metadata as directives. 160 void AMDGPUTargetAsmStreamer::finish() { 161 std::string S; 162 getPALMetadata()->toString(S); 163 OS << S; 164 } 165 166 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) { 167 OS << "\t.amdgcn_target \"" << Target << "\"\n"; 168 } 169 170 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 171 uint32_t Major, uint32_t Minor) { 172 OS << "\t.hsa_code_object_version " << 173 Twine(Major) << "," << Twine(Minor) << '\n'; 174 } 175 176 void 177 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 178 uint32_t Minor, 179 uint32_t Stepping, 180 StringRef VendorName, 181 StringRef ArchName) { 182 OS << "\t.hsa_code_object_isa " << 183 Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) << 184 ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 185 186 } 187 188 void 189 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 190 OS << "\t.amd_kernel_code_t\n"; 191 dumpAmdKernelCode(&Header, OS, "\t\t"); 192 OS << "\t.end_amd_kernel_code_t\n"; 193 } 194 195 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 196 unsigned Type) { 197 switch (Type) { 198 default: llvm_unreachable("Invalid AMDGPU symbol type"); 199 case ELF::STT_AMDGPU_HSA_KERNEL: 200 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 201 break; 202 } 203 } 204 205 bool AMDGPUTargetAsmStreamer::EmitISAVersion(StringRef IsaVersionString) { 206 OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n"; 207 return true; 208 } 209 210 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 211 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 212 std::string HSAMetadataString; 213 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 214 return false; 215 216 OS << '\t' << AssemblerDirectiveBegin << '\n'; 217 OS << HSAMetadataString << '\n'; 218 OS << '\t' << AssemblerDirectiveEnd << '\n'; 219 return true; 220 } 221 222 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 223 msgpack::Document &HSAMetadataDoc, bool Strict) { 224 V3::MetadataVerifier Verifier(Strict); 225 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 226 return false; 227 228 std::string HSAMetadataString; 229 raw_string_ostream StrOS(HSAMetadataString); 230 HSAMetadataDoc.toYAML(StrOS); 231 232 OS << '\t' << V3::AssemblerDirectiveBegin << '\n'; 233 OS << StrOS.str() << '\n'; 234 OS << '\t' << V3::AssemblerDirectiveEnd << '\n'; 235 return true; 236 } 237 238 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 239 const MCSubtargetInfo &STI, StringRef KernelName, 240 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 241 bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) { 242 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 243 244 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 245 246 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 247 STREAM << "\t\t" << DIRECTIVE << " " \ 248 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 249 250 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 251 << '\n'; 252 OS << "\t\t.amdhsa_private_segment_fixed_size " 253 << KD.private_segment_fixed_size << '\n'; 254 255 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 256 kernel_code_properties, 257 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 258 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 259 kernel_code_properties, 260 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 261 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 262 kernel_code_properties, 263 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 264 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 265 kernel_code_properties, 266 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 267 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 268 kernel_code_properties, 269 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 270 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 271 kernel_code_properties, 272 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 273 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 274 kernel_code_properties, 275 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 276 PRINT_FIELD( 277 OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, 278 compute_pgm_rsrc2, 279 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET); 280 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 281 compute_pgm_rsrc2, 282 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 283 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 284 compute_pgm_rsrc2, 285 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 286 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 287 compute_pgm_rsrc2, 288 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 289 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 290 compute_pgm_rsrc2, 291 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 292 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 293 compute_pgm_rsrc2, 294 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 295 296 // These directives are required. 297 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 298 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 299 300 if (!ReserveVCC) 301 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 302 if (IVersion.Major >= 7 && !ReserveFlatScr) 303 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 304 if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI)) 305 OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n'; 306 307 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 308 compute_pgm_rsrc1, 309 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 310 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 311 compute_pgm_rsrc1, 312 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 313 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 314 compute_pgm_rsrc1, 315 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 316 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 317 compute_pgm_rsrc1, 318 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 319 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 320 compute_pgm_rsrc1, 321 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 322 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 323 compute_pgm_rsrc1, 324 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 325 if (IVersion.Major >= 9) 326 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 327 compute_pgm_rsrc1, 328 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 329 if (IVersion.Major >= 10) { 330 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 331 compute_pgm_rsrc1, 332 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 333 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 334 compute_pgm_rsrc1, 335 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 336 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 337 compute_pgm_rsrc1, 338 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 339 } 340 PRINT_FIELD( 341 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 342 compute_pgm_rsrc2, 343 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 344 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 345 compute_pgm_rsrc2, 346 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 347 PRINT_FIELD( 348 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 349 compute_pgm_rsrc2, 350 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 351 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 352 compute_pgm_rsrc2, 353 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 354 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 355 compute_pgm_rsrc2, 356 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 357 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 358 compute_pgm_rsrc2, 359 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 360 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 361 compute_pgm_rsrc2, 362 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 363 #undef PRINT_FIELD 364 365 OS << "\t.end_amdhsa_kernel\n"; 366 } 367 368 //===----------------------------------------------------------------------===// 369 // AMDGPUTargetELFStreamer 370 //===----------------------------------------------------------------------===// 371 372 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer( 373 MCStreamer &S, const MCSubtargetInfo &STI) 374 : AMDGPUTargetStreamer(S), Streamer(S) { 375 MCAssembler &MCA = getStreamer().getAssembler(); 376 unsigned EFlags = MCA.getELFHeaderEFlags(); 377 378 EFlags &= ~ELF::EF_AMDGPU_MACH; 379 EFlags |= getElfMach(STI.getCPU()); 380 381 EFlags &= ~ELF::EF_AMDGPU_XNACK; 382 if (AMDGPU::hasXNACK(STI)) 383 EFlags |= ELF::EF_AMDGPU_XNACK; 384 385 EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC; 386 if (AMDGPU::hasSRAMECC(STI)) 387 EFlags |= ELF::EF_AMDGPU_SRAM_ECC; 388 389 MCA.setELFHeaderEFlags(EFlags); 390 } 391 392 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 393 return static_cast<MCELFStreamer &>(Streamer); 394 } 395 396 // A hook for emitting stuff at the end. 397 // We use it for emitting the accumulated PAL metadata as a .note record. 398 void AMDGPUTargetELFStreamer::finish() { 399 std::string Blob; 400 const char *Vendor = getPALMetadata()->getVendor(); 401 unsigned Type = getPALMetadata()->getType(); 402 getPALMetadata()->toBlob(Type, Blob); 403 if (Blob.empty()) 404 return; 405 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 406 [&](MCELFStreamer &OS) { OS.EmitBytes(Blob); }); 407 } 408 409 void AMDGPUTargetELFStreamer::EmitNote( 410 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 411 function_ref<void(MCELFStreamer &)> EmitDesc) { 412 auto &S = getStreamer(); 413 auto &Context = S.getContext(); 414 415 auto NameSZ = Name.size() + 1; 416 417 S.PushSection(); 418 S.SwitchSection(Context.getELFSection( 419 ElfNote::SectionName, ELF::SHT_NOTE, ELF::SHF_ALLOC)); 420 S.EmitIntValue(NameSZ, 4); // namesz 421 S.EmitValue(DescSZ, 4); // descz 422 S.EmitIntValue(NoteType, 4); // type 423 S.EmitBytes(Name); // name 424 S.EmitValueToAlignment(4, 0, 1, 0); // padding 0 425 EmitDesc(S); // desc 426 S.EmitValueToAlignment(4, 0, 1, 0); // padding 0 427 S.PopSection(); 428 } 429 430 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {} 431 432 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 433 uint32_t Major, uint32_t Minor) { 434 435 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 436 ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 437 OS.EmitIntValue(Major, 4); 438 OS.EmitIntValue(Minor, 4); 439 }); 440 } 441 442 void 443 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 444 uint32_t Minor, 445 uint32_t Stepping, 446 StringRef VendorName, 447 StringRef ArchName) { 448 uint16_t VendorNameSize = VendorName.size() + 1; 449 uint16_t ArchNameSize = ArchName.size() + 1; 450 451 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 452 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 453 VendorNameSize + ArchNameSize; 454 455 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 456 ElfNote::NT_AMDGPU_HSA_ISA, [&](MCELFStreamer &OS) { 457 OS.EmitIntValue(VendorNameSize, 2); 458 OS.EmitIntValue(ArchNameSize, 2); 459 OS.EmitIntValue(Major, 4); 460 OS.EmitIntValue(Minor, 4); 461 OS.EmitIntValue(Stepping, 4); 462 OS.EmitBytes(VendorName); 463 OS.EmitIntValue(0, 1); // NULL terminate VendorName 464 OS.EmitBytes(ArchName); 465 OS.EmitIntValue(0, 1); // NULL terminte ArchName 466 }); 467 } 468 469 void 470 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 471 472 MCStreamer &OS = getStreamer(); 473 OS.PushSection(); 474 OS.EmitBytes(StringRef((const char*)&Header, sizeof(Header))); 475 OS.PopSection(); 476 } 477 478 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 479 unsigned Type) { 480 MCSymbolELF *Symbol = cast<MCSymbolELF>( 481 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 482 Symbol->setType(Type); 483 } 484 485 bool AMDGPUTargetELFStreamer::EmitISAVersion(StringRef IsaVersionString) { 486 // Create two labels to mark the beginning and end of the desc field 487 // and a MCExpr to calculate the size of the desc field. 488 auto &Context = getContext(); 489 auto *DescBegin = Context.createTempSymbol(); 490 auto *DescEnd = Context.createTempSymbol(); 491 auto *DescSZ = MCBinaryExpr::createSub( 492 MCSymbolRefExpr::create(DescEnd, Context), 493 MCSymbolRefExpr::create(DescBegin, Context), Context); 494 495 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_ISA, 496 [&](MCELFStreamer &OS) { 497 OS.EmitLabel(DescBegin); 498 OS.EmitBytes(IsaVersionString); 499 OS.EmitLabel(DescEnd); 500 }); 501 return true; 502 } 503 504 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 505 bool Strict) { 506 V3::MetadataVerifier Verifier(Strict); 507 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 508 return false; 509 510 std::string HSAMetadataString; 511 HSAMetadataDoc.writeToBlob(HSAMetadataString); 512 513 // Create two labels to mark the beginning and end of the desc field 514 // and a MCExpr to calculate the size of the desc field. 515 auto &Context = getContext(); 516 auto *DescBegin = Context.createTempSymbol(); 517 auto *DescEnd = Context.createTempSymbol(); 518 auto *DescSZ = MCBinaryExpr::createSub( 519 MCSymbolRefExpr::create(DescEnd, Context), 520 MCSymbolRefExpr::create(DescBegin, Context), Context); 521 522 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 523 [&](MCELFStreamer &OS) { 524 OS.EmitLabel(DescBegin); 525 OS.EmitBytes(HSAMetadataString); 526 OS.EmitLabel(DescEnd); 527 }); 528 return true; 529 } 530 531 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 532 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 533 std::string HSAMetadataString; 534 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 535 return false; 536 537 // Create two labels to mark the beginning and end of the desc field 538 // and a MCExpr to calculate the size of the desc field. 539 auto &Context = getContext(); 540 auto *DescBegin = Context.createTempSymbol(); 541 auto *DescEnd = Context.createTempSymbol(); 542 auto *DescSZ = MCBinaryExpr::createSub( 543 MCSymbolRefExpr::create(DescEnd, Context), 544 MCSymbolRefExpr::create(DescBegin, Context), Context); 545 546 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_HSA_METADATA, 547 [&](MCELFStreamer &OS) { 548 OS.EmitLabel(DescBegin); 549 OS.EmitBytes(HSAMetadataString); 550 OS.EmitLabel(DescEnd); 551 }); 552 return true; 553 } 554 555 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 556 const MCSubtargetInfo &STI, StringRef KernelName, 557 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 558 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, 559 bool ReserveXNACK) { 560 auto &Streamer = getStreamer(); 561 auto &Context = Streamer.getContext(); 562 563 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 564 Context.getOrCreateSymbol(Twine(KernelName))); 565 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 566 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 567 568 // Copy kernel descriptor symbol's binding, other and visibility from the 569 // kernel code symbol. 570 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 571 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 572 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 573 // Kernel descriptor symbol's type and size are fixed. 574 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 575 KernelDescriptorSymbol->setSize( 576 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 577 578 // The visibility of the kernel code symbol must be protected or less to allow 579 // static relocations from the kernel descriptor to be used. 580 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 581 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 582 583 Streamer.EmitLabel(KernelDescriptorSymbol); 584 Streamer.EmitBytes(StringRef( 585 (const char*)&(KernelDescriptor), 586 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset))); 587 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 588 // expression being created is: 589 // (start of kernel code) - (start of kernel descriptor) 590 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 591 Streamer.EmitValue(MCBinaryExpr::createSub( 592 MCSymbolRefExpr::create( 593 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 594 MCSymbolRefExpr::create( 595 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 596 Context), 597 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 598 Streamer.EmitBytes(StringRef( 599 (const char*)&(KernelDescriptor) + 600 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) + 601 sizeof(KernelDescriptor.kernel_code_entry_byte_offset), 602 sizeof(KernelDescriptor) - 603 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) - 604 sizeof(KernelDescriptor.kernel_code_entry_byte_offset))); 605 } 606