1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPUPTNote.h" 15 #include "AMDKernelCodeT.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/MC/MCAssembler.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCELFStreamer.h" 23 #include "llvm/MC/MCSectionELF.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/AMDGPUMetadata.h" 26 #include "llvm/Support/AMDHSAKernelDescriptor.h" 27 #include "llvm/Support/Casting.h" 28 #include "llvm/Support/FormattedStream.h" 29 #include "llvm/Support/TargetParser.h" 30 31 using namespace llvm; 32 using namespace llvm::AMDGPU; 33 34 //===----------------------------------------------------------------------===// 35 // AMDGPUTargetStreamer 36 //===----------------------------------------------------------------------===// 37 38 static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, 39 uint32_t &Stepping, bool Sramecc, bool Xnack) { 40 if (Major == 9 && Minor == 0) { 41 switch (Stepping) { 42 case 0: 43 case 2: 44 case 4: 45 case 6: 46 if (Xnack) 47 Stepping++; 48 } 49 } 50 } 51 52 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 53 HSAMD::Metadata HSAMetadata; 54 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 55 return false; 56 return EmitHSAMetadata(HSAMetadata); 57 } 58 59 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 60 msgpack::Document HSAMetadataDoc; 61 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 62 return false; 63 return EmitHSAMetadata(HSAMetadataDoc, false); 64 } 65 66 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 67 AMDGPU::GPUKind AK; 68 69 switch (ElfMach) { 70 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type"); 71 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 72 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 73 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 74 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 75 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 76 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 77 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 78 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 79 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 80 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 81 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 82 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 83 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 84 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 85 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 86 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break; 100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break; 108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break; 109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX940: AK = GK_GFX940; break; 110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 113 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break; 114 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 115 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 116 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break; 117 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break; 118 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break; 119 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: AK = GK_GFX1035; break; 120 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036: AK = GK_GFX1036; break; 121 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100: AK = GK_GFX1100; break; 122 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101: AK = GK_GFX1101; break; 123 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102: AK = GK_GFX1102; break; 124 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103: AK = GK_GFX1103; break; 125 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 126 } 127 128 StringRef GPUName = getArchNameAMDGCN(AK); 129 if (GPUName != "") 130 return GPUName; 131 return getArchNameR600(AK); 132 } 133 134 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 135 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 136 if (AK == AMDGPU::GPUKind::GK_NONE) 137 AK = parseArchR600(GPU); 138 139 switch (AK) { 140 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 141 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 142 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 143 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 144 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 145 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 146 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 147 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 148 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 149 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 150 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 151 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 152 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 153 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 154 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 155 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 156 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 157 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 158 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602; 159 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 160 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 161 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 162 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 163 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 164 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705; 165 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 166 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 167 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 168 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805; 169 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 170 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 171 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 172 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 173 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 174 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 175 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 176 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A; 177 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C; 178 case GK_GFX940: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX940; 179 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 180 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 181 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 182 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013; 183 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 184 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 185 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032; 186 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033; 187 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034; 188 case GK_GFX1035: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035; 189 case GK_GFX1036: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036; 190 case GK_GFX1100: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100; 191 case GK_GFX1101: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101; 192 case GK_GFX1102: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102; 193 case GK_GFX1103: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103; 194 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 195 } 196 197 llvm_unreachable("unknown GPU"); 198 } 199 200 //===----------------------------------------------------------------------===// 201 // AMDGPUTargetAsmStreamer 202 //===----------------------------------------------------------------------===// 203 204 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 205 formatted_raw_ostream &OS) 206 : AMDGPUTargetStreamer(S), OS(OS) { } 207 208 // A hook for emitting stuff at the end. 209 // We use it for emitting the accumulated PAL metadata as directives. 210 // The PAL metadata is reset after it is emitted. 211 void AMDGPUTargetAsmStreamer::finish() { 212 std::string S; 213 getPALMetadata()->toString(S); 214 OS << S; 215 216 // Reset the pal metadata so its data will not affect a compilation that 217 // reuses this object. 218 getPALMetadata()->reset(); 219 } 220 221 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() { 222 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n"; 223 } 224 225 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 226 uint32_t Major, uint32_t Minor) { 227 OS << "\t.hsa_code_object_version " << 228 Twine(Major) << "," << Twine(Minor) << '\n'; 229 } 230 231 void 232 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 233 uint32_t Minor, 234 uint32_t Stepping, 235 StringRef VendorName, 236 StringRef ArchName) { 237 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 238 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << "," 239 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 240 } 241 242 void 243 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 244 OS << "\t.amd_kernel_code_t\n"; 245 dumpAmdKernelCode(&Header, OS, "\t\t"); 246 OS << "\t.end_amd_kernel_code_t\n"; 247 } 248 249 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 250 unsigned Type) { 251 switch (Type) { 252 default: llvm_unreachable("Invalid AMDGPU symbol type"); 253 case ELF::STT_AMDGPU_HSA_KERNEL: 254 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 255 break; 256 } 257 } 258 259 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 260 Align Alignment) { 261 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 262 << Alignment.value() << '\n'; 263 } 264 265 bool AMDGPUTargetAsmStreamer::EmitISAVersion() { 266 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n"; 267 return true; 268 } 269 270 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 271 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 272 std::string HSAMetadataString; 273 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 274 return false; 275 276 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n'; 277 OS << HSAMetadataString << '\n'; 278 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n'; 279 return true; 280 } 281 282 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 283 msgpack::Document &HSAMetadataDoc, bool Strict) { 284 HSAMD::V3::MetadataVerifier Verifier(Strict); 285 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 286 return false; 287 288 std::string HSAMetadataString; 289 raw_string_ostream StrOS(HSAMetadataString); 290 HSAMetadataDoc.toYAML(StrOS); 291 292 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n'; 293 OS << StrOS.str() << '\n'; 294 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n'; 295 return true; 296 } 297 298 bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 299 const uint32_t Encoded_s_code_end = 0xbf9f0000; 300 const uint32_t Encoded_s_nop = 0xbf800000; 301 uint32_t Encoded_pad = Encoded_s_code_end; 302 303 // Instruction cache line size in bytes. 304 const unsigned Log2CacheLineSize = 6; 305 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 306 307 // Extra padding amount in bytes to support prefetch mode 3. 308 unsigned FillSize = 3 * CacheLineSize; 309 310 if (AMDGPU::isGFX90A(STI)) { 311 Encoded_pad = Encoded_s_nop; 312 FillSize = 16 * CacheLineSize; 313 } 314 315 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n'; 316 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n'; 317 return true; 318 } 319 320 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 321 const MCSubtargetInfo &STI, StringRef KernelName, 322 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 323 bool ReserveVCC, bool ReserveFlatScr) { 324 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 325 326 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 327 328 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 329 STREAM << "\t\t" << DIRECTIVE << " " \ 330 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 331 332 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 333 << '\n'; 334 OS << "\t\t.amdhsa_private_segment_fixed_size " 335 << KD.private_segment_fixed_size << '\n'; 336 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n'; 337 338 PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD, 339 compute_pgm_rsrc2, 340 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT); 341 342 if (!hasArchitectedFlatScratch(STI)) 343 PRINT_FIELD( 344 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 345 kernel_code_properties, 346 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 347 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 348 kernel_code_properties, 349 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 350 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 351 kernel_code_properties, 352 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 353 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 354 kernel_code_properties, 355 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 356 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 357 kernel_code_properties, 358 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 359 if (!hasArchitectedFlatScratch(STI)) 360 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 361 kernel_code_properties, 362 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 363 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 364 kernel_code_properties, 365 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 366 if (IVersion.Major >= 10) 367 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 368 kernel_code_properties, 369 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 370 PRINT_FIELD(OS, 371 (hasArchitectedFlatScratch(STI) 372 ? ".amdhsa_enable_private_segment" 373 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"), 374 KD, compute_pgm_rsrc2, 375 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 376 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 377 compute_pgm_rsrc2, 378 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 379 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 380 compute_pgm_rsrc2, 381 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 382 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 383 compute_pgm_rsrc2, 384 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 385 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 386 compute_pgm_rsrc2, 387 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 388 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 389 compute_pgm_rsrc2, 390 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 391 392 // These directives are required. 393 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 394 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 395 396 if (AMDGPU::isGFX90A(STI)) 397 OS << "\t\t.amdhsa_accum_offset " << 398 (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3, 399 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 400 << '\n'; 401 402 if (!ReserveVCC) 403 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 404 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI)) 405 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 406 407 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 408 switch (*HsaAbiVer) { 409 default: 410 break; 411 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 412 break; 413 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 414 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 415 case ELF::ELFABIVERSION_AMDGPU_HSA_V5: 416 if (getTargetID()->isXnackSupported()) 417 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n'; 418 break; 419 } 420 } 421 422 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 423 compute_pgm_rsrc1, 424 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 425 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 426 compute_pgm_rsrc1, 427 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 428 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 429 compute_pgm_rsrc1, 430 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 431 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 432 compute_pgm_rsrc1, 433 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 434 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 435 compute_pgm_rsrc1, 436 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 437 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 438 compute_pgm_rsrc1, 439 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 440 if (IVersion.Major >= 9) 441 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 442 compute_pgm_rsrc1, 443 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 444 if (AMDGPU::isGFX90A(STI)) 445 PRINT_FIELD(OS, ".amdhsa_tg_split", KD, 446 compute_pgm_rsrc3, 447 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 448 if (IVersion.Major >= 10) { 449 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 450 compute_pgm_rsrc1, 451 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 452 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 453 compute_pgm_rsrc1, 454 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 455 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 456 compute_pgm_rsrc1, 457 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 458 PRINT_FIELD(OS, ".amdhsa_shared_vgpr_count", KD, compute_pgm_rsrc3, 459 amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 460 } 461 PRINT_FIELD( 462 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 463 compute_pgm_rsrc2, 464 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 465 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 466 compute_pgm_rsrc2, 467 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 468 PRINT_FIELD( 469 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 470 compute_pgm_rsrc2, 471 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 472 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 473 compute_pgm_rsrc2, 474 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 475 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 476 compute_pgm_rsrc2, 477 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 478 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 479 compute_pgm_rsrc2, 480 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 481 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 482 compute_pgm_rsrc2, 483 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 484 #undef PRINT_FIELD 485 486 OS << "\t.end_amdhsa_kernel\n"; 487 } 488 489 //===----------------------------------------------------------------------===// 490 // AMDGPUTargetELFStreamer 491 //===----------------------------------------------------------------------===// 492 493 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 494 const MCSubtargetInfo &STI) 495 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {} 496 497 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 498 return static_cast<MCELFStreamer &>(Streamer); 499 } 500 501 // A hook for emitting stuff at the end. 502 // We use it for emitting the accumulated PAL metadata as a .note record. 503 // The PAL metadata is reset after it is emitted. 504 void AMDGPUTargetELFStreamer::finish() { 505 MCAssembler &MCA = getStreamer().getAssembler(); 506 MCA.setELFHeaderEFlags(getEFlags()); 507 508 std::string Blob; 509 const char *Vendor = getPALMetadata()->getVendor(); 510 unsigned Type = getPALMetadata()->getType(); 511 getPALMetadata()->toBlob(Type, Blob); 512 if (Blob.empty()) 513 return; 514 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 515 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 516 517 // Reset the pal metadata so its data will not affect a compilation that 518 // reuses this object. 519 getPALMetadata()->reset(); 520 } 521 522 void AMDGPUTargetELFStreamer::EmitNote( 523 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 524 function_ref<void(MCELFStreamer &)> EmitDesc) { 525 auto &S = getStreamer(); 526 auto &Context = S.getContext(); 527 528 auto NameSZ = Name.size() + 1; 529 530 unsigned NoteFlags = 0; 531 // TODO Apparently, this is currently needed for OpenCL as mentioned in 532 // https://reviews.llvm.org/D74995 533 if (STI.getTargetTriple().getOS() == Triple::AMDHSA) 534 NoteFlags = ELF::SHF_ALLOC; 535 536 S.pushSection(); 537 S.switchSection( 538 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 539 S.emitInt32(NameSZ); // namesz 540 S.emitValue(DescSZ, 4); // descz 541 S.emitInt32(NoteType); // type 542 S.emitBytes(Name); // name 543 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 544 EmitDesc(S); // desc 545 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 546 S.popSection(); 547 } 548 549 unsigned AMDGPUTargetELFStreamer::getEFlags() { 550 switch (STI.getTargetTriple().getArch()) { 551 default: 552 llvm_unreachable("Unsupported Arch"); 553 case Triple::r600: 554 return getEFlagsR600(); 555 case Triple::amdgcn: 556 return getEFlagsAMDGCN(); 557 } 558 } 559 560 unsigned AMDGPUTargetELFStreamer::getEFlagsR600() { 561 assert(STI.getTargetTriple().getArch() == Triple::r600); 562 563 return getElfMach(STI.getCPU()); 564 } 565 566 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() { 567 assert(STI.getTargetTriple().getArch() == Triple::amdgcn); 568 569 switch (STI.getTargetTriple().getOS()) { 570 default: 571 // TODO: Why are some tests have "mingw" listed as OS? 572 // llvm_unreachable("Unsupported OS"); 573 case Triple::UnknownOS: 574 return getEFlagsUnknownOS(); 575 case Triple::AMDHSA: 576 return getEFlagsAMDHSA(); 577 case Triple::AMDPAL: 578 return getEFlagsAMDPAL(); 579 case Triple::Mesa3D: 580 return getEFlagsMesa3D(); 581 } 582 } 583 584 unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() { 585 // TODO: Why are some tests have "mingw" listed as OS? 586 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS); 587 588 return getEFlagsV3(); 589 } 590 591 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() { 592 assert(STI.getTargetTriple().getOS() == Triple::AMDHSA); 593 594 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 595 switch (*HsaAbiVer) { 596 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 597 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 598 return getEFlagsV3(); 599 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 600 case ELF::ELFABIVERSION_AMDGPU_HSA_V5: 601 return getEFlagsV4(); 602 } 603 } 604 605 llvm_unreachable("HSA OS ABI Version identification must be defined"); 606 } 607 608 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() { 609 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL); 610 611 return getEFlagsV3(); 612 } 613 614 unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() { 615 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D); 616 617 return getEFlagsV3(); 618 } 619 620 unsigned AMDGPUTargetELFStreamer::getEFlagsV3() { 621 unsigned EFlagsV3 = 0; 622 623 // mach. 624 EFlagsV3 |= getElfMach(STI.getCPU()); 625 626 // xnack. 627 if (getTargetID()->isXnackOnOrAny()) 628 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3; 629 // sramecc. 630 if (getTargetID()->isSramEccOnOrAny()) 631 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3; 632 633 return EFlagsV3; 634 } 635 636 unsigned AMDGPUTargetELFStreamer::getEFlagsV4() { 637 unsigned EFlagsV4 = 0; 638 639 // mach. 640 EFlagsV4 |= getElfMach(STI.getCPU()); 641 642 // xnack. 643 switch (getTargetID()->getXnackSetting()) { 644 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 645 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4; 646 break; 647 case AMDGPU::IsaInfo::TargetIDSetting::Any: 648 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4; 649 break; 650 case AMDGPU::IsaInfo::TargetIDSetting::Off: 651 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4; 652 break; 653 case AMDGPU::IsaInfo::TargetIDSetting::On: 654 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4; 655 break; 656 } 657 // sramecc. 658 switch (getTargetID()->getSramEccSetting()) { 659 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 660 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4; 661 break; 662 case AMDGPU::IsaInfo::TargetIDSetting::Any: 663 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4; 664 break; 665 case AMDGPU::IsaInfo::TargetIDSetting::Off: 666 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4; 667 break; 668 case AMDGPU::IsaInfo::TargetIDSetting::On: 669 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4; 670 break; 671 } 672 673 return EFlagsV4; 674 } 675 676 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {} 677 678 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 679 uint32_t Major, uint32_t Minor) { 680 681 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 682 ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 683 OS.emitInt32(Major); 684 OS.emitInt32(Minor); 685 }); 686 } 687 688 void 689 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 690 uint32_t Minor, 691 uint32_t Stepping, 692 StringRef VendorName, 693 StringRef ArchName) { 694 uint16_t VendorNameSize = VendorName.size() + 1; 695 uint16_t ArchNameSize = ArchName.size() + 1; 696 697 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 698 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 699 VendorNameSize + ArchNameSize; 700 701 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 702 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 703 ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) { 704 OS.emitInt16(VendorNameSize); 705 OS.emitInt16(ArchNameSize); 706 OS.emitInt32(Major); 707 OS.emitInt32(Minor); 708 OS.emitInt32(Stepping); 709 OS.emitBytes(VendorName); 710 OS.emitInt8(0); // NULL terminate VendorName 711 OS.emitBytes(ArchName); 712 OS.emitInt8(0); // NULL terminate ArchName 713 }); 714 } 715 716 void 717 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 718 719 MCStreamer &OS = getStreamer(); 720 OS.pushSection(); 721 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 722 OS.popSection(); 723 } 724 725 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 726 unsigned Type) { 727 MCSymbolELF *Symbol = cast<MCSymbolELF>( 728 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 729 Symbol->setType(Type); 730 } 731 732 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 733 Align Alignment) { 734 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 735 SymbolELF->setType(ELF::STT_OBJECT); 736 737 if (!SymbolELF->isBindingSet()) { 738 SymbolELF->setBinding(ELF::STB_GLOBAL); 739 SymbolELF->setExternal(true); 740 } 741 742 if (SymbolELF->declareCommon(Size, Alignment.value(), true)) { 743 report_fatal_error("Symbol: " + Symbol->getName() + 744 " redeclared as different type"); 745 } 746 747 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 748 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 749 } 750 751 bool AMDGPUTargetELFStreamer::EmitISAVersion() { 752 // Create two labels to mark the beginning and end of the desc field 753 // and a MCExpr to calculate the size of the desc field. 754 auto &Context = getContext(); 755 auto *DescBegin = Context.createTempSymbol(); 756 auto *DescEnd = Context.createTempSymbol(); 757 auto *DescSZ = MCBinaryExpr::createSub( 758 MCSymbolRefExpr::create(DescEnd, Context), 759 MCSymbolRefExpr::create(DescBegin, Context), Context); 760 761 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME, 762 [&](MCELFStreamer &OS) { 763 OS.emitLabel(DescBegin); 764 OS.emitBytes(getTargetID()->toString()); 765 OS.emitLabel(DescEnd); 766 }); 767 return true; 768 } 769 770 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 771 bool Strict) { 772 HSAMD::V3::MetadataVerifier Verifier(Strict); 773 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 774 return false; 775 776 std::string HSAMetadataString; 777 HSAMetadataDoc.writeToBlob(HSAMetadataString); 778 779 // Create two labels to mark the beginning and end of the desc field 780 // and a MCExpr to calculate the size of the desc field. 781 auto &Context = getContext(); 782 auto *DescBegin = Context.createTempSymbol(); 783 auto *DescEnd = Context.createTempSymbol(); 784 auto *DescSZ = MCBinaryExpr::createSub( 785 MCSymbolRefExpr::create(DescEnd, Context), 786 MCSymbolRefExpr::create(DescBegin, Context), Context); 787 788 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 789 [&](MCELFStreamer &OS) { 790 OS.emitLabel(DescBegin); 791 OS.emitBytes(HSAMetadataString); 792 OS.emitLabel(DescEnd); 793 }); 794 return true; 795 } 796 797 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 798 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 799 std::string HSAMetadataString; 800 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 801 return false; 802 803 // Create two labels to mark the beginning and end of the desc field 804 // and a MCExpr to calculate the size of the desc field. 805 auto &Context = getContext(); 806 auto *DescBegin = Context.createTempSymbol(); 807 auto *DescEnd = Context.createTempSymbol(); 808 auto *DescSZ = MCBinaryExpr::createSub( 809 MCSymbolRefExpr::create(DescEnd, Context), 810 MCSymbolRefExpr::create(DescBegin, Context), Context); 811 812 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA, 813 [&](MCELFStreamer &OS) { 814 OS.emitLabel(DescBegin); 815 OS.emitBytes(HSAMetadataString); 816 OS.emitLabel(DescEnd); 817 }); 818 return true; 819 } 820 821 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 822 const uint32_t Encoded_s_code_end = 0xbf9f0000; 823 const uint32_t Encoded_s_nop = 0xbf800000; 824 uint32_t Encoded_pad = Encoded_s_code_end; 825 826 // Instruction cache line size in bytes. 827 const unsigned Log2CacheLineSize = 6; 828 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 829 830 // Extra padding amount in bytes to support prefetch mode 3. 831 unsigned FillSize = 3 * CacheLineSize; 832 833 if (AMDGPU::isGFX90A(STI)) { 834 Encoded_pad = Encoded_s_nop; 835 FillSize = 16 * CacheLineSize; 836 } 837 838 MCStreamer &OS = getStreamer(); 839 OS.pushSection(); 840 OS.emitValueToAlignment(CacheLineSize, Encoded_pad, 4); 841 for (unsigned I = 0; I < FillSize; I += 4) 842 OS.emitInt32(Encoded_pad); 843 OS.popSection(); 844 return true; 845 } 846 847 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 848 const MCSubtargetInfo &STI, StringRef KernelName, 849 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 850 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) { 851 auto &Streamer = getStreamer(); 852 auto &Context = Streamer.getContext(); 853 854 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 855 Context.getOrCreateSymbol(Twine(KernelName))); 856 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 857 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 858 859 // Copy kernel descriptor symbol's binding, other and visibility from the 860 // kernel code symbol. 861 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 862 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 863 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 864 // Kernel descriptor symbol's type and size are fixed. 865 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 866 KernelDescriptorSymbol->setSize( 867 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 868 869 // The visibility of the kernel code symbol must be protected or less to allow 870 // static relocations from the kernel descriptor to be used. 871 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 872 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 873 874 Streamer.emitLabel(KernelDescriptorSymbol); 875 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size); 876 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size); 877 Streamer.emitInt32(KernelDescriptor.kernarg_size); 878 879 for (uint8_t Res : KernelDescriptor.reserved0) 880 Streamer.emitInt8(Res); 881 882 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 883 // expression being created is: 884 // (start of kernel code) - (start of kernel descriptor) 885 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 886 Streamer.emitValue(MCBinaryExpr::createSub( 887 MCSymbolRefExpr::create( 888 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 889 MCSymbolRefExpr::create( 890 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 891 Context), 892 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 893 for (uint8_t Res : KernelDescriptor.reserved1) 894 Streamer.emitInt8(Res); 895 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3); 896 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1); 897 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2); 898 Streamer.emitInt16(KernelDescriptor.kernel_code_properties); 899 for (uint8_t Res : KernelDescriptor.reserved2) 900 Streamer.emitInt8(Res); 901 } 902