1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPUPTNote.h" 15 #include "AMDKernelCodeT.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/MC/MCAssembler.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCELFStreamer.h" 23 #include "llvm/MC/MCSectionELF.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/AMDGPUMetadata.h" 26 #include "llvm/Support/AMDHSAKernelDescriptor.h" 27 #include "llvm/Support/Casting.h" 28 #include "llvm/Support/FormattedStream.h" 29 #include "llvm/Support/TargetParser.h" 30 31 using namespace llvm; 32 using namespace llvm::AMDGPU; 33 34 //===----------------------------------------------------------------------===// 35 // AMDGPUTargetStreamer 36 //===----------------------------------------------------------------------===// 37 38 static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, 39 uint32_t &Stepping, bool Sramecc, bool Xnack) { 40 if (Major == 9 && Minor == 0) { 41 switch (Stepping) { 42 case 0: 43 case 2: 44 case 4: 45 case 6: 46 if (Xnack) 47 Stepping++; 48 } 49 } 50 } 51 52 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 53 HSAMD::Metadata HSAMetadata; 54 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 55 return false; 56 return EmitHSAMetadata(HSAMetadata); 57 } 58 59 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 60 msgpack::Document HSAMetadataDoc; 61 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 62 return false; 63 return EmitHSAMetadata(HSAMetadataDoc, false); 64 } 65 66 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 67 AMDGPU::GPUKind AK; 68 69 switch (ElfMach) { 70 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type"); 71 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 72 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 73 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 74 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 75 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 76 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 77 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 78 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 79 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 80 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 81 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 82 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 83 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 84 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 85 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 86 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break; 100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break; 108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break; 109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX940: AK = GK_GFX940; break; 110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 113 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break; 114 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 115 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 116 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break; 117 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break; 118 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break; 119 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: AK = GK_GFX1035; break; 120 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036: AK = GK_GFX1036; break; 121 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 122 } 123 124 StringRef GPUName = getArchNameAMDGCN(AK); 125 if (GPUName != "") 126 return GPUName; 127 return getArchNameR600(AK); 128 } 129 130 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 131 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 132 if (AK == AMDGPU::GPUKind::GK_NONE) 133 AK = parseArchR600(GPU); 134 135 switch (AK) { 136 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 137 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 138 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 139 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 140 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 141 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 142 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 143 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 144 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 145 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 146 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 147 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 148 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 149 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 150 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 151 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 152 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 153 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 154 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602; 155 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 156 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 157 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 158 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 159 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 160 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705; 161 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 162 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 163 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 164 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805; 165 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 166 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 167 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 168 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 169 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 170 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 171 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 172 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A; 173 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C; 174 case GK_GFX940: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX940; 175 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 176 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 177 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 178 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013; 179 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 180 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 181 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032; 182 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033; 183 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034; 184 case GK_GFX1035: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035; 185 case GK_GFX1036: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036; 186 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 187 } 188 189 llvm_unreachable("unknown GPU"); 190 } 191 192 //===----------------------------------------------------------------------===// 193 // AMDGPUTargetAsmStreamer 194 //===----------------------------------------------------------------------===// 195 196 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 197 formatted_raw_ostream &OS) 198 : AMDGPUTargetStreamer(S), OS(OS) { } 199 200 // A hook for emitting stuff at the end. 201 // We use it for emitting the accumulated PAL metadata as directives. 202 // The PAL metadata is reset after it is emitted. 203 void AMDGPUTargetAsmStreamer::finish() { 204 std::string S; 205 getPALMetadata()->toString(S); 206 OS << S; 207 208 // Reset the pal metadata so its data will not affect a compilation that 209 // reuses this object. 210 getPALMetadata()->reset(); 211 } 212 213 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() { 214 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n"; 215 } 216 217 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 218 uint32_t Major, uint32_t Minor) { 219 OS << "\t.hsa_code_object_version " << 220 Twine(Major) << "," << Twine(Minor) << '\n'; 221 } 222 223 void 224 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 225 uint32_t Minor, 226 uint32_t Stepping, 227 StringRef VendorName, 228 StringRef ArchName) { 229 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 230 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << "," 231 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 232 } 233 234 void 235 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 236 OS << "\t.amd_kernel_code_t\n"; 237 dumpAmdKernelCode(&Header, OS, "\t\t"); 238 OS << "\t.end_amd_kernel_code_t\n"; 239 } 240 241 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 242 unsigned Type) { 243 switch (Type) { 244 default: llvm_unreachable("Invalid AMDGPU symbol type"); 245 case ELF::STT_AMDGPU_HSA_KERNEL: 246 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 247 break; 248 } 249 } 250 251 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 252 Align Alignment) { 253 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 254 << Alignment.value() << '\n'; 255 } 256 257 bool AMDGPUTargetAsmStreamer::EmitISAVersion() { 258 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n"; 259 return true; 260 } 261 262 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 263 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 264 std::string HSAMetadataString; 265 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 266 return false; 267 268 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n'; 269 OS << HSAMetadataString << '\n'; 270 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n'; 271 return true; 272 } 273 274 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 275 msgpack::Document &HSAMetadataDoc, bool Strict) { 276 HSAMD::V3::MetadataVerifier Verifier(Strict); 277 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 278 return false; 279 280 std::string HSAMetadataString; 281 raw_string_ostream StrOS(HSAMetadataString); 282 HSAMetadataDoc.toYAML(StrOS); 283 284 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n'; 285 OS << StrOS.str() << '\n'; 286 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n'; 287 return true; 288 } 289 290 bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 291 const uint32_t Encoded_s_code_end = 0xbf9f0000; 292 const uint32_t Encoded_s_nop = 0xbf800000; 293 uint32_t Encoded_pad = Encoded_s_code_end; 294 295 // Instruction cache line size in bytes. 296 const unsigned Log2CacheLineSize = 6; 297 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 298 299 // Extra padding amount in bytes to support prefetch mode 3. 300 unsigned FillSize = 3 * CacheLineSize; 301 302 if (AMDGPU::isGFX90A(STI)) { 303 Encoded_pad = Encoded_s_nop; 304 FillSize = 16 * CacheLineSize; 305 } 306 307 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n'; 308 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n'; 309 return true; 310 } 311 312 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 313 const MCSubtargetInfo &STI, StringRef KernelName, 314 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 315 bool ReserveVCC, bool ReserveFlatScr) { 316 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 317 318 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 319 320 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 321 STREAM << "\t\t" << DIRECTIVE << " " \ 322 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 323 324 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 325 << '\n'; 326 OS << "\t\t.amdhsa_private_segment_fixed_size " 327 << KD.private_segment_fixed_size << '\n'; 328 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n'; 329 330 PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD, 331 compute_pgm_rsrc2, 332 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT); 333 334 if (!hasArchitectedFlatScratch(STI)) 335 PRINT_FIELD( 336 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 337 kernel_code_properties, 338 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 339 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 340 kernel_code_properties, 341 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 342 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 343 kernel_code_properties, 344 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 345 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 346 kernel_code_properties, 347 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 348 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 349 kernel_code_properties, 350 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 351 if (!hasArchitectedFlatScratch(STI)) 352 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 353 kernel_code_properties, 354 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 355 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 356 kernel_code_properties, 357 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 358 if (IVersion.Major >= 10) 359 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 360 kernel_code_properties, 361 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 362 PRINT_FIELD(OS, 363 (hasArchitectedFlatScratch(STI) 364 ? ".amdhsa_enable_private_segment" 365 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"), 366 KD, compute_pgm_rsrc2, 367 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 368 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 369 compute_pgm_rsrc2, 370 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 371 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 372 compute_pgm_rsrc2, 373 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 374 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 375 compute_pgm_rsrc2, 376 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 377 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 378 compute_pgm_rsrc2, 379 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 380 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 381 compute_pgm_rsrc2, 382 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 383 384 // These directives are required. 385 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 386 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 387 388 if (AMDGPU::isGFX90A(STI)) 389 OS << "\t\t.amdhsa_accum_offset " << 390 (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3, 391 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 392 << '\n'; 393 394 if (!ReserveVCC) 395 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 396 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI)) 397 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 398 399 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 400 switch (*HsaAbiVer) { 401 default: 402 break; 403 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 404 break; 405 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 406 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 407 case ELF::ELFABIVERSION_AMDGPU_HSA_V5: 408 if (getTargetID()->isXnackSupported()) 409 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n'; 410 break; 411 } 412 } 413 414 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 415 compute_pgm_rsrc1, 416 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 417 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 418 compute_pgm_rsrc1, 419 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 420 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 421 compute_pgm_rsrc1, 422 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 423 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 424 compute_pgm_rsrc1, 425 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 426 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 427 compute_pgm_rsrc1, 428 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 429 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 430 compute_pgm_rsrc1, 431 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 432 if (IVersion.Major >= 9) 433 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 434 compute_pgm_rsrc1, 435 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 436 if (AMDGPU::isGFX90A(STI)) 437 PRINT_FIELD(OS, ".amdhsa_tg_split", KD, 438 compute_pgm_rsrc3, 439 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 440 if (IVersion.Major >= 10) { 441 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 442 compute_pgm_rsrc1, 443 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 444 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 445 compute_pgm_rsrc1, 446 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 447 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 448 compute_pgm_rsrc1, 449 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 450 } 451 PRINT_FIELD( 452 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 453 compute_pgm_rsrc2, 454 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 455 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 456 compute_pgm_rsrc2, 457 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 458 PRINT_FIELD( 459 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 460 compute_pgm_rsrc2, 461 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 462 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 463 compute_pgm_rsrc2, 464 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 465 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 466 compute_pgm_rsrc2, 467 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 468 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 469 compute_pgm_rsrc2, 470 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 471 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 472 compute_pgm_rsrc2, 473 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 474 #undef PRINT_FIELD 475 476 OS << "\t.end_amdhsa_kernel\n"; 477 } 478 479 //===----------------------------------------------------------------------===// 480 // AMDGPUTargetELFStreamer 481 //===----------------------------------------------------------------------===// 482 483 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 484 const MCSubtargetInfo &STI) 485 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {} 486 487 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 488 return static_cast<MCELFStreamer &>(Streamer); 489 } 490 491 // A hook for emitting stuff at the end. 492 // We use it for emitting the accumulated PAL metadata as a .note record. 493 // The PAL metadata is reset after it is emitted. 494 void AMDGPUTargetELFStreamer::finish() { 495 MCAssembler &MCA = getStreamer().getAssembler(); 496 MCA.setELFHeaderEFlags(getEFlags()); 497 498 std::string Blob; 499 const char *Vendor = getPALMetadata()->getVendor(); 500 unsigned Type = getPALMetadata()->getType(); 501 getPALMetadata()->toBlob(Type, Blob); 502 if (Blob.empty()) 503 return; 504 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 505 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 506 507 // Reset the pal metadata so its data will not affect a compilation that 508 // reuses this object. 509 getPALMetadata()->reset(); 510 } 511 512 void AMDGPUTargetELFStreamer::EmitNote( 513 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 514 function_ref<void(MCELFStreamer &)> EmitDesc) { 515 auto &S = getStreamer(); 516 auto &Context = S.getContext(); 517 518 auto NameSZ = Name.size() + 1; 519 520 unsigned NoteFlags = 0; 521 // TODO Apparently, this is currently needed for OpenCL as mentioned in 522 // https://reviews.llvm.org/D74995 523 if (STI.getTargetTriple().getOS() == Triple::AMDHSA) 524 NoteFlags = ELF::SHF_ALLOC; 525 526 S.PushSection(); 527 S.SwitchSection( 528 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 529 S.emitInt32(NameSZ); // namesz 530 S.emitValue(DescSZ, 4); // descz 531 S.emitInt32(NoteType); // type 532 S.emitBytes(Name); // name 533 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 534 EmitDesc(S); // desc 535 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 536 S.PopSection(); 537 } 538 539 unsigned AMDGPUTargetELFStreamer::getEFlags() { 540 switch (STI.getTargetTriple().getArch()) { 541 default: 542 llvm_unreachable("Unsupported Arch"); 543 case Triple::r600: 544 return getEFlagsR600(); 545 case Triple::amdgcn: 546 return getEFlagsAMDGCN(); 547 } 548 } 549 550 unsigned AMDGPUTargetELFStreamer::getEFlagsR600() { 551 assert(STI.getTargetTriple().getArch() == Triple::r600); 552 553 return getElfMach(STI.getCPU()); 554 } 555 556 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() { 557 assert(STI.getTargetTriple().getArch() == Triple::amdgcn); 558 559 switch (STI.getTargetTriple().getOS()) { 560 default: 561 // TODO: Why are some tests have "mingw" listed as OS? 562 // llvm_unreachable("Unsupported OS"); 563 case Triple::UnknownOS: 564 return getEFlagsUnknownOS(); 565 case Triple::AMDHSA: 566 return getEFlagsAMDHSA(); 567 case Triple::AMDPAL: 568 return getEFlagsAMDPAL(); 569 case Triple::Mesa3D: 570 return getEFlagsMesa3D(); 571 } 572 } 573 574 unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() { 575 // TODO: Why are some tests have "mingw" listed as OS? 576 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS); 577 578 return getEFlagsV3(); 579 } 580 581 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() { 582 assert(STI.getTargetTriple().getOS() == Triple::AMDHSA); 583 584 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 585 switch (*HsaAbiVer) { 586 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 587 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 588 return getEFlagsV3(); 589 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 590 case ELF::ELFABIVERSION_AMDGPU_HSA_V5: 591 return getEFlagsV4(); 592 } 593 } 594 595 llvm_unreachable("HSA OS ABI Version identification must be defined"); 596 } 597 598 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() { 599 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL); 600 601 return getEFlagsV3(); 602 } 603 604 unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() { 605 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D); 606 607 return getEFlagsV3(); 608 } 609 610 unsigned AMDGPUTargetELFStreamer::getEFlagsV3() { 611 unsigned EFlagsV3 = 0; 612 613 // mach. 614 EFlagsV3 |= getElfMach(STI.getCPU()); 615 616 // xnack. 617 if (getTargetID()->isXnackOnOrAny()) 618 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3; 619 // sramecc. 620 if (getTargetID()->isSramEccOnOrAny()) 621 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3; 622 623 return EFlagsV3; 624 } 625 626 unsigned AMDGPUTargetELFStreamer::getEFlagsV4() { 627 unsigned EFlagsV4 = 0; 628 629 // mach. 630 EFlagsV4 |= getElfMach(STI.getCPU()); 631 632 // xnack. 633 switch (getTargetID()->getXnackSetting()) { 634 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 635 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4; 636 break; 637 case AMDGPU::IsaInfo::TargetIDSetting::Any: 638 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4; 639 break; 640 case AMDGPU::IsaInfo::TargetIDSetting::Off: 641 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4; 642 break; 643 case AMDGPU::IsaInfo::TargetIDSetting::On: 644 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4; 645 break; 646 } 647 // sramecc. 648 switch (getTargetID()->getSramEccSetting()) { 649 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 650 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4; 651 break; 652 case AMDGPU::IsaInfo::TargetIDSetting::Any: 653 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4; 654 break; 655 case AMDGPU::IsaInfo::TargetIDSetting::Off: 656 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4; 657 break; 658 case AMDGPU::IsaInfo::TargetIDSetting::On: 659 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4; 660 break; 661 } 662 663 return EFlagsV4; 664 } 665 666 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {} 667 668 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 669 uint32_t Major, uint32_t Minor) { 670 671 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 672 ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 673 OS.emitInt32(Major); 674 OS.emitInt32(Minor); 675 }); 676 } 677 678 void 679 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 680 uint32_t Minor, 681 uint32_t Stepping, 682 StringRef VendorName, 683 StringRef ArchName) { 684 uint16_t VendorNameSize = VendorName.size() + 1; 685 uint16_t ArchNameSize = ArchName.size() + 1; 686 687 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 688 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 689 VendorNameSize + ArchNameSize; 690 691 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 692 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 693 ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) { 694 OS.emitInt16(VendorNameSize); 695 OS.emitInt16(ArchNameSize); 696 OS.emitInt32(Major); 697 OS.emitInt32(Minor); 698 OS.emitInt32(Stepping); 699 OS.emitBytes(VendorName); 700 OS.emitInt8(0); // NULL terminate VendorName 701 OS.emitBytes(ArchName); 702 OS.emitInt8(0); // NULL terminate ArchName 703 }); 704 } 705 706 void 707 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 708 709 MCStreamer &OS = getStreamer(); 710 OS.PushSection(); 711 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 712 OS.PopSection(); 713 } 714 715 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 716 unsigned Type) { 717 MCSymbolELF *Symbol = cast<MCSymbolELF>( 718 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 719 Symbol->setType(Type); 720 } 721 722 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 723 Align Alignment) { 724 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 725 SymbolELF->setType(ELF::STT_OBJECT); 726 727 if (!SymbolELF->isBindingSet()) { 728 SymbolELF->setBinding(ELF::STB_GLOBAL); 729 SymbolELF->setExternal(true); 730 } 731 732 if (SymbolELF->declareCommon(Size, Alignment.value(), true)) { 733 report_fatal_error("Symbol: " + Symbol->getName() + 734 " redeclared as different type"); 735 } 736 737 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 738 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 739 } 740 741 bool AMDGPUTargetELFStreamer::EmitISAVersion() { 742 // Create two labels to mark the beginning and end of the desc field 743 // and a MCExpr to calculate the size of the desc field. 744 auto &Context = getContext(); 745 auto *DescBegin = Context.createTempSymbol(); 746 auto *DescEnd = Context.createTempSymbol(); 747 auto *DescSZ = MCBinaryExpr::createSub( 748 MCSymbolRefExpr::create(DescEnd, Context), 749 MCSymbolRefExpr::create(DescBegin, Context), Context); 750 751 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME, 752 [&](MCELFStreamer &OS) { 753 OS.emitLabel(DescBegin); 754 OS.emitBytes(getTargetID()->toString()); 755 OS.emitLabel(DescEnd); 756 }); 757 return true; 758 } 759 760 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 761 bool Strict) { 762 HSAMD::V3::MetadataVerifier Verifier(Strict); 763 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 764 return false; 765 766 std::string HSAMetadataString; 767 HSAMetadataDoc.writeToBlob(HSAMetadataString); 768 769 // Create two labels to mark the beginning and end of the desc field 770 // and a MCExpr to calculate the size of the desc field. 771 auto &Context = getContext(); 772 auto *DescBegin = Context.createTempSymbol(); 773 auto *DescEnd = Context.createTempSymbol(); 774 auto *DescSZ = MCBinaryExpr::createSub( 775 MCSymbolRefExpr::create(DescEnd, Context), 776 MCSymbolRefExpr::create(DescBegin, Context), Context); 777 778 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 779 [&](MCELFStreamer &OS) { 780 OS.emitLabel(DescBegin); 781 OS.emitBytes(HSAMetadataString); 782 OS.emitLabel(DescEnd); 783 }); 784 return true; 785 } 786 787 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 788 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 789 std::string HSAMetadataString; 790 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 791 return false; 792 793 // Create two labels to mark the beginning and end of the desc field 794 // and a MCExpr to calculate the size of the desc field. 795 auto &Context = getContext(); 796 auto *DescBegin = Context.createTempSymbol(); 797 auto *DescEnd = Context.createTempSymbol(); 798 auto *DescSZ = MCBinaryExpr::createSub( 799 MCSymbolRefExpr::create(DescEnd, Context), 800 MCSymbolRefExpr::create(DescBegin, Context), Context); 801 802 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA, 803 [&](MCELFStreamer &OS) { 804 OS.emitLabel(DescBegin); 805 OS.emitBytes(HSAMetadataString); 806 OS.emitLabel(DescEnd); 807 }); 808 return true; 809 } 810 811 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 812 const uint32_t Encoded_s_code_end = 0xbf9f0000; 813 const uint32_t Encoded_s_nop = 0xbf800000; 814 uint32_t Encoded_pad = Encoded_s_code_end; 815 816 // Instruction cache line size in bytes. 817 const unsigned Log2CacheLineSize = 6; 818 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 819 820 // Extra padding amount in bytes to support prefetch mode 3. 821 unsigned FillSize = 3 * CacheLineSize; 822 823 if (AMDGPU::isGFX90A(STI)) { 824 Encoded_pad = Encoded_s_nop; 825 FillSize = 16 * CacheLineSize; 826 } 827 828 MCStreamer &OS = getStreamer(); 829 OS.PushSection(); 830 OS.emitValueToAlignment(CacheLineSize, Encoded_pad, 4); 831 for (unsigned I = 0; I < FillSize; I += 4) 832 OS.emitInt32(Encoded_pad); 833 OS.PopSection(); 834 return true; 835 } 836 837 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 838 const MCSubtargetInfo &STI, StringRef KernelName, 839 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 840 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) { 841 auto &Streamer = getStreamer(); 842 auto &Context = Streamer.getContext(); 843 844 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 845 Context.getOrCreateSymbol(Twine(KernelName))); 846 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 847 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 848 849 // Copy kernel descriptor symbol's binding, other and visibility from the 850 // kernel code symbol. 851 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 852 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 853 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 854 // Kernel descriptor symbol's type and size are fixed. 855 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 856 KernelDescriptorSymbol->setSize( 857 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 858 859 // The visibility of the kernel code symbol must be protected or less to allow 860 // static relocations from the kernel descriptor to be used. 861 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 862 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 863 864 Streamer.emitLabel(KernelDescriptorSymbol); 865 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size); 866 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size); 867 Streamer.emitInt32(KernelDescriptor.kernarg_size); 868 869 for (uint8_t Res : KernelDescriptor.reserved0) 870 Streamer.emitInt8(Res); 871 872 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 873 // expression being created is: 874 // (start of kernel code) - (start of kernel descriptor) 875 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 876 Streamer.emitValue(MCBinaryExpr::createSub( 877 MCSymbolRefExpr::create( 878 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 879 MCSymbolRefExpr::create( 880 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 881 Context), 882 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 883 for (uint8_t Res : KernelDescriptor.reserved1) 884 Streamer.emitInt8(Res); 885 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3); 886 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1); 887 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2); 888 Streamer.emitInt16(KernelDescriptor.kernel_code_properties); 889 for (uint8_t Res : KernelDescriptor.reserved2) 890 Streamer.emitInt8(Res); 891 } 892