1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPU.h" 15 #include "SIDefines.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/ADT/Twine.h" 19 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/IR/Constants.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/IR/Metadata.h" 24 #include "llvm/IR/Module.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCELFStreamer.h" 27 #include "llvm/MC/MCObjectFileInfo.h" 28 #include "llvm/MC/MCSectionELF.h" 29 #include "llvm/Support/FormattedStream.h" 30 #include "llvm/Support/TargetParser.h" 31 32 namespace llvm { 33 #include "AMDGPUPTNote.h" 34 } 35 36 using namespace llvm; 37 using namespace llvm::AMDGPU; 38 using namespace llvm::AMDGPU::HSAMD; 39 40 //===----------------------------------------------------------------------===// 41 // AMDGPUTargetStreamer 42 //===----------------------------------------------------------------------===// 43 44 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 45 HSAMD::Metadata HSAMetadata; 46 if (HSAMD::fromString(std::string(HSAMetadataString), HSAMetadata)) 47 return false; 48 49 return EmitHSAMetadata(HSAMetadata); 50 } 51 52 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 53 msgpack::Document HSAMetadataDoc; 54 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 55 return false; 56 return EmitHSAMetadata(HSAMetadataDoc, false); 57 } 58 59 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 60 AMDGPU::GPUKind AK; 61 62 switch (ElfMach) { 63 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type"); 64 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 65 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 66 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 67 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 68 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 69 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 70 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 71 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 72 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 73 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 74 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 75 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 76 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 77 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 78 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 79 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 80 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 81 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 82 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 105 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 106 } 107 108 StringRef GPUName = getArchNameAMDGCN(AK); 109 if (GPUName != "") 110 return GPUName; 111 return getArchNameR600(AK); 112 } 113 114 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 115 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 116 if (AK == AMDGPU::GPUKind::GK_NONE) 117 AK = parseArchR600(GPU); 118 119 switch (AK) { 120 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 121 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 122 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 123 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 124 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 125 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 126 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 127 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 128 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 129 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 130 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 131 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 132 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 133 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 134 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 135 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 136 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 137 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 138 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602; 139 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 140 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 141 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 142 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 143 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 144 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705; 145 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 146 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 147 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 148 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805; 149 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 150 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 151 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 152 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 153 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 154 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 155 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 156 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 157 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 158 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 159 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 160 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 161 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 162 } 163 164 llvm_unreachable("unknown GPU"); 165 } 166 167 //===----------------------------------------------------------------------===// 168 // AMDGPUTargetAsmStreamer 169 //===----------------------------------------------------------------------===// 170 171 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 172 formatted_raw_ostream &OS) 173 : AMDGPUTargetStreamer(S), OS(OS) { } 174 175 // A hook for emitting stuff at the end. 176 // We use it for emitting the accumulated PAL metadata as directives. 177 // The PAL metadata is reset after it is emitted. 178 void AMDGPUTargetAsmStreamer::finish() { 179 std::string S; 180 getPALMetadata()->toString(S); 181 OS << S; 182 183 // Reset the pal metadata so its data will not affect a compilation that 184 // reuses this object. 185 getPALMetadata()->reset(); 186 } 187 188 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) { 189 OS << "\t.amdgcn_target \"" << Target << "\"\n"; 190 } 191 192 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 193 uint32_t Major, uint32_t Minor) { 194 OS << "\t.hsa_code_object_version " << 195 Twine(Major) << "," << Twine(Minor) << '\n'; 196 } 197 198 void 199 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 200 uint32_t Minor, 201 uint32_t Stepping, 202 StringRef VendorName, 203 StringRef ArchName) { 204 OS << "\t.hsa_code_object_isa " << 205 Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) << 206 ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 207 208 } 209 210 void 211 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 212 OS << "\t.amd_kernel_code_t\n"; 213 dumpAmdKernelCode(&Header, OS, "\t\t"); 214 OS << "\t.end_amd_kernel_code_t\n"; 215 } 216 217 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 218 unsigned Type) { 219 switch (Type) { 220 default: llvm_unreachable("Invalid AMDGPU symbol type"); 221 case ELF::STT_AMDGPU_HSA_KERNEL: 222 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 223 break; 224 } 225 } 226 227 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 228 Align Alignment) { 229 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 230 << Alignment.value() << '\n'; 231 } 232 233 bool AMDGPUTargetAsmStreamer::EmitISAVersion(StringRef IsaVersionString) { 234 OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n"; 235 return true; 236 } 237 238 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 239 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 240 std::string HSAMetadataString; 241 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 242 return false; 243 244 OS << '\t' << AssemblerDirectiveBegin << '\n'; 245 OS << HSAMetadataString << '\n'; 246 OS << '\t' << AssemblerDirectiveEnd << '\n'; 247 return true; 248 } 249 250 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 251 msgpack::Document &HSAMetadataDoc, bool Strict) { 252 V3::MetadataVerifier Verifier(Strict); 253 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 254 return false; 255 256 std::string HSAMetadataString; 257 raw_string_ostream StrOS(HSAMetadataString); 258 HSAMetadataDoc.toYAML(StrOS); 259 260 OS << '\t' << V3::AssemblerDirectiveBegin << '\n'; 261 OS << StrOS.str() << '\n'; 262 OS << '\t' << V3::AssemblerDirectiveEnd << '\n'; 263 return true; 264 } 265 266 bool AMDGPUTargetAsmStreamer::EmitCodeEnd() { 267 const uint32_t Encoded_s_code_end = 0xbf9f0000; 268 OS << "\t.p2alignl 6, " << Encoded_s_code_end << '\n'; 269 OS << "\t.fill 48, 4, " << Encoded_s_code_end << '\n'; 270 return true; 271 } 272 273 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 274 const MCSubtargetInfo &STI, StringRef KernelName, 275 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 276 bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) { 277 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 278 279 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 280 281 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 282 STREAM << "\t\t" << DIRECTIVE << " " \ 283 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 284 285 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 286 << '\n'; 287 OS << "\t\t.amdhsa_private_segment_fixed_size " 288 << KD.private_segment_fixed_size << '\n'; 289 290 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 291 kernel_code_properties, 292 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 293 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 294 kernel_code_properties, 295 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 296 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 297 kernel_code_properties, 298 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 299 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 300 kernel_code_properties, 301 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 302 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 303 kernel_code_properties, 304 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 305 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 306 kernel_code_properties, 307 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 308 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 309 kernel_code_properties, 310 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 311 if (IVersion.Major >= 10) 312 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 313 kernel_code_properties, 314 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 315 PRINT_FIELD( 316 OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, 317 compute_pgm_rsrc2, 318 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET); 319 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 320 compute_pgm_rsrc2, 321 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 322 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 323 compute_pgm_rsrc2, 324 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 325 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 326 compute_pgm_rsrc2, 327 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 328 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 329 compute_pgm_rsrc2, 330 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 331 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 332 compute_pgm_rsrc2, 333 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 334 335 // These directives are required. 336 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 337 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 338 339 if (!ReserveVCC) 340 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 341 if (IVersion.Major >= 7 && !ReserveFlatScr) 342 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 343 if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI)) 344 OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n'; 345 346 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 347 compute_pgm_rsrc1, 348 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 349 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 350 compute_pgm_rsrc1, 351 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 352 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 353 compute_pgm_rsrc1, 354 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 355 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 356 compute_pgm_rsrc1, 357 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 358 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 359 compute_pgm_rsrc1, 360 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 361 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 362 compute_pgm_rsrc1, 363 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 364 if (IVersion.Major >= 9) 365 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 366 compute_pgm_rsrc1, 367 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 368 if (IVersion.Major >= 10) { 369 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 370 compute_pgm_rsrc1, 371 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 372 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 373 compute_pgm_rsrc1, 374 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 375 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 376 compute_pgm_rsrc1, 377 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 378 } 379 PRINT_FIELD( 380 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 381 compute_pgm_rsrc2, 382 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 383 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 384 compute_pgm_rsrc2, 385 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 386 PRINT_FIELD( 387 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 388 compute_pgm_rsrc2, 389 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 390 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 391 compute_pgm_rsrc2, 392 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 393 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 394 compute_pgm_rsrc2, 395 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 396 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 397 compute_pgm_rsrc2, 398 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 399 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 400 compute_pgm_rsrc2, 401 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 402 #undef PRINT_FIELD 403 404 OS << "\t.end_amdhsa_kernel\n"; 405 } 406 407 //===----------------------------------------------------------------------===// 408 // AMDGPUTargetELFStreamer 409 //===----------------------------------------------------------------------===// 410 411 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 412 const MCSubtargetInfo &STI) 413 : AMDGPUTargetStreamer(S), Streamer(S), Os(STI.getTargetTriple().getOS()) { 414 MCAssembler &MCA = getStreamer().getAssembler(); 415 unsigned EFlags = MCA.getELFHeaderEFlags(); 416 417 EFlags &= ~ELF::EF_AMDGPU_MACH; 418 EFlags |= getElfMach(STI.getCPU()); 419 420 EFlags &= ~ELF::EF_AMDGPU_XNACK; 421 if (AMDGPU::hasXNACK(STI)) 422 EFlags |= ELF::EF_AMDGPU_XNACK; 423 424 EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC; 425 if (AMDGPU::hasSRAMECC(STI)) 426 EFlags |= ELF::EF_AMDGPU_SRAM_ECC; 427 428 MCA.setELFHeaderEFlags(EFlags); 429 } 430 431 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 432 return static_cast<MCELFStreamer &>(Streamer); 433 } 434 435 // A hook for emitting stuff at the end. 436 // We use it for emitting the accumulated PAL metadata as a .note record. 437 // The PAL metadata is reset after it is emitted. 438 void AMDGPUTargetELFStreamer::finish() { 439 std::string Blob; 440 const char *Vendor = getPALMetadata()->getVendor(); 441 unsigned Type = getPALMetadata()->getType(); 442 getPALMetadata()->toBlob(Type, Blob); 443 if (Blob.empty()) 444 return; 445 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 446 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 447 448 // Reset the pal metadata so its data will not affect a compilation that 449 // reuses this object. 450 getPALMetadata()->reset(); 451 } 452 453 void AMDGPUTargetELFStreamer::EmitNote( 454 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 455 function_ref<void(MCELFStreamer &)> EmitDesc) { 456 auto &S = getStreamer(); 457 auto &Context = S.getContext(); 458 459 auto NameSZ = Name.size() + 1; 460 461 unsigned NoteFlags = 0; 462 // TODO Apparently, this is currently needed for OpenCL as mentioned in 463 // https://reviews.llvm.org/D74995 464 if (Os == Triple::AMDHSA) 465 NoteFlags = ELF::SHF_ALLOC; 466 467 S.PushSection(); 468 S.SwitchSection( 469 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 470 S.emitInt32(NameSZ); // namesz 471 S.emitValue(DescSZ, 4); // descz 472 S.emitInt32(NoteType); // type 473 S.emitBytes(Name); // name 474 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 475 EmitDesc(S); // desc 476 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 477 S.PopSection(); 478 } 479 480 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {} 481 482 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 483 uint32_t Major, uint32_t Minor) { 484 485 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 486 ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 487 OS.emitInt32(Major); 488 OS.emitInt32(Minor); 489 }); 490 } 491 492 void 493 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 494 uint32_t Minor, 495 uint32_t Stepping, 496 StringRef VendorName, 497 StringRef ArchName) { 498 uint16_t VendorNameSize = VendorName.size() + 1; 499 uint16_t ArchNameSize = ArchName.size() + 1; 500 501 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 502 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 503 VendorNameSize + ArchNameSize; 504 505 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 506 ElfNote::NT_AMDGPU_HSA_ISA, [&](MCELFStreamer &OS) { 507 OS.emitInt16(VendorNameSize); 508 OS.emitInt16(ArchNameSize); 509 OS.emitInt32(Major); 510 OS.emitInt32(Minor); 511 OS.emitInt32(Stepping); 512 OS.emitBytes(VendorName); 513 OS.emitInt8(0); // NULL terminate VendorName 514 OS.emitBytes(ArchName); 515 OS.emitInt8(0); // NULL terminte ArchName 516 }); 517 } 518 519 void 520 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 521 522 MCStreamer &OS = getStreamer(); 523 OS.PushSection(); 524 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 525 OS.PopSection(); 526 } 527 528 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 529 unsigned Type) { 530 MCSymbolELF *Symbol = cast<MCSymbolELF>( 531 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 532 Symbol->setType(Type); 533 } 534 535 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 536 Align Alignment) { 537 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 538 SymbolELF->setType(ELF::STT_OBJECT); 539 540 if (!SymbolELF->isBindingSet()) { 541 SymbolELF->setBinding(ELF::STB_GLOBAL); 542 SymbolELF->setExternal(true); 543 } 544 545 if (SymbolELF->declareCommon(Size, Alignment.value(), true)) { 546 report_fatal_error("Symbol: " + Symbol->getName() + 547 " redeclared as different type"); 548 } 549 550 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 551 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 552 } 553 554 bool AMDGPUTargetELFStreamer::EmitISAVersion(StringRef IsaVersionString) { 555 // Create two labels to mark the beginning and end of the desc field 556 // and a MCExpr to calculate the size of the desc field. 557 auto &Context = getContext(); 558 auto *DescBegin = Context.createTempSymbol(); 559 auto *DescEnd = Context.createTempSymbol(); 560 auto *DescSZ = MCBinaryExpr::createSub( 561 MCSymbolRefExpr::create(DescEnd, Context), 562 MCSymbolRefExpr::create(DescBegin, Context), Context); 563 564 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_ISA, 565 [&](MCELFStreamer &OS) { 566 OS.emitLabel(DescBegin); 567 OS.emitBytes(IsaVersionString); 568 OS.emitLabel(DescEnd); 569 }); 570 return true; 571 } 572 573 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 574 bool Strict) { 575 V3::MetadataVerifier Verifier(Strict); 576 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 577 return false; 578 579 std::string HSAMetadataString; 580 HSAMetadataDoc.writeToBlob(HSAMetadataString); 581 582 // Create two labels to mark the beginning and end of the desc field 583 // and a MCExpr to calculate the size of the desc field. 584 auto &Context = getContext(); 585 auto *DescBegin = Context.createTempSymbol(); 586 auto *DescEnd = Context.createTempSymbol(); 587 auto *DescSZ = MCBinaryExpr::createSub( 588 MCSymbolRefExpr::create(DescEnd, Context), 589 MCSymbolRefExpr::create(DescBegin, Context), Context); 590 591 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 592 [&](MCELFStreamer &OS) { 593 OS.emitLabel(DescBegin); 594 OS.emitBytes(HSAMetadataString); 595 OS.emitLabel(DescEnd); 596 }); 597 return true; 598 } 599 600 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 601 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 602 std::string HSAMetadataString; 603 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 604 return false; 605 606 // Create two labels to mark the beginning and end of the desc field 607 // and a MCExpr to calculate the size of the desc field. 608 auto &Context = getContext(); 609 auto *DescBegin = Context.createTempSymbol(); 610 auto *DescEnd = Context.createTempSymbol(); 611 auto *DescSZ = MCBinaryExpr::createSub( 612 MCSymbolRefExpr::create(DescEnd, Context), 613 MCSymbolRefExpr::create(DescBegin, Context), Context); 614 615 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_HSA_METADATA, 616 [&](MCELFStreamer &OS) { 617 OS.emitLabel(DescBegin); 618 OS.emitBytes(HSAMetadataString); 619 OS.emitLabel(DescEnd); 620 }); 621 return true; 622 } 623 624 bool AMDGPUTargetELFStreamer::EmitCodeEnd() { 625 const uint32_t Encoded_s_code_end = 0xbf9f0000; 626 627 MCStreamer &OS = getStreamer(); 628 OS.PushSection(); 629 OS.emitValueToAlignment(64, Encoded_s_code_end, 4); 630 for (unsigned I = 0; I < 48; ++I) 631 OS.emitInt32(Encoded_s_code_end); 632 OS.PopSection(); 633 return true; 634 } 635 636 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 637 const MCSubtargetInfo &STI, StringRef KernelName, 638 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 639 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, 640 bool ReserveXNACK) { 641 auto &Streamer = getStreamer(); 642 auto &Context = Streamer.getContext(); 643 644 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 645 Context.getOrCreateSymbol(Twine(KernelName))); 646 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 647 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 648 649 // Copy kernel descriptor symbol's binding, other and visibility from the 650 // kernel code symbol. 651 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 652 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 653 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 654 // Kernel descriptor symbol's type and size are fixed. 655 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 656 KernelDescriptorSymbol->setSize( 657 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 658 659 // The visibility of the kernel code symbol must be protected or less to allow 660 // static relocations from the kernel descriptor to be used. 661 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 662 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 663 664 Streamer.emitLabel(KernelDescriptorSymbol); 665 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size); 666 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size); 667 for (uint8_t Res : KernelDescriptor.reserved0) 668 Streamer.emitInt8(Res); 669 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 670 // expression being created is: 671 // (start of kernel code) - (start of kernel descriptor) 672 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 673 Streamer.emitValue(MCBinaryExpr::createSub( 674 MCSymbolRefExpr::create( 675 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 676 MCSymbolRefExpr::create( 677 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 678 Context), 679 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 680 for (uint8_t Res : KernelDescriptor.reserved1) 681 Streamer.emitInt8(Res); 682 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3); 683 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1); 684 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2); 685 Streamer.emitInt16(KernelDescriptor.kernel_code_properties); 686 for (uint8_t Res : KernelDescriptor.reserved2) 687 Streamer.emitInt8(Res); 688 } 689