1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPU.h" 15 #include "SIDefines.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/ADT/Twine.h" 19 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/IR/Constants.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/IR/Metadata.h" 24 #include "llvm/IR/Module.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCELFStreamer.h" 27 #include "llvm/MC/MCObjectFileInfo.h" 28 #include "llvm/MC/MCSectionELF.h" 29 #include "llvm/Support/FormattedStream.h" 30 #include "llvm/Support/TargetParser.h" 31 32 namespace llvm { 33 #include "AMDGPUPTNote.h" 34 } 35 36 using namespace llvm; 37 using namespace llvm::AMDGPU; 38 using namespace llvm::AMDGPU::HSAMD; 39 40 //===----------------------------------------------------------------------===// 41 // AMDGPUTargetStreamer 42 //===----------------------------------------------------------------------===// 43 44 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 45 HSAMD::Metadata HSAMetadata; 46 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 47 return false; 48 49 return EmitHSAMetadata(HSAMetadata); 50 } 51 52 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 53 msgpack::Document HSAMetadataDoc; 54 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 55 return false; 56 return EmitHSAMetadata(HSAMetadataDoc, false); 57 } 58 59 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 60 AMDGPU::GPUKind AK; 61 62 switch (ElfMach) { 63 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 64 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 65 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 66 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 67 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 68 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 69 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 70 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 71 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 72 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 73 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 74 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 75 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 76 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 77 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 78 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 79 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 80 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 81 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 82 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 98 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 99 } 100 101 StringRef GPUName = getArchNameAMDGCN(AK); 102 if (GPUName != "") 103 return GPUName; 104 return getArchNameR600(AK); 105 } 106 107 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 108 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 109 if (AK == AMDGPU::GPUKind::GK_NONE) 110 AK = parseArchR600(GPU); 111 112 switch (AK) { 113 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 114 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 115 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 116 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 117 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 118 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 119 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 120 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 121 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 122 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 123 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 124 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 125 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 126 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 127 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 128 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 129 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 130 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 131 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 132 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 133 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 134 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 135 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 136 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 137 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 138 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 139 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 140 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 141 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 142 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 143 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 144 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 145 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 146 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 147 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 148 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 149 } 150 151 llvm_unreachable("unknown GPU"); 152 } 153 154 //===----------------------------------------------------------------------===// 155 // AMDGPUTargetAsmStreamer 156 //===----------------------------------------------------------------------===// 157 158 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 159 formatted_raw_ostream &OS) 160 : AMDGPUTargetStreamer(S), OS(OS) { } 161 162 // A hook for emitting stuff at the end. 163 // We use it for emitting the accumulated PAL metadata as directives. 164 void AMDGPUTargetAsmStreamer::finish() { 165 std::string S; 166 getPALMetadata()->toString(S); 167 OS << S; 168 } 169 170 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) { 171 OS << "\t.amdgcn_target \"" << Target << "\"\n"; 172 } 173 174 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 175 uint32_t Major, uint32_t Minor) { 176 OS << "\t.hsa_code_object_version " << 177 Twine(Major) << "," << Twine(Minor) << '\n'; 178 } 179 180 void 181 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 182 uint32_t Minor, 183 uint32_t Stepping, 184 StringRef VendorName, 185 StringRef ArchName) { 186 OS << "\t.hsa_code_object_isa " << 187 Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) << 188 ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 189 190 } 191 192 void 193 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 194 OS << "\t.amd_kernel_code_t\n"; 195 dumpAmdKernelCode(&Header, OS, "\t\t"); 196 OS << "\t.end_amd_kernel_code_t\n"; 197 } 198 199 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 200 unsigned Type) { 201 switch (Type) { 202 default: llvm_unreachable("Invalid AMDGPU symbol type"); 203 case ELF::STT_AMDGPU_HSA_KERNEL: 204 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 205 break; 206 } 207 } 208 209 bool AMDGPUTargetAsmStreamer::EmitISAVersion(StringRef IsaVersionString) { 210 OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n"; 211 return true; 212 } 213 214 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 215 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 216 std::string HSAMetadataString; 217 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 218 return false; 219 220 OS << '\t' << AssemblerDirectiveBegin << '\n'; 221 OS << HSAMetadataString << '\n'; 222 OS << '\t' << AssemblerDirectiveEnd << '\n'; 223 return true; 224 } 225 226 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 227 msgpack::Document &HSAMetadataDoc, bool Strict) { 228 V3::MetadataVerifier Verifier(Strict); 229 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 230 return false; 231 232 std::string HSAMetadataString; 233 raw_string_ostream StrOS(HSAMetadataString); 234 HSAMetadataDoc.toYAML(StrOS); 235 236 OS << '\t' << V3::AssemblerDirectiveBegin << '\n'; 237 OS << StrOS.str() << '\n'; 238 OS << '\t' << V3::AssemblerDirectiveEnd << '\n'; 239 return true; 240 } 241 242 bool AMDGPUTargetAsmStreamer::EmitCodeEnd() { 243 const uint32_t Encoded_s_code_end = 0xbf9f0000; 244 OS << "\t.p2alignl 6, " << Encoded_s_code_end << '\n'; 245 OS << "\t.fill 32, 4, " << Encoded_s_code_end << '\n'; 246 return true; 247 } 248 249 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 250 const MCSubtargetInfo &STI, StringRef KernelName, 251 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 252 bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) { 253 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 254 255 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 256 257 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 258 STREAM << "\t\t" << DIRECTIVE << " " \ 259 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 260 261 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 262 << '\n'; 263 OS << "\t\t.amdhsa_private_segment_fixed_size " 264 << KD.private_segment_fixed_size << '\n'; 265 266 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 267 kernel_code_properties, 268 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 269 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 270 kernel_code_properties, 271 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 272 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 273 kernel_code_properties, 274 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 275 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 276 kernel_code_properties, 277 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 278 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 279 kernel_code_properties, 280 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 281 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 282 kernel_code_properties, 283 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 284 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 285 kernel_code_properties, 286 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 287 if (IVersion.Major >= 10) 288 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 289 kernel_code_properties, 290 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 291 PRINT_FIELD( 292 OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, 293 compute_pgm_rsrc2, 294 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET); 295 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 296 compute_pgm_rsrc2, 297 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 298 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 299 compute_pgm_rsrc2, 300 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 301 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 302 compute_pgm_rsrc2, 303 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 304 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 305 compute_pgm_rsrc2, 306 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 307 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 308 compute_pgm_rsrc2, 309 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 310 311 // These directives are required. 312 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 313 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 314 315 if (!ReserveVCC) 316 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 317 if (IVersion.Major >= 7 && !ReserveFlatScr) 318 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 319 if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI)) 320 OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n'; 321 322 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 323 compute_pgm_rsrc1, 324 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 325 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 326 compute_pgm_rsrc1, 327 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 328 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 329 compute_pgm_rsrc1, 330 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 331 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 332 compute_pgm_rsrc1, 333 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 334 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 335 compute_pgm_rsrc1, 336 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 337 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 338 compute_pgm_rsrc1, 339 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 340 if (IVersion.Major >= 9) 341 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 342 compute_pgm_rsrc1, 343 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 344 if (IVersion.Major >= 10) { 345 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 346 compute_pgm_rsrc1, 347 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 348 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 349 compute_pgm_rsrc1, 350 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 351 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 352 compute_pgm_rsrc1, 353 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 354 } 355 PRINT_FIELD( 356 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 357 compute_pgm_rsrc2, 358 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 359 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 360 compute_pgm_rsrc2, 361 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 362 PRINT_FIELD( 363 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 364 compute_pgm_rsrc2, 365 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 366 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 367 compute_pgm_rsrc2, 368 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 369 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 370 compute_pgm_rsrc2, 371 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 372 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 373 compute_pgm_rsrc2, 374 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 375 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 376 compute_pgm_rsrc2, 377 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 378 #undef PRINT_FIELD 379 380 OS << "\t.end_amdhsa_kernel\n"; 381 } 382 383 //===----------------------------------------------------------------------===// 384 // AMDGPUTargetELFStreamer 385 //===----------------------------------------------------------------------===// 386 387 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer( 388 MCStreamer &S, const MCSubtargetInfo &STI) 389 : AMDGPUTargetStreamer(S), Streamer(S) { 390 MCAssembler &MCA = getStreamer().getAssembler(); 391 unsigned EFlags = MCA.getELFHeaderEFlags(); 392 393 EFlags &= ~ELF::EF_AMDGPU_MACH; 394 EFlags |= getElfMach(STI.getCPU()); 395 396 EFlags &= ~ELF::EF_AMDGPU_XNACK; 397 if (AMDGPU::hasXNACK(STI)) 398 EFlags |= ELF::EF_AMDGPU_XNACK; 399 400 EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC; 401 if (AMDGPU::hasSRAMECC(STI)) 402 EFlags |= ELF::EF_AMDGPU_SRAM_ECC; 403 404 MCA.setELFHeaderEFlags(EFlags); 405 } 406 407 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 408 return static_cast<MCELFStreamer &>(Streamer); 409 } 410 411 // A hook for emitting stuff at the end. 412 // We use it for emitting the accumulated PAL metadata as a .note record. 413 void AMDGPUTargetELFStreamer::finish() { 414 std::string Blob; 415 const char *Vendor = getPALMetadata()->getVendor(); 416 unsigned Type = getPALMetadata()->getType(); 417 getPALMetadata()->toBlob(Type, Blob); 418 if (Blob.empty()) 419 return; 420 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 421 [&](MCELFStreamer &OS) { OS.EmitBytes(Blob); }); 422 } 423 424 void AMDGPUTargetELFStreamer::EmitNote( 425 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 426 function_ref<void(MCELFStreamer &)> EmitDesc) { 427 auto &S = getStreamer(); 428 auto &Context = S.getContext(); 429 430 auto NameSZ = Name.size() + 1; 431 432 S.PushSection(); 433 S.SwitchSection(Context.getELFSection( 434 ElfNote::SectionName, ELF::SHT_NOTE, ELF::SHF_ALLOC)); 435 S.EmitIntValue(NameSZ, 4); // namesz 436 S.EmitValue(DescSZ, 4); // descz 437 S.EmitIntValue(NoteType, 4); // type 438 S.EmitBytes(Name); // name 439 S.EmitValueToAlignment(4, 0, 1, 0); // padding 0 440 EmitDesc(S); // desc 441 S.EmitValueToAlignment(4, 0, 1, 0); // padding 0 442 S.PopSection(); 443 } 444 445 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {} 446 447 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 448 uint32_t Major, uint32_t Minor) { 449 450 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 451 ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 452 OS.EmitIntValue(Major, 4); 453 OS.EmitIntValue(Minor, 4); 454 }); 455 } 456 457 void 458 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 459 uint32_t Minor, 460 uint32_t Stepping, 461 StringRef VendorName, 462 StringRef ArchName) { 463 uint16_t VendorNameSize = VendorName.size() + 1; 464 uint16_t ArchNameSize = ArchName.size() + 1; 465 466 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 467 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 468 VendorNameSize + ArchNameSize; 469 470 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 471 ElfNote::NT_AMDGPU_HSA_ISA, [&](MCELFStreamer &OS) { 472 OS.EmitIntValue(VendorNameSize, 2); 473 OS.EmitIntValue(ArchNameSize, 2); 474 OS.EmitIntValue(Major, 4); 475 OS.EmitIntValue(Minor, 4); 476 OS.EmitIntValue(Stepping, 4); 477 OS.EmitBytes(VendorName); 478 OS.EmitIntValue(0, 1); // NULL terminate VendorName 479 OS.EmitBytes(ArchName); 480 OS.EmitIntValue(0, 1); // NULL terminte ArchName 481 }); 482 } 483 484 void 485 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 486 487 MCStreamer &OS = getStreamer(); 488 OS.PushSection(); 489 OS.EmitBytes(StringRef((const char*)&Header, sizeof(Header))); 490 OS.PopSection(); 491 } 492 493 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 494 unsigned Type) { 495 MCSymbolELF *Symbol = cast<MCSymbolELF>( 496 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 497 Symbol->setType(Type); 498 } 499 500 bool AMDGPUTargetELFStreamer::EmitISAVersion(StringRef IsaVersionString) { 501 // Create two labels to mark the beginning and end of the desc field 502 // and a MCExpr to calculate the size of the desc field. 503 auto &Context = getContext(); 504 auto *DescBegin = Context.createTempSymbol(); 505 auto *DescEnd = Context.createTempSymbol(); 506 auto *DescSZ = MCBinaryExpr::createSub( 507 MCSymbolRefExpr::create(DescEnd, Context), 508 MCSymbolRefExpr::create(DescBegin, Context), Context); 509 510 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_ISA, 511 [&](MCELFStreamer &OS) { 512 OS.EmitLabel(DescBegin); 513 OS.EmitBytes(IsaVersionString); 514 OS.EmitLabel(DescEnd); 515 }); 516 return true; 517 } 518 519 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 520 bool Strict) { 521 V3::MetadataVerifier Verifier(Strict); 522 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 523 return false; 524 525 std::string HSAMetadataString; 526 HSAMetadataDoc.writeToBlob(HSAMetadataString); 527 528 // Create two labels to mark the beginning and end of the desc field 529 // and a MCExpr to calculate the size of the desc field. 530 auto &Context = getContext(); 531 auto *DescBegin = Context.createTempSymbol(); 532 auto *DescEnd = Context.createTempSymbol(); 533 auto *DescSZ = MCBinaryExpr::createSub( 534 MCSymbolRefExpr::create(DescEnd, Context), 535 MCSymbolRefExpr::create(DescBegin, Context), Context); 536 537 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 538 [&](MCELFStreamer &OS) { 539 OS.EmitLabel(DescBegin); 540 OS.EmitBytes(HSAMetadataString); 541 OS.EmitLabel(DescEnd); 542 }); 543 return true; 544 } 545 546 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 547 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 548 std::string HSAMetadataString; 549 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 550 return false; 551 552 // Create two labels to mark the beginning and end of the desc field 553 // and a MCExpr to calculate the size of the desc field. 554 auto &Context = getContext(); 555 auto *DescBegin = Context.createTempSymbol(); 556 auto *DescEnd = Context.createTempSymbol(); 557 auto *DescSZ = MCBinaryExpr::createSub( 558 MCSymbolRefExpr::create(DescEnd, Context), 559 MCSymbolRefExpr::create(DescBegin, Context), Context); 560 561 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_HSA_METADATA, 562 [&](MCELFStreamer &OS) { 563 OS.EmitLabel(DescBegin); 564 OS.EmitBytes(HSAMetadataString); 565 OS.EmitLabel(DescEnd); 566 }); 567 return true; 568 } 569 570 bool AMDGPUTargetELFStreamer::EmitCodeEnd() { 571 const uint32_t Encoded_s_code_end = 0xbf9f0000; 572 573 MCStreamer &OS = getStreamer(); 574 OS.PushSection(); 575 OS.EmitValueToAlignment(64, Encoded_s_code_end, 4); 576 for (unsigned I = 0; I < 32; ++I) 577 OS.EmitIntValue(Encoded_s_code_end, 4); 578 OS.PopSection(); 579 return true; 580 } 581 582 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 583 const MCSubtargetInfo &STI, StringRef KernelName, 584 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 585 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, 586 bool ReserveXNACK) { 587 auto &Streamer = getStreamer(); 588 auto &Context = Streamer.getContext(); 589 590 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 591 Context.getOrCreateSymbol(Twine(KernelName))); 592 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 593 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 594 595 // Copy kernel descriptor symbol's binding, other and visibility from the 596 // kernel code symbol. 597 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 598 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 599 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 600 // Kernel descriptor symbol's type and size are fixed. 601 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 602 KernelDescriptorSymbol->setSize( 603 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 604 605 // The visibility of the kernel code symbol must be protected or less to allow 606 // static relocations from the kernel descriptor to be used. 607 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 608 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 609 610 Streamer.EmitLabel(KernelDescriptorSymbol); 611 Streamer.EmitBytes(StringRef( 612 (const char*)&(KernelDescriptor), 613 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset))); 614 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 615 // expression being created is: 616 // (start of kernel code) - (start of kernel descriptor) 617 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 618 Streamer.EmitValue(MCBinaryExpr::createSub( 619 MCSymbolRefExpr::create( 620 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 621 MCSymbolRefExpr::create( 622 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 623 Context), 624 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 625 Streamer.EmitBytes(StringRef( 626 (const char*)&(KernelDescriptor) + 627 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) + 628 sizeof(KernelDescriptor.kernel_code_entry_byte_offset), 629 sizeof(KernelDescriptor) - 630 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) - 631 sizeof(KernelDescriptor.kernel_code_entry_byte_offset))); 632 } 633