1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPUPTNote.h" 15 #include "AMDKernelCodeT.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCELFStreamer.h" 22 #include "llvm/MC/MCSectionELF.h" 23 #include "llvm/Support/AMDGPUMetadata.h" 24 #include "llvm/Support/AMDHSAKernelDescriptor.h" 25 #include "llvm/Support/FormattedStream.h" 26 27 using namespace llvm; 28 using namespace llvm::AMDGPU; 29 30 //===----------------------------------------------------------------------===// 31 // AMDGPUTargetStreamer 32 //===----------------------------------------------------------------------===// 33 34 static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, 35 uint32_t &Stepping, bool Sramecc, bool Xnack) { 36 if (Major == 9 && Minor == 0) { 37 switch (Stepping) { 38 case 0: 39 case 2: 40 case 4: 41 case 6: 42 if (Xnack) 43 Stepping++; 44 } 45 } 46 } 47 48 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 49 HSAMD::Metadata HSAMetadata; 50 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 51 return false; 52 return EmitHSAMetadata(HSAMetadata); 53 } 54 55 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 56 msgpack::Document HSAMetadataDoc; 57 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 58 return false; 59 return EmitHSAMetadata(HSAMetadataDoc, false); 60 } 61 62 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 63 AMDGPU::GPUKind AK; 64 65 switch (ElfMach) { 66 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type"); 67 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 68 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 69 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 70 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 71 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 72 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 73 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 74 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 75 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 76 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 77 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 78 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 79 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 80 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 81 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 82 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break; 104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break; 105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break; 109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break; 112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break; 113 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break; 114 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 115 } 116 117 StringRef GPUName = getArchNameAMDGCN(AK); 118 if (GPUName != "") 119 return GPUName; 120 return getArchNameR600(AK); 121 } 122 123 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 124 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 125 if (AK == AMDGPU::GPUKind::GK_NONE) 126 AK = parseArchR600(GPU); 127 128 switch (AK) { 129 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 130 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 131 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 132 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 133 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 134 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 135 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 136 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 137 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 138 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 139 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 140 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 141 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 142 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 143 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 144 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 145 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 146 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 147 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602; 148 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 149 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 150 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 151 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 152 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 153 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705; 154 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 155 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 156 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 157 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805; 158 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 159 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 160 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 161 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 162 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 163 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 164 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 165 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A; 166 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C; 167 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 168 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 169 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 170 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013; 171 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 172 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 173 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032; 174 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033; 175 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034; 176 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 177 } 178 179 llvm_unreachable("unknown GPU"); 180 } 181 182 //===----------------------------------------------------------------------===// 183 // AMDGPUTargetAsmStreamer 184 //===----------------------------------------------------------------------===// 185 186 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 187 formatted_raw_ostream &OS) 188 : AMDGPUTargetStreamer(S), OS(OS) { } 189 190 // A hook for emitting stuff at the end. 191 // We use it for emitting the accumulated PAL metadata as directives. 192 // The PAL metadata is reset after it is emitted. 193 void AMDGPUTargetAsmStreamer::finish() { 194 std::string S; 195 getPALMetadata()->toString(S); 196 OS << S; 197 198 // Reset the pal metadata so its data will not affect a compilation that 199 // reuses this object. 200 getPALMetadata()->reset(); 201 } 202 203 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() { 204 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n"; 205 } 206 207 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 208 uint32_t Major, uint32_t Minor) { 209 OS << "\t.hsa_code_object_version " << 210 Twine(Major) << "," << Twine(Minor) << '\n'; 211 } 212 213 void 214 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 215 uint32_t Minor, 216 uint32_t Stepping, 217 StringRef VendorName, 218 StringRef ArchName) { 219 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 220 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << "," 221 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 222 } 223 224 void 225 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 226 OS << "\t.amd_kernel_code_t\n"; 227 dumpAmdKernelCode(&Header, OS, "\t\t"); 228 OS << "\t.end_amd_kernel_code_t\n"; 229 } 230 231 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 232 unsigned Type) { 233 switch (Type) { 234 default: llvm_unreachable("Invalid AMDGPU symbol type"); 235 case ELF::STT_AMDGPU_HSA_KERNEL: 236 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 237 break; 238 } 239 } 240 241 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 242 Align Alignment) { 243 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 244 << Alignment.value() << '\n'; 245 } 246 247 bool AMDGPUTargetAsmStreamer::EmitISAVersion() { 248 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n"; 249 return true; 250 } 251 252 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 253 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 254 std::string HSAMetadataString; 255 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 256 return false; 257 258 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n'; 259 OS << HSAMetadataString << '\n'; 260 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n'; 261 return true; 262 } 263 264 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 265 msgpack::Document &HSAMetadataDoc, bool Strict) { 266 HSAMD::V3::MetadataVerifier Verifier(Strict); 267 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 268 return false; 269 270 std::string HSAMetadataString; 271 raw_string_ostream StrOS(HSAMetadataString); 272 HSAMetadataDoc.toYAML(StrOS); 273 274 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n'; 275 OS << StrOS.str() << '\n'; 276 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n'; 277 return true; 278 } 279 280 bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 281 const uint32_t Encoded_s_code_end = 0xbf9f0000; 282 const uint32_t Encoded_s_nop = 0xbf800000; 283 uint32_t Encoded_pad = Encoded_s_code_end; 284 285 // Instruction cache line size in bytes. 286 const unsigned Log2CacheLineSize = 6; 287 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 288 289 // Extra padding amount in bytes to support prefetch mode 3. 290 unsigned FillSize = 3 * CacheLineSize; 291 292 if (AMDGPU::isGFX90A(STI)) { 293 Encoded_pad = Encoded_s_nop; 294 FillSize = 16 * CacheLineSize; 295 } 296 297 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n'; 298 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n'; 299 return true; 300 } 301 302 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 303 const MCSubtargetInfo &STI, StringRef KernelName, 304 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 305 bool ReserveVCC, bool ReserveFlatScr) { 306 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 307 308 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 309 310 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 311 STREAM << "\t\t" << DIRECTIVE << " " \ 312 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 313 314 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 315 << '\n'; 316 OS << "\t\t.amdhsa_private_segment_fixed_size " 317 << KD.private_segment_fixed_size << '\n'; 318 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n'; 319 320 if (!hasArchitectedFlatScratch(STI)) 321 PRINT_FIELD( 322 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 323 kernel_code_properties, 324 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 325 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 326 kernel_code_properties, 327 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 328 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 329 kernel_code_properties, 330 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 331 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 332 kernel_code_properties, 333 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 334 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 335 kernel_code_properties, 336 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 337 if (!hasArchitectedFlatScratch(STI)) 338 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 339 kernel_code_properties, 340 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 341 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 342 kernel_code_properties, 343 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 344 if (IVersion.Major >= 10) 345 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 346 kernel_code_properties, 347 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 348 PRINT_FIELD(OS, 349 (hasArchitectedFlatScratch(STI) 350 ? ".amdhsa_enable_private_segment" 351 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"), 352 KD, compute_pgm_rsrc2, 353 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 354 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 355 compute_pgm_rsrc2, 356 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 357 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 358 compute_pgm_rsrc2, 359 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 360 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 361 compute_pgm_rsrc2, 362 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 363 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 364 compute_pgm_rsrc2, 365 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 366 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 367 compute_pgm_rsrc2, 368 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 369 370 // These directives are required. 371 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 372 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 373 374 if (AMDGPU::isGFX90A(STI)) 375 OS << "\t\t.amdhsa_accum_offset " << 376 (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3, 377 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 378 << '\n'; 379 380 if (!ReserveVCC) 381 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 382 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI)) 383 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 384 385 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 386 switch (*HsaAbiVer) { 387 default: 388 break; 389 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 390 break; 391 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 392 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 393 if (getTargetID()->isXnackSupported()) 394 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n'; 395 break; 396 } 397 } 398 399 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 400 compute_pgm_rsrc1, 401 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 402 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 403 compute_pgm_rsrc1, 404 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 405 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 406 compute_pgm_rsrc1, 407 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 408 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 409 compute_pgm_rsrc1, 410 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 411 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 412 compute_pgm_rsrc1, 413 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 414 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 415 compute_pgm_rsrc1, 416 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 417 if (IVersion.Major >= 9) 418 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 419 compute_pgm_rsrc1, 420 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 421 if (AMDGPU::isGFX90A(STI)) 422 PRINT_FIELD(OS, ".amdhsa_tg_split", KD, 423 compute_pgm_rsrc3, 424 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 425 if (IVersion.Major >= 10) { 426 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 427 compute_pgm_rsrc1, 428 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 429 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 430 compute_pgm_rsrc1, 431 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 432 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 433 compute_pgm_rsrc1, 434 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 435 } 436 PRINT_FIELD( 437 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 438 compute_pgm_rsrc2, 439 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 440 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 441 compute_pgm_rsrc2, 442 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 443 PRINT_FIELD( 444 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 445 compute_pgm_rsrc2, 446 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 447 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 448 compute_pgm_rsrc2, 449 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 450 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 451 compute_pgm_rsrc2, 452 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 453 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 454 compute_pgm_rsrc2, 455 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 456 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 457 compute_pgm_rsrc2, 458 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 459 #undef PRINT_FIELD 460 461 OS << "\t.end_amdhsa_kernel\n"; 462 } 463 464 //===----------------------------------------------------------------------===// 465 // AMDGPUTargetELFStreamer 466 //===----------------------------------------------------------------------===// 467 468 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 469 const MCSubtargetInfo &STI) 470 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {} 471 472 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 473 return static_cast<MCELFStreamer &>(Streamer); 474 } 475 476 // A hook for emitting stuff at the end. 477 // We use it for emitting the accumulated PAL metadata as a .note record. 478 // The PAL metadata is reset after it is emitted. 479 void AMDGPUTargetELFStreamer::finish() { 480 MCAssembler &MCA = getStreamer().getAssembler(); 481 MCA.setELFHeaderEFlags(getEFlags()); 482 483 std::string Blob; 484 const char *Vendor = getPALMetadata()->getVendor(); 485 unsigned Type = getPALMetadata()->getType(); 486 getPALMetadata()->toBlob(Type, Blob); 487 if (Blob.empty()) 488 return; 489 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 490 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 491 492 // Reset the pal metadata so its data will not affect a compilation that 493 // reuses this object. 494 getPALMetadata()->reset(); 495 } 496 497 void AMDGPUTargetELFStreamer::EmitNote( 498 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 499 function_ref<void(MCELFStreamer &)> EmitDesc) { 500 auto &S = getStreamer(); 501 auto &Context = S.getContext(); 502 503 auto NameSZ = Name.size() + 1; 504 505 unsigned NoteFlags = 0; 506 // TODO Apparently, this is currently needed for OpenCL as mentioned in 507 // https://reviews.llvm.org/D74995 508 if (STI.getTargetTriple().getOS() == Triple::AMDHSA) 509 NoteFlags = ELF::SHF_ALLOC; 510 511 S.PushSection(); 512 S.SwitchSection( 513 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 514 S.emitInt32(NameSZ); // namesz 515 S.emitValue(DescSZ, 4); // descz 516 S.emitInt32(NoteType); // type 517 S.emitBytes(Name); // name 518 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 519 EmitDesc(S); // desc 520 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 521 S.PopSection(); 522 } 523 524 unsigned AMDGPUTargetELFStreamer::getEFlags() { 525 switch (STI.getTargetTriple().getArch()) { 526 default: 527 llvm_unreachable("Unsupported Arch"); 528 case Triple::r600: 529 return getEFlagsR600(); 530 case Triple::amdgcn: 531 return getEFlagsAMDGCN(); 532 } 533 } 534 535 unsigned AMDGPUTargetELFStreamer::getEFlagsR600() { 536 assert(STI.getTargetTriple().getArch() == Triple::r600); 537 538 return getElfMach(STI.getCPU()); 539 } 540 541 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() { 542 assert(STI.getTargetTriple().getArch() == Triple::amdgcn); 543 544 switch (STI.getTargetTriple().getOS()) { 545 default: 546 // TODO: Why are some tests have "mingw" listed as OS? 547 // llvm_unreachable("Unsupported OS"); 548 case Triple::UnknownOS: 549 return getEFlagsUnknownOS(); 550 case Triple::AMDHSA: 551 return getEFlagsAMDHSA(); 552 case Triple::AMDPAL: 553 return getEFlagsAMDPAL(); 554 case Triple::Mesa3D: 555 return getEFlagsMesa3D(); 556 } 557 } 558 559 unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() { 560 // TODO: Why are some tests have "mingw" listed as OS? 561 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS); 562 563 return getEFlagsV3(); 564 } 565 566 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() { 567 assert(STI.getTargetTriple().getOS() == Triple::AMDHSA); 568 569 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 570 switch (*HsaAbiVer) { 571 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 572 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 573 return getEFlagsV3(); 574 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 575 return getEFlagsV4(); 576 } 577 } 578 579 llvm_unreachable("HSA OS ABI Version identification must be defined"); 580 } 581 582 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() { 583 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL); 584 585 return getEFlagsV3(); 586 } 587 588 unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() { 589 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D); 590 591 return getEFlagsV3(); 592 } 593 594 unsigned AMDGPUTargetELFStreamer::getEFlagsV3() { 595 unsigned EFlagsV3 = 0; 596 597 // mach. 598 EFlagsV3 |= getElfMach(STI.getCPU()); 599 600 // xnack. 601 if (getTargetID()->isXnackOnOrAny()) 602 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3; 603 // sramecc. 604 if (getTargetID()->isSramEccOnOrAny()) 605 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3; 606 607 return EFlagsV3; 608 } 609 610 unsigned AMDGPUTargetELFStreamer::getEFlagsV4() { 611 unsigned EFlagsV4 = 0; 612 613 // mach. 614 EFlagsV4 |= getElfMach(STI.getCPU()); 615 616 // xnack. 617 switch (getTargetID()->getXnackSetting()) { 618 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 619 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4; 620 break; 621 case AMDGPU::IsaInfo::TargetIDSetting::Any: 622 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4; 623 break; 624 case AMDGPU::IsaInfo::TargetIDSetting::Off: 625 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4; 626 break; 627 case AMDGPU::IsaInfo::TargetIDSetting::On: 628 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4; 629 break; 630 } 631 // sramecc. 632 switch (getTargetID()->getSramEccSetting()) { 633 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 634 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4; 635 break; 636 case AMDGPU::IsaInfo::TargetIDSetting::Any: 637 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4; 638 break; 639 case AMDGPU::IsaInfo::TargetIDSetting::Off: 640 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4; 641 break; 642 case AMDGPU::IsaInfo::TargetIDSetting::On: 643 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4; 644 break; 645 } 646 647 return EFlagsV4; 648 } 649 650 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {} 651 652 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 653 uint32_t Major, uint32_t Minor) { 654 655 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 656 ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 657 OS.emitInt32(Major); 658 OS.emitInt32(Minor); 659 }); 660 } 661 662 void 663 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 664 uint32_t Minor, 665 uint32_t Stepping, 666 StringRef VendorName, 667 StringRef ArchName) { 668 uint16_t VendorNameSize = VendorName.size() + 1; 669 uint16_t ArchNameSize = ArchName.size() + 1; 670 671 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 672 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 673 VendorNameSize + ArchNameSize; 674 675 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 676 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 677 ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) { 678 OS.emitInt16(VendorNameSize); 679 OS.emitInt16(ArchNameSize); 680 OS.emitInt32(Major); 681 OS.emitInt32(Minor); 682 OS.emitInt32(Stepping); 683 OS.emitBytes(VendorName); 684 OS.emitInt8(0); // NULL terminate VendorName 685 OS.emitBytes(ArchName); 686 OS.emitInt8(0); // NULL terminte ArchName 687 }); 688 } 689 690 void 691 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 692 693 MCStreamer &OS = getStreamer(); 694 OS.PushSection(); 695 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 696 OS.PopSection(); 697 } 698 699 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 700 unsigned Type) { 701 MCSymbolELF *Symbol = cast<MCSymbolELF>( 702 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 703 Symbol->setType(Type); 704 } 705 706 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 707 Align Alignment) { 708 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 709 SymbolELF->setType(ELF::STT_OBJECT); 710 711 if (!SymbolELF->isBindingSet()) { 712 SymbolELF->setBinding(ELF::STB_GLOBAL); 713 SymbolELF->setExternal(true); 714 } 715 716 if (SymbolELF->declareCommon(Size, Alignment.value(), true)) { 717 report_fatal_error("Symbol: " + Symbol->getName() + 718 " redeclared as different type"); 719 } 720 721 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 722 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 723 } 724 725 bool AMDGPUTargetELFStreamer::EmitISAVersion() { 726 // Create two labels to mark the beginning and end of the desc field 727 // and a MCExpr to calculate the size of the desc field. 728 auto &Context = getContext(); 729 auto *DescBegin = Context.createTempSymbol(); 730 auto *DescEnd = Context.createTempSymbol(); 731 auto *DescSZ = MCBinaryExpr::createSub( 732 MCSymbolRefExpr::create(DescEnd, Context), 733 MCSymbolRefExpr::create(DescBegin, Context), Context); 734 735 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME, 736 [&](MCELFStreamer &OS) { 737 OS.emitLabel(DescBegin); 738 OS.emitBytes(getTargetID()->toString()); 739 OS.emitLabel(DescEnd); 740 }); 741 return true; 742 } 743 744 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 745 bool Strict) { 746 HSAMD::V3::MetadataVerifier Verifier(Strict); 747 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 748 return false; 749 750 std::string HSAMetadataString; 751 HSAMetadataDoc.writeToBlob(HSAMetadataString); 752 753 // Create two labels to mark the beginning and end of the desc field 754 // and a MCExpr to calculate the size of the desc field. 755 auto &Context = getContext(); 756 auto *DescBegin = Context.createTempSymbol(); 757 auto *DescEnd = Context.createTempSymbol(); 758 auto *DescSZ = MCBinaryExpr::createSub( 759 MCSymbolRefExpr::create(DescEnd, Context), 760 MCSymbolRefExpr::create(DescBegin, Context), Context); 761 762 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 763 [&](MCELFStreamer &OS) { 764 OS.emitLabel(DescBegin); 765 OS.emitBytes(HSAMetadataString); 766 OS.emitLabel(DescEnd); 767 }); 768 return true; 769 } 770 771 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 772 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 773 std::string HSAMetadataString; 774 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 775 return false; 776 777 // Create two labels to mark the beginning and end of the desc field 778 // and a MCExpr to calculate the size of the desc field. 779 auto &Context = getContext(); 780 auto *DescBegin = Context.createTempSymbol(); 781 auto *DescEnd = Context.createTempSymbol(); 782 auto *DescSZ = MCBinaryExpr::createSub( 783 MCSymbolRefExpr::create(DescEnd, Context), 784 MCSymbolRefExpr::create(DescBegin, Context), Context); 785 786 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA, 787 [&](MCELFStreamer &OS) { 788 OS.emitLabel(DescBegin); 789 OS.emitBytes(HSAMetadataString); 790 OS.emitLabel(DescEnd); 791 }); 792 return true; 793 } 794 795 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 796 const uint32_t Encoded_s_code_end = 0xbf9f0000; 797 const uint32_t Encoded_s_nop = 0xbf800000; 798 uint32_t Encoded_pad = Encoded_s_code_end; 799 800 // Instruction cache line size in bytes. 801 const unsigned Log2CacheLineSize = 6; 802 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 803 804 // Extra padding amount in bytes to support prefetch mode 3. 805 unsigned FillSize = 3 * CacheLineSize; 806 807 if (AMDGPU::isGFX90A(STI)) { 808 Encoded_pad = Encoded_s_nop; 809 FillSize = 16 * CacheLineSize; 810 } 811 812 MCStreamer &OS = getStreamer(); 813 OS.PushSection(); 814 OS.emitValueToAlignment(CacheLineSize, Encoded_pad, 4); 815 for (unsigned I = 0; I < FillSize; I += 4) 816 OS.emitInt32(Encoded_pad); 817 OS.PopSection(); 818 return true; 819 } 820 821 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 822 const MCSubtargetInfo &STI, StringRef KernelName, 823 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 824 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) { 825 auto &Streamer = getStreamer(); 826 auto &Context = Streamer.getContext(); 827 828 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 829 Context.getOrCreateSymbol(Twine(KernelName))); 830 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 831 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 832 833 // Copy kernel descriptor symbol's binding, other and visibility from the 834 // kernel code symbol. 835 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 836 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 837 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 838 // Kernel descriptor symbol's type and size are fixed. 839 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 840 KernelDescriptorSymbol->setSize( 841 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 842 843 // The visibility of the kernel code symbol must be protected or less to allow 844 // static relocations from the kernel descriptor to be used. 845 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 846 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 847 848 Streamer.emitLabel(KernelDescriptorSymbol); 849 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size); 850 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size); 851 Streamer.emitInt32(KernelDescriptor.kernarg_size); 852 853 for (uint8_t Res : KernelDescriptor.reserved0) 854 Streamer.emitInt8(Res); 855 856 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 857 // expression being created is: 858 // (start of kernel code) - (start of kernel descriptor) 859 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 860 Streamer.emitValue(MCBinaryExpr::createSub( 861 MCSymbolRefExpr::create( 862 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 863 MCSymbolRefExpr::create( 864 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 865 Context), 866 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 867 for (uint8_t Res : KernelDescriptor.reserved1) 868 Streamer.emitInt8(Res); 869 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3); 870 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1); 871 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2); 872 Streamer.emitInt16(KernelDescriptor.kernel_code_properties); 873 for (uint8_t Res : KernelDescriptor.reserved2) 874 Streamer.emitInt8(Res); 875 } 876