1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPUPTNote.h" 15 #include "AMDKernelCodeT.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCELFStreamer.h" 22 #include "llvm/MC/MCSectionELF.h" 23 #include "llvm/Support/AMDGPUMetadata.h" 24 #include "llvm/Support/AMDHSAKernelDescriptor.h" 25 #include "llvm/Support/FormattedStream.h" 26 27 using namespace llvm; 28 using namespace llvm::AMDGPU; 29 30 //===----------------------------------------------------------------------===// 31 // AMDGPUTargetStreamer 32 //===----------------------------------------------------------------------===// 33 34 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 35 HSAMD::Metadata HSAMetadata; 36 if (HSAMD::fromString(std::string(HSAMetadataString), HSAMetadata)) 37 return false; 38 39 return EmitHSAMetadata(HSAMetadata); 40 } 41 42 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 43 msgpack::Document HSAMetadataDoc; 44 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 45 return false; 46 return EmitHSAMetadata(HSAMetadataDoc, false); 47 } 48 49 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 50 AMDGPU::GPUKind AK; 51 52 switch (ElfMach) { 53 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type"); 54 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 55 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 56 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 57 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 58 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 59 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 60 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 61 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 62 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 63 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 64 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 65 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 66 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 67 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 68 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 69 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 70 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 71 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 72 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break; 73 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 74 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 75 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 76 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 77 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 78 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break; 79 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 80 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 81 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 82 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break; 98 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 99 } 100 101 StringRef GPUName = getArchNameAMDGCN(AK); 102 if (GPUName != "") 103 return GPUName; 104 return getArchNameR600(AK); 105 } 106 107 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 108 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 109 if (AK == AMDGPU::GPUKind::GK_NONE) 110 AK = parseArchR600(GPU); 111 112 switch (AK) { 113 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 114 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 115 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 116 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 117 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 118 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 119 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 120 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 121 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 122 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 123 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 124 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 125 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 126 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 127 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 128 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 129 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 130 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 131 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602; 132 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 133 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 134 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 135 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 136 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 137 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705; 138 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 139 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 140 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 141 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805; 142 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 143 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 144 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 145 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 146 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 147 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 148 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 149 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C; 150 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 151 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 152 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 153 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 154 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 155 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032; 156 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033; 157 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 158 } 159 160 llvm_unreachable("unknown GPU"); 161 } 162 163 //===----------------------------------------------------------------------===// 164 // AMDGPUTargetAsmStreamer 165 //===----------------------------------------------------------------------===// 166 167 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 168 formatted_raw_ostream &OS) 169 : AMDGPUTargetStreamer(S), OS(OS) { } 170 171 // A hook for emitting stuff at the end. 172 // We use it for emitting the accumulated PAL metadata as directives. 173 // The PAL metadata is reset after it is emitted. 174 void AMDGPUTargetAsmStreamer::finish() { 175 std::string S; 176 getPALMetadata()->toString(S); 177 OS << S; 178 179 // Reset the pal metadata so its data will not affect a compilation that 180 // reuses this object. 181 getPALMetadata()->reset(); 182 } 183 184 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) { 185 OS << "\t.amdgcn_target \"" << Target << "\"\n"; 186 } 187 188 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 189 uint32_t Major, uint32_t Minor) { 190 OS << "\t.hsa_code_object_version " << 191 Twine(Major) << "," << Twine(Minor) << '\n'; 192 } 193 194 void 195 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 196 uint32_t Minor, 197 uint32_t Stepping, 198 StringRef VendorName, 199 StringRef ArchName) { 200 OS << "\t.hsa_code_object_isa " << 201 Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) << 202 ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 203 204 } 205 206 void 207 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 208 OS << "\t.amd_kernel_code_t\n"; 209 dumpAmdKernelCode(&Header, OS, "\t\t"); 210 OS << "\t.end_amd_kernel_code_t\n"; 211 } 212 213 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 214 unsigned Type) { 215 switch (Type) { 216 default: llvm_unreachable("Invalid AMDGPU symbol type"); 217 case ELF::STT_AMDGPU_HSA_KERNEL: 218 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 219 break; 220 } 221 } 222 223 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 224 Align Alignment) { 225 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 226 << Alignment.value() << '\n'; 227 } 228 229 bool AMDGPUTargetAsmStreamer::EmitISAVersion(StringRef IsaVersionString) { 230 OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n"; 231 return true; 232 } 233 234 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 235 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 236 std::string HSAMetadataString; 237 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 238 return false; 239 240 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n'; 241 OS << HSAMetadataString << '\n'; 242 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n'; 243 return true; 244 } 245 246 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 247 msgpack::Document &HSAMetadataDoc, bool Strict) { 248 HSAMD::V3::MetadataVerifier Verifier(Strict); 249 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 250 return false; 251 252 std::string HSAMetadataString; 253 raw_string_ostream StrOS(HSAMetadataString); 254 HSAMetadataDoc.toYAML(StrOS); 255 256 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n'; 257 OS << StrOS.str() << '\n'; 258 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n'; 259 return true; 260 } 261 262 bool AMDGPUTargetAsmStreamer::EmitCodeEnd() { 263 const uint32_t Encoded_s_code_end = 0xbf9f0000; 264 OS << "\t.p2alignl 6, " << Encoded_s_code_end << '\n'; 265 OS << "\t.fill 48, 4, " << Encoded_s_code_end << '\n'; 266 return true; 267 } 268 269 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 270 const MCSubtargetInfo &STI, StringRef KernelName, 271 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 272 bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) { 273 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 274 275 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 276 277 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 278 STREAM << "\t\t" << DIRECTIVE << " " \ 279 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 280 281 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 282 << '\n'; 283 OS << "\t\t.amdhsa_private_segment_fixed_size " 284 << KD.private_segment_fixed_size << '\n'; 285 286 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 287 kernel_code_properties, 288 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 289 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 290 kernel_code_properties, 291 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 292 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 293 kernel_code_properties, 294 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 295 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 296 kernel_code_properties, 297 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 298 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 299 kernel_code_properties, 300 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 301 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 302 kernel_code_properties, 303 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 304 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 305 kernel_code_properties, 306 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 307 if (IVersion.Major >= 10) 308 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 309 kernel_code_properties, 310 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 311 PRINT_FIELD( 312 OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, 313 compute_pgm_rsrc2, 314 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 315 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 316 compute_pgm_rsrc2, 317 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 318 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 319 compute_pgm_rsrc2, 320 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 321 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 322 compute_pgm_rsrc2, 323 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 324 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 325 compute_pgm_rsrc2, 326 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 327 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 328 compute_pgm_rsrc2, 329 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 330 331 // These directives are required. 332 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 333 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 334 335 if (!ReserveVCC) 336 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 337 if (IVersion.Major >= 7 && !ReserveFlatScr) 338 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 339 if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI)) 340 OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n'; 341 342 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 343 compute_pgm_rsrc1, 344 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 345 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 346 compute_pgm_rsrc1, 347 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 348 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 349 compute_pgm_rsrc1, 350 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 351 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 352 compute_pgm_rsrc1, 353 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 354 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 355 compute_pgm_rsrc1, 356 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 357 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 358 compute_pgm_rsrc1, 359 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 360 if (IVersion.Major >= 9) 361 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 362 compute_pgm_rsrc1, 363 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 364 if (IVersion.Major >= 10) { 365 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 366 compute_pgm_rsrc1, 367 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 368 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 369 compute_pgm_rsrc1, 370 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 371 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 372 compute_pgm_rsrc1, 373 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 374 } 375 PRINT_FIELD( 376 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 377 compute_pgm_rsrc2, 378 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 379 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 380 compute_pgm_rsrc2, 381 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 382 PRINT_FIELD( 383 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 384 compute_pgm_rsrc2, 385 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 386 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 387 compute_pgm_rsrc2, 388 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 389 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 390 compute_pgm_rsrc2, 391 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 392 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 393 compute_pgm_rsrc2, 394 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 395 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 396 compute_pgm_rsrc2, 397 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 398 #undef PRINT_FIELD 399 400 OS << "\t.end_amdhsa_kernel\n"; 401 } 402 403 //===----------------------------------------------------------------------===// 404 // AMDGPUTargetELFStreamer 405 //===----------------------------------------------------------------------===// 406 407 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 408 const MCSubtargetInfo &STI) 409 : AMDGPUTargetStreamer(S), Streamer(S), Os(STI.getTargetTriple().getOS()) { 410 MCAssembler &MCA = getStreamer().getAssembler(); 411 unsigned EFlags = MCA.getELFHeaderEFlags(); 412 413 EFlags &= ~ELF::EF_AMDGPU_MACH; 414 EFlags |= getElfMach(STI.getCPU()); 415 416 EFlags &= ~ELF::EF_AMDGPU_XNACK; 417 if (AMDGPU::hasXNACK(STI)) 418 EFlags |= ELF::EF_AMDGPU_XNACK; 419 420 EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC; 421 if (AMDGPU::hasSRAMECC(STI)) 422 EFlags |= ELF::EF_AMDGPU_SRAM_ECC; 423 424 MCA.setELFHeaderEFlags(EFlags); 425 } 426 427 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 428 return static_cast<MCELFStreamer &>(Streamer); 429 } 430 431 // A hook for emitting stuff at the end. 432 // We use it for emitting the accumulated PAL metadata as a .note record. 433 // The PAL metadata is reset after it is emitted. 434 void AMDGPUTargetELFStreamer::finish() { 435 std::string Blob; 436 const char *Vendor = getPALMetadata()->getVendor(); 437 unsigned Type = getPALMetadata()->getType(); 438 getPALMetadata()->toBlob(Type, Blob); 439 if (Blob.empty()) 440 return; 441 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 442 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 443 444 // Reset the pal metadata so its data will not affect a compilation that 445 // reuses this object. 446 getPALMetadata()->reset(); 447 } 448 449 void AMDGPUTargetELFStreamer::EmitNote( 450 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 451 function_ref<void(MCELFStreamer &)> EmitDesc) { 452 auto &S = getStreamer(); 453 auto &Context = S.getContext(); 454 455 auto NameSZ = Name.size() + 1; 456 457 unsigned NoteFlags = 0; 458 // TODO Apparently, this is currently needed for OpenCL as mentioned in 459 // https://reviews.llvm.org/D74995 460 if (Os == Triple::AMDHSA) 461 NoteFlags = ELF::SHF_ALLOC; 462 463 S.PushSection(); 464 S.SwitchSection( 465 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 466 S.emitInt32(NameSZ); // namesz 467 S.emitValue(DescSZ, 4); // descz 468 S.emitInt32(NoteType); // type 469 S.emitBytes(Name); // name 470 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 471 EmitDesc(S); // desc 472 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 473 S.PopSection(); 474 } 475 476 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {} 477 478 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 479 uint32_t Major, uint32_t Minor) { 480 481 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 482 ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 483 OS.emitInt32(Major); 484 OS.emitInt32(Minor); 485 }); 486 } 487 488 void 489 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 490 uint32_t Minor, 491 uint32_t Stepping, 492 StringRef VendorName, 493 StringRef ArchName) { 494 uint16_t VendorNameSize = VendorName.size() + 1; 495 uint16_t ArchNameSize = ArchName.size() + 1; 496 497 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 498 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 499 VendorNameSize + ArchNameSize; 500 501 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 502 ElfNote::NT_AMDGPU_HSA_ISA, [&](MCELFStreamer &OS) { 503 OS.emitInt16(VendorNameSize); 504 OS.emitInt16(ArchNameSize); 505 OS.emitInt32(Major); 506 OS.emitInt32(Minor); 507 OS.emitInt32(Stepping); 508 OS.emitBytes(VendorName); 509 OS.emitInt8(0); // NULL terminate VendorName 510 OS.emitBytes(ArchName); 511 OS.emitInt8(0); // NULL terminte ArchName 512 }); 513 } 514 515 void 516 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 517 518 MCStreamer &OS = getStreamer(); 519 OS.PushSection(); 520 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 521 OS.PopSection(); 522 } 523 524 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 525 unsigned Type) { 526 MCSymbolELF *Symbol = cast<MCSymbolELF>( 527 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 528 Symbol->setType(Type); 529 } 530 531 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 532 Align Alignment) { 533 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 534 SymbolELF->setType(ELF::STT_OBJECT); 535 536 if (!SymbolELF->isBindingSet()) { 537 SymbolELF->setBinding(ELF::STB_GLOBAL); 538 SymbolELF->setExternal(true); 539 } 540 541 if (SymbolELF->declareCommon(Size, Alignment.value(), true)) { 542 report_fatal_error("Symbol: " + Symbol->getName() + 543 " redeclared as different type"); 544 } 545 546 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 547 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 548 } 549 550 bool AMDGPUTargetELFStreamer::EmitISAVersion(StringRef IsaVersionString) { 551 // Create two labels to mark the beginning and end of the desc field 552 // and a MCExpr to calculate the size of the desc field. 553 auto &Context = getContext(); 554 auto *DescBegin = Context.createTempSymbol(); 555 auto *DescEnd = Context.createTempSymbol(); 556 auto *DescSZ = MCBinaryExpr::createSub( 557 MCSymbolRefExpr::create(DescEnd, Context), 558 MCSymbolRefExpr::create(DescBegin, Context), Context); 559 560 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_ISA, 561 [&](MCELFStreamer &OS) { 562 OS.emitLabel(DescBegin); 563 OS.emitBytes(IsaVersionString); 564 OS.emitLabel(DescEnd); 565 }); 566 return true; 567 } 568 569 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 570 bool Strict) { 571 HSAMD::V3::MetadataVerifier Verifier(Strict); 572 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 573 return false; 574 575 std::string HSAMetadataString; 576 HSAMetadataDoc.writeToBlob(HSAMetadataString); 577 578 // Create two labels to mark the beginning and end of the desc field 579 // and a MCExpr to calculate the size of the desc field. 580 auto &Context = getContext(); 581 auto *DescBegin = Context.createTempSymbol(); 582 auto *DescEnd = Context.createTempSymbol(); 583 auto *DescSZ = MCBinaryExpr::createSub( 584 MCSymbolRefExpr::create(DescEnd, Context), 585 MCSymbolRefExpr::create(DescBegin, Context), Context); 586 587 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 588 [&](MCELFStreamer &OS) { 589 OS.emitLabel(DescBegin); 590 OS.emitBytes(HSAMetadataString); 591 OS.emitLabel(DescEnd); 592 }); 593 return true; 594 } 595 596 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 597 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 598 std::string HSAMetadataString; 599 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 600 return false; 601 602 // Create two labels to mark the beginning and end of the desc field 603 // and a MCExpr to calculate the size of the desc field. 604 auto &Context = getContext(); 605 auto *DescBegin = Context.createTempSymbol(); 606 auto *DescEnd = Context.createTempSymbol(); 607 auto *DescSZ = MCBinaryExpr::createSub( 608 MCSymbolRefExpr::create(DescEnd, Context), 609 MCSymbolRefExpr::create(DescBegin, Context), Context); 610 611 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_HSA_METADATA, 612 [&](MCELFStreamer &OS) { 613 OS.emitLabel(DescBegin); 614 OS.emitBytes(HSAMetadataString); 615 OS.emitLabel(DescEnd); 616 }); 617 return true; 618 } 619 620 bool AMDGPUTargetELFStreamer::EmitCodeEnd() { 621 const uint32_t Encoded_s_code_end = 0xbf9f0000; 622 623 MCStreamer &OS = getStreamer(); 624 OS.PushSection(); 625 OS.emitValueToAlignment(64, Encoded_s_code_end, 4); 626 for (unsigned I = 0; I < 48; ++I) 627 OS.emitInt32(Encoded_s_code_end); 628 OS.PopSection(); 629 return true; 630 } 631 632 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 633 const MCSubtargetInfo &STI, StringRef KernelName, 634 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 635 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, 636 bool ReserveXNACK) { 637 auto &Streamer = getStreamer(); 638 auto &Context = Streamer.getContext(); 639 640 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 641 Context.getOrCreateSymbol(Twine(KernelName))); 642 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 643 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 644 645 // Copy kernel descriptor symbol's binding, other and visibility from the 646 // kernel code symbol. 647 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 648 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 649 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 650 // Kernel descriptor symbol's type and size are fixed. 651 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 652 KernelDescriptorSymbol->setSize( 653 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 654 655 // The visibility of the kernel code symbol must be protected or less to allow 656 // static relocations from the kernel descriptor to be used. 657 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 658 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 659 660 Streamer.emitLabel(KernelDescriptorSymbol); 661 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size); 662 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size); 663 for (uint8_t Res : KernelDescriptor.reserved0) 664 Streamer.emitInt8(Res); 665 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 666 // expression being created is: 667 // (start of kernel code) - (start of kernel descriptor) 668 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 669 Streamer.emitValue(MCBinaryExpr::createSub( 670 MCSymbolRefExpr::create( 671 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 672 MCSymbolRefExpr::create( 673 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 674 Context), 675 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 676 for (uint8_t Res : KernelDescriptor.reserved1) 677 Streamer.emitInt8(Res); 678 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3); 679 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1); 680 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2); 681 Streamer.emitInt16(KernelDescriptor.kernel_code_properties); 682 for (uint8_t Res : KernelDescriptor.reserved2) 683 Streamer.emitInt8(Res); 684 } 685