1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPU.h" 15 #include "SIDefines.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/ADT/Twine.h" 19 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/IR/Constants.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/IR/Metadata.h" 24 #include "llvm/IR/Module.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCELFStreamer.h" 27 #include "llvm/MC/MCObjectFileInfo.h" 28 #include "llvm/MC/MCSectionELF.h" 29 #include "llvm/Support/FormattedStream.h" 30 #include "llvm/Support/TargetParser.h" 31 32 namespace llvm { 33 #include "AMDGPUPTNote.h" 34 } 35 36 using namespace llvm; 37 using namespace llvm::AMDGPU; 38 using namespace llvm::AMDGPU::HSAMD; 39 40 //===----------------------------------------------------------------------===// 41 // AMDGPUTargetStreamer 42 //===----------------------------------------------------------------------===// 43 44 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 45 HSAMD::Metadata HSAMetadata; 46 if (HSAMD::fromString(std::string(HSAMetadataString), HSAMetadata)) 47 return false; 48 49 return EmitHSAMetadata(HSAMetadata); 50 } 51 52 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 53 msgpack::Document HSAMetadataDoc; 54 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 55 return false; 56 return EmitHSAMetadata(HSAMetadataDoc, false); 57 } 58 59 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 60 AMDGPU::GPUKind AK; 61 62 switch (ElfMach) { 63 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type"); 64 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 65 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 66 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 67 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 68 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 69 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 70 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 71 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 72 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 73 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 74 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 75 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 76 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 77 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 78 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 79 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 80 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 81 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 82 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 102 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 103 } 104 105 StringRef GPUName = getArchNameAMDGCN(AK); 106 if (GPUName != "") 107 return GPUName; 108 return getArchNameR600(AK); 109 } 110 111 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 112 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 113 if (AK == AMDGPU::GPUKind::GK_NONE) 114 AK = parseArchR600(GPU); 115 116 switch (AK) { 117 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 118 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 119 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 120 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 121 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 122 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 123 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 124 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 125 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 126 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 127 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 128 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 129 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 130 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 131 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 132 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 133 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 134 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 135 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 136 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 137 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 138 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 139 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 140 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 141 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 142 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 143 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 144 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 145 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 146 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 147 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 148 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 149 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 150 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 151 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 152 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 153 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 154 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 155 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 156 } 157 158 llvm_unreachable("unknown GPU"); 159 } 160 161 //===----------------------------------------------------------------------===// 162 // AMDGPUTargetAsmStreamer 163 //===----------------------------------------------------------------------===// 164 165 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 166 formatted_raw_ostream &OS) 167 : AMDGPUTargetStreamer(S), OS(OS) { } 168 169 // A hook for emitting stuff at the end. 170 // We use it for emitting the accumulated PAL metadata as directives. 171 // The PAL metadata is reset after it is emitted. 172 void AMDGPUTargetAsmStreamer::finish() { 173 std::string S; 174 getPALMetadata()->toString(S); 175 OS << S; 176 177 // Reset the pal metadata so its data will not affect a compilation that 178 // reuses this object. 179 getPALMetadata()->reset(); 180 } 181 182 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) { 183 OS << "\t.amdgcn_target \"" << Target << "\"\n"; 184 } 185 186 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 187 uint32_t Major, uint32_t Minor) { 188 OS << "\t.hsa_code_object_version " << 189 Twine(Major) << "," << Twine(Minor) << '\n'; 190 } 191 192 void 193 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 194 uint32_t Minor, 195 uint32_t Stepping, 196 StringRef VendorName, 197 StringRef ArchName) { 198 OS << "\t.hsa_code_object_isa " << 199 Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) << 200 ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 201 202 } 203 204 void 205 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 206 OS << "\t.amd_kernel_code_t\n"; 207 dumpAmdKernelCode(&Header, OS, "\t\t"); 208 OS << "\t.end_amd_kernel_code_t\n"; 209 } 210 211 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 212 unsigned Type) { 213 switch (Type) { 214 default: llvm_unreachable("Invalid AMDGPU symbol type"); 215 case ELF::STT_AMDGPU_HSA_KERNEL: 216 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 217 break; 218 } 219 } 220 221 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 222 Align Alignment) { 223 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 224 << Alignment.value() << '\n'; 225 } 226 227 bool AMDGPUTargetAsmStreamer::EmitISAVersion(StringRef IsaVersionString) { 228 OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n"; 229 return true; 230 } 231 232 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 233 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 234 std::string HSAMetadataString; 235 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 236 return false; 237 238 OS << '\t' << AssemblerDirectiveBegin << '\n'; 239 OS << HSAMetadataString << '\n'; 240 OS << '\t' << AssemblerDirectiveEnd << '\n'; 241 return true; 242 } 243 244 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 245 msgpack::Document &HSAMetadataDoc, bool Strict) { 246 V3::MetadataVerifier Verifier(Strict); 247 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 248 return false; 249 250 std::string HSAMetadataString; 251 raw_string_ostream StrOS(HSAMetadataString); 252 HSAMetadataDoc.toYAML(StrOS); 253 254 OS << '\t' << V3::AssemblerDirectiveBegin << '\n'; 255 OS << StrOS.str() << '\n'; 256 OS << '\t' << V3::AssemblerDirectiveEnd << '\n'; 257 return true; 258 } 259 260 bool AMDGPUTargetAsmStreamer::EmitCodeEnd() { 261 const uint32_t Encoded_s_code_end = 0xbf9f0000; 262 OS << "\t.p2alignl 6, " << Encoded_s_code_end << '\n'; 263 OS << "\t.fill 48, 4, " << Encoded_s_code_end << '\n'; 264 return true; 265 } 266 267 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 268 const MCSubtargetInfo &STI, StringRef KernelName, 269 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 270 bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) { 271 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 272 273 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 274 275 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 276 STREAM << "\t\t" << DIRECTIVE << " " \ 277 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 278 279 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 280 << '\n'; 281 OS << "\t\t.amdhsa_private_segment_fixed_size " 282 << KD.private_segment_fixed_size << '\n'; 283 284 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 285 kernel_code_properties, 286 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 287 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 288 kernel_code_properties, 289 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 290 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 291 kernel_code_properties, 292 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 293 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 294 kernel_code_properties, 295 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 296 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 297 kernel_code_properties, 298 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 299 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 300 kernel_code_properties, 301 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 302 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 303 kernel_code_properties, 304 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 305 if (IVersion.Major >= 10) 306 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 307 kernel_code_properties, 308 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 309 PRINT_FIELD( 310 OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, 311 compute_pgm_rsrc2, 312 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET); 313 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 314 compute_pgm_rsrc2, 315 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 316 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 317 compute_pgm_rsrc2, 318 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 319 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 320 compute_pgm_rsrc2, 321 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 322 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 323 compute_pgm_rsrc2, 324 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 325 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 326 compute_pgm_rsrc2, 327 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 328 329 // These directives are required. 330 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 331 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 332 333 if (!ReserveVCC) 334 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 335 if (IVersion.Major >= 7 && !ReserveFlatScr) 336 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 337 if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI)) 338 OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n'; 339 340 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 341 compute_pgm_rsrc1, 342 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 343 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 344 compute_pgm_rsrc1, 345 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 346 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 347 compute_pgm_rsrc1, 348 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 349 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 350 compute_pgm_rsrc1, 351 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 352 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 353 compute_pgm_rsrc1, 354 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 355 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 356 compute_pgm_rsrc1, 357 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 358 if (IVersion.Major >= 9) 359 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 360 compute_pgm_rsrc1, 361 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 362 if (IVersion.Major >= 10) { 363 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 364 compute_pgm_rsrc1, 365 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 366 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 367 compute_pgm_rsrc1, 368 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 369 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 370 compute_pgm_rsrc1, 371 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 372 } 373 PRINT_FIELD( 374 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 375 compute_pgm_rsrc2, 376 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 377 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 378 compute_pgm_rsrc2, 379 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 380 PRINT_FIELD( 381 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 382 compute_pgm_rsrc2, 383 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 384 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 385 compute_pgm_rsrc2, 386 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 387 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 388 compute_pgm_rsrc2, 389 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 390 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 391 compute_pgm_rsrc2, 392 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 393 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 394 compute_pgm_rsrc2, 395 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 396 #undef PRINT_FIELD 397 398 OS << "\t.end_amdhsa_kernel\n"; 399 } 400 401 //===----------------------------------------------------------------------===// 402 // AMDGPUTargetELFStreamer 403 //===----------------------------------------------------------------------===// 404 405 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 406 const MCSubtargetInfo &STI) 407 : AMDGPUTargetStreamer(S), Streamer(S), Os(STI.getTargetTriple().getOS()) { 408 MCAssembler &MCA = getStreamer().getAssembler(); 409 unsigned EFlags = MCA.getELFHeaderEFlags(); 410 411 EFlags &= ~ELF::EF_AMDGPU_MACH; 412 EFlags |= getElfMach(STI.getCPU()); 413 414 EFlags &= ~ELF::EF_AMDGPU_XNACK; 415 if (AMDGPU::hasXNACK(STI)) 416 EFlags |= ELF::EF_AMDGPU_XNACK; 417 418 EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC; 419 if (AMDGPU::hasSRAMECC(STI)) 420 EFlags |= ELF::EF_AMDGPU_SRAM_ECC; 421 422 MCA.setELFHeaderEFlags(EFlags); 423 } 424 425 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 426 return static_cast<MCELFStreamer &>(Streamer); 427 } 428 429 // A hook for emitting stuff at the end. 430 // We use it for emitting the accumulated PAL metadata as a .note record. 431 // The PAL metadata is reset after it is emitted. 432 void AMDGPUTargetELFStreamer::finish() { 433 std::string Blob; 434 const char *Vendor = getPALMetadata()->getVendor(); 435 unsigned Type = getPALMetadata()->getType(); 436 getPALMetadata()->toBlob(Type, Blob); 437 if (Blob.empty()) 438 return; 439 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 440 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 441 442 // Reset the pal metadata so its data will not affect a compilation that 443 // reuses this object. 444 getPALMetadata()->reset(); 445 } 446 447 void AMDGPUTargetELFStreamer::EmitNote( 448 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 449 function_ref<void(MCELFStreamer &)> EmitDesc) { 450 auto &S = getStreamer(); 451 auto &Context = S.getContext(); 452 453 auto NameSZ = Name.size() + 1; 454 455 unsigned NoteFlags = 0; 456 // TODO Apparently, this is currently needed for OpenCL as mentioned in 457 // https://reviews.llvm.org/D74995 458 if (Os == Triple::AMDHSA) 459 NoteFlags = ELF::SHF_ALLOC; 460 461 S.PushSection(); 462 S.SwitchSection( 463 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 464 S.emitInt32(NameSZ); // namesz 465 S.emitValue(DescSZ, 4); // descz 466 S.emitInt32(NoteType); // type 467 S.emitBytes(Name); // name 468 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 469 EmitDesc(S); // desc 470 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 471 S.PopSection(); 472 } 473 474 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {} 475 476 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 477 uint32_t Major, uint32_t Minor) { 478 479 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 480 ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 481 OS.emitInt32(Major); 482 OS.emitInt32(Minor); 483 }); 484 } 485 486 void 487 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 488 uint32_t Minor, 489 uint32_t Stepping, 490 StringRef VendorName, 491 StringRef ArchName) { 492 uint16_t VendorNameSize = VendorName.size() + 1; 493 uint16_t ArchNameSize = ArchName.size() + 1; 494 495 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 496 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 497 VendorNameSize + ArchNameSize; 498 499 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 500 ElfNote::NT_AMDGPU_HSA_ISA, [&](MCELFStreamer &OS) { 501 OS.emitInt16(VendorNameSize); 502 OS.emitInt16(ArchNameSize); 503 OS.emitInt32(Major); 504 OS.emitInt32(Minor); 505 OS.emitInt32(Stepping); 506 OS.emitBytes(VendorName); 507 OS.emitInt8(0); // NULL terminate VendorName 508 OS.emitBytes(ArchName); 509 OS.emitInt8(0); // NULL terminte ArchName 510 }); 511 } 512 513 void 514 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 515 516 MCStreamer &OS = getStreamer(); 517 OS.PushSection(); 518 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 519 OS.PopSection(); 520 } 521 522 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 523 unsigned Type) { 524 MCSymbolELF *Symbol = cast<MCSymbolELF>( 525 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 526 Symbol->setType(Type); 527 } 528 529 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 530 Align Alignment) { 531 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 532 SymbolELF->setType(ELF::STT_OBJECT); 533 534 if (!SymbolELF->isBindingSet()) { 535 SymbolELF->setBinding(ELF::STB_GLOBAL); 536 SymbolELF->setExternal(true); 537 } 538 539 if (SymbolELF->declareCommon(Size, Alignment.value(), true)) { 540 report_fatal_error("Symbol: " + Symbol->getName() + 541 " redeclared as different type"); 542 } 543 544 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 545 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 546 } 547 548 bool AMDGPUTargetELFStreamer::EmitISAVersion(StringRef IsaVersionString) { 549 // Create two labels to mark the beginning and end of the desc field 550 // and a MCExpr to calculate the size of the desc field. 551 auto &Context = getContext(); 552 auto *DescBegin = Context.createTempSymbol(); 553 auto *DescEnd = Context.createTempSymbol(); 554 auto *DescSZ = MCBinaryExpr::createSub( 555 MCSymbolRefExpr::create(DescEnd, Context), 556 MCSymbolRefExpr::create(DescBegin, Context), Context); 557 558 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_ISA, 559 [&](MCELFStreamer &OS) { 560 OS.emitLabel(DescBegin); 561 OS.emitBytes(IsaVersionString); 562 OS.emitLabel(DescEnd); 563 }); 564 return true; 565 } 566 567 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 568 bool Strict) { 569 V3::MetadataVerifier Verifier(Strict); 570 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 571 return false; 572 573 std::string HSAMetadataString; 574 HSAMetadataDoc.writeToBlob(HSAMetadataString); 575 576 // Create two labels to mark the beginning and end of the desc field 577 // and a MCExpr to calculate the size of the desc field. 578 auto &Context = getContext(); 579 auto *DescBegin = Context.createTempSymbol(); 580 auto *DescEnd = Context.createTempSymbol(); 581 auto *DescSZ = MCBinaryExpr::createSub( 582 MCSymbolRefExpr::create(DescEnd, Context), 583 MCSymbolRefExpr::create(DescBegin, Context), Context); 584 585 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 586 [&](MCELFStreamer &OS) { 587 OS.emitLabel(DescBegin); 588 OS.emitBytes(HSAMetadataString); 589 OS.emitLabel(DescEnd); 590 }); 591 return true; 592 } 593 594 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 595 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 596 std::string HSAMetadataString; 597 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 598 return false; 599 600 // Create two labels to mark the beginning and end of the desc field 601 // and a MCExpr to calculate the size of the desc field. 602 auto &Context = getContext(); 603 auto *DescBegin = Context.createTempSymbol(); 604 auto *DescEnd = Context.createTempSymbol(); 605 auto *DescSZ = MCBinaryExpr::createSub( 606 MCSymbolRefExpr::create(DescEnd, Context), 607 MCSymbolRefExpr::create(DescBegin, Context), Context); 608 609 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_HSA_METADATA, 610 [&](MCELFStreamer &OS) { 611 OS.emitLabel(DescBegin); 612 OS.emitBytes(HSAMetadataString); 613 OS.emitLabel(DescEnd); 614 }); 615 return true; 616 } 617 618 bool AMDGPUTargetELFStreamer::EmitCodeEnd() { 619 const uint32_t Encoded_s_code_end = 0xbf9f0000; 620 621 MCStreamer &OS = getStreamer(); 622 OS.PushSection(); 623 OS.emitValueToAlignment(64, Encoded_s_code_end, 4); 624 for (unsigned I = 0; I < 48; ++I) 625 OS.emitInt32(Encoded_s_code_end); 626 OS.PopSection(); 627 return true; 628 } 629 630 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 631 const MCSubtargetInfo &STI, StringRef KernelName, 632 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 633 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, 634 bool ReserveXNACK) { 635 auto &Streamer = getStreamer(); 636 auto &Context = Streamer.getContext(); 637 638 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 639 Context.getOrCreateSymbol(Twine(KernelName))); 640 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 641 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 642 643 // Copy kernel descriptor symbol's binding, other and visibility from the 644 // kernel code symbol. 645 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 646 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 647 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 648 // Kernel descriptor symbol's type and size are fixed. 649 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 650 KernelDescriptorSymbol->setSize( 651 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 652 653 // The visibility of the kernel code symbol must be protected or less to allow 654 // static relocations from the kernel descriptor to be used. 655 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 656 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 657 658 Streamer.emitLabel(KernelDescriptorSymbol); 659 Streamer.emitBytes(StringRef( 660 (const char*)&(KernelDescriptor), 661 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset))); 662 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 663 // expression being created is: 664 // (start of kernel code) - (start of kernel descriptor) 665 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 666 Streamer.emitValue(MCBinaryExpr::createSub( 667 MCSymbolRefExpr::create( 668 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 669 MCSymbolRefExpr::create( 670 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 671 Context), 672 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 673 Streamer.emitBytes(StringRef( 674 (const char*)&(KernelDescriptor) + 675 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) + 676 sizeof(KernelDescriptor.kernel_code_entry_byte_offset), 677 sizeof(KernelDescriptor) - 678 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) - 679 sizeof(KernelDescriptor.kernel_code_entry_byte_offset))); 680 } 681