1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPU.h" 15 #include "SIDefines.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/ADT/Twine.h" 19 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/IR/Constants.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/IR/Metadata.h" 24 #include "llvm/IR/Module.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCELFStreamer.h" 27 #include "llvm/MC/MCObjectFileInfo.h" 28 #include "llvm/MC/MCSectionELF.h" 29 #include "llvm/Support/FormattedStream.h" 30 #include "llvm/Support/TargetParser.h" 31 32 namespace llvm { 33 #include "AMDGPUPTNote.h" 34 } 35 36 using namespace llvm; 37 using namespace llvm::AMDGPU; 38 using namespace llvm::AMDGPU::HSAMD; 39 40 //===----------------------------------------------------------------------===// 41 // AMDGPUTargetStreamer 42 //===----------------------------------------------------------------------===// 43 44 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 45 HSAMD::Metadata HSAMetadata; 46 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 47 return false; 48 49 return EmitHSAMetadata(HSAMetadata); 50 } 51 52 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 53 msgpack::Document HSAMetadataDoc; 54 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 55 return false; 56 return EmitHSAMetadata(HSAMetadataDoc, false); 57 } 58 59 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 60 AMDGPU::GPUKind AK; 61 62 switch (ElfMach) { 63 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 64 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 65 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 66 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 67 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 68 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 69 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 70 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 71 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 72 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 73 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 74 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 75 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 76 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 77 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 78 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 79 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 80 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 81 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 82 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 95 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 96 } 97 98 StringRef GPUName = getArchNameAMDGCN(AK); 99 if (GPUName != "") 100 return GPUName; 101 return getArchNameR600(AK); 102 } 103 104 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 105 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 106 if (AK == AMDGPU::GPUKind::GK_NONE) 107 AK = parseArchR600(GPU); 108 109 switch (AK) { 110 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 111 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 112 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 113 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 114 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 115 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 116 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 117 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 118 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 119 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 120 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 121 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 122 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 123 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 124 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 125 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 126 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 127 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 128 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 129 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 130 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 131 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 132 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 133 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 134 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 135 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 136 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 137 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 138 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 139 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 140 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 141 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 142 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 143 } 144 145 llvm_unreachable("unknown GPU"); 146 } 147 148 //===----------------------------------------------------------------------===// 149 // AMDGPUTargetAsmStreamer 150 //===----------------------------------------------------------------------===// 151 152 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 153 formatted_raw_ostream &OS) 154 : AMDGPUTargetStreamer(S), OS(OS) { } 155 156 // A hook for emitting stuff at the end. 157 // We use it for emitting the accumulated PAL metadata as directives. 158 void AMDGPUTargetAsmStreamer::finish() { 159 std::string S; 160 getPALMetadata()->toString(S); 161 OS << S; 162 } 163 164 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) { 165 OS << "\t.amdgcn_target \"" << Target << "\"\n"; 166 } 167 168 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 169 uint32_t Major, uint32_t Minor) { 170 OS << "\t.hsa_code_object_version " << 171 Twine(Major) << "," << Twine(Minor) << '\n'; 172 } 173 174 void 175 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 176 uint32_t Minor, 177 uint32_t Stepping, 178 StringRef VendorName, 179 StringRef ArchName) { 180 OS << "\t.hsa_code_object_isa " << 181 Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) << 182 ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 183 184 } 185 186 void 187 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 188 OS << "\t.amd_kernel_code_t\n"; 189 dumpAmdKernelCode(&Header, OS, "\t\t"); 190 OS << "\t.end_amd_kernel_code_t\n"; 191 } 192 193 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 194 unsigned Type) { 195 switch (Type) { 196 default: llvm_unreachable("Invalid AMDGPU symbol type"); 197 case ELF::STT_AMDGPU_HSA_KERNEL: 198 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 199 break; 200 } 201 } 202 203 bool AMDGPUTargetAsmStreamer::EmitISAVersion(StringRef IsaVersionString) { 204 OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n"; 205 return true; 206 } 207 208 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 209 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 210 std::string HSAMetadataString; 211 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 212 return false; 213 214 OS << '\t' << AssemblerDirectiveBegin << '\n'; 215 OS << HSAMetadataString << '\n'; 216 OS << '\t' << AssemblerDirectiveEnd << '\n'; 217 return true; 218 } 219 220 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 221 msgpack::Document &HSAMetadataDoc, bool Strict) { 222 V3::MetadataVerifier Verifier(Strict); 223 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 224 return false; 225 226 std::string HSAMetadataString; 227 raw_string_ostream StrOS(HSAMetadataString); 228 HSAMetadataDoc.toYAML(StrOS); 229 230 OS << '\t' << V3::AssemblerDirectiveBegin << '\n'; 231 OS << StrOS.str() << '\n'; 232 OS << '\t' << V3::AssemblerDirectiveEnd << '\n'; 233 return true; 234 } 235 236 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 237 const MCSubtargetInfo &STI, StringRef KernelName, 238 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 239 bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) { 240 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 241 242 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 243 244 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 245 STREAM << "\t\t" << DIRECTIVE << " " \ 246 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 247 248 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 249 << '\n'; 250 OS << "\t\t.amdhsa_private_segment_fixed_size " 251 << KD.private_segment_fixed_size << '\n'; 252 253 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 254 kernel_code_properties, 255 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 256 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 257 kernel_code_properties, 258 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 259 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 260 kernel_code_properties, 261 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 262 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 263 kernel_code_properties, 264 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 265 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 266 kernel_code_properties, 267 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 268 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 269 kernel_code_properties, 270 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 271 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 272 kernel_code_properties, 273 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 274 PRINT_FIELD( 275 OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, 276 compute_pgm_rsrc2, 277 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET); 278 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 279 compute_pgm_rsrc2, 280 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 281 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 282 compute_pgm_rsrc2, 283 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 284 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 285 compute_pgm_rsrc2, 286 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 287 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 288 compute_pgm_rsrc2, 289 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 290 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 291 compute_pgm_rsrc2, 292 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 293 294 // These directives are required. 295 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 296 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 297 298 if (!ReserveVCC) 299 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 300 if (IVersion.Major >= 7 && !ReserveFlatScr) 301 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 302 if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI)) 303 OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n'; 304 305 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 306 compute_pgm_rsrc1, 307 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 308 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 309 compute_pgm_rsrc1, 310 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 311 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 312 compute_pgm_rsrc1, 313 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 314 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 315 compute_pgm_rsrc1, 316 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 317 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 318 compute_pgm_rsrc1, 319 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 320 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 321 compute_pgm_rsrc1, 322 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 323 if (IVersion.Major >= 9) 324 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 325 compute_pgm_rsrc1, 326 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 327 PRINT_FIELD( 328 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 329 compute_pgm_rsrc2, 330 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 331 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 332 compute_pgm_rsrc2, 333 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 334 PRINT_FIELD( 335 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 336 compute_pgm_rsrc2, 337 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 338 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 339 compute_pgm_rsrc2, 340 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 341 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 342 compute_pgm_rsrc2, 343 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 344 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 345 compute_pgm_rsrc2, 346 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 347 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 348 compute_pgm_rsrc2, 349 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 350 #undef PRINT_FIELD 351 352 OS << "\t.end_amdhsa_kernel\n"; 353 } 354 355 //===----------------------------------------------------------------------===// 356 // AMDGPUTargetELFStreamer 357 //===----------------------------------------------------------------------===// 358 359 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer( 360 MCStreamer &S, const MCSubtargetInfo &STI) 361 : AMDGPUTargetStreamer(S), Streamer(S) { 362 MCAssembler &MCA = getStreamer().getAssembler(); 363 unsigned EFlags = MCA.getELFHeaderEFlags(); 364 365 EFlags &= ~ELF::EF_AMDGPU_MACH; 366 EFlags |= getElfMach(STI.getCPU()); 367 368 EFlags &= ~ELF::EF_AMDGPU_XNACK; 369 if (AMDGPU::hasXNACK(STI)) 370 EFlags |= ELF::EF_AMDGPU_XNACK; 371 372 EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC; 373 if (AMDGPU::hasSRAMECC(STI)) 374 EFlags |= ELF::EF_AMDGPU_SRAM_ECC; 375 376 MCA.setELFHeaderEFlags(EFlags); 377 } 378 379 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 380 return static_cast<MCELFStreamer &>(Streamer); 381 } 382 383 // A hook for emitting stuff at the end. 384 // We use it for emitting the accumulated PAL metadata as a .note record. 385 void AMDGPUTargetELFStreamer::finish() { 386 std::string Blob; 387 const char *Vendor = getPALMetadata()->getVendor(); 388 unsigned Type = getPALMetadata()->getType(); 389 getPALMetadata()->toBlob(Type, Blob); 390 if (Blob.empty()) 391 return; 392 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 393 [&](MCELFStreamer &OS) { OS.EmitBytes(Blob); }); 394 } 395 396 void AMDGPUTargetELFStreamer::EmitNote( 397 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 398 function_ref<void(MCELFStreamer &)> EmitDesc) { 399 auto &S = getStreamer(); 400 auto &Context = S.getContext(); 401 402 auto NameSZ = Name.size() + 1; 403 404 S.PushSection(); 405 S.SwitchSection(Context.getELFSection( 406 ElfNote::SectionName, ELF::SHT_NOTE, ELF::SHF_ALLOC)); 407 S.EmitIntValue(NameSZ, 4); // namesz 408 S.EmitValue(DescSZ, 4); // descz 409 S.EmitIntValue(NoteType, 4); // type 410 S.EmitBytes(Name); // name 411 S.EmitValueToAlignment(4, 0, 1, 0); // padding 0 412 EmitDesc(S); // desc 413 S.EmitValueToAlignment(4, 0, 1, 0); // padding 0 414 S.PopSection(); 415 } 416 417 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {} 418 419 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 420 uint32_t Major, uint32_t Minor) { 421 422 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 423 ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 424 OS.EmitIntValue(Major, 4); 425 OS.EmitIntValue(Minor, 4); 426 }); 427 } 428 429 void 430 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 431 uint32_t Minor, 432 uint32_t Stepping, 433 StringRef VendorName, 434 StringRef ArchName) { 435 uint16_t VendorNameSize = VendorName.size() + 1; 436 uint16_t ArchNameSize = ArchName.size() + 1; 437 438 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 439 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 440 VendorNameSize + ArchNameSize; 441 442 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 443 ElfNote::NT_AMDGPU_HSA_ISA, [&](MCELFStreamer &OS) { 444 OS.EmitIntValue(VendorNameSize, 2); 445 OS.EmitIntValue(ArchNameSize, 2); 446 OS.EmitIntValue(Major, 4); 447 OS.EmitIntValue(Minor, 4); 448 OS.EmitIntValue(Stepping, 4); 449 OS.EmitBytes(VendorName); 450 OS.EmitIntValue(0, 1); // NULL terminate VendorName 451 OS.EmitBytes(ArchName); 452 OS.EmitIntValue(0, 1); // NULL terminte ArchName 453 }); 454 } 455 456 void 457 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 458 459 MCStreamer &OS = getStreamer(); 460 OS.PushSection(); 461 OS.EmitBytes(StringRef((const char*)&Header, sizeof(Header))); 462 OS.PopSection(); 463 } 464 465 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 466 unsigned Type) { 467 MCSymbolELF *Symbol = cast<MCSymbolELF>( 468 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 469 Symbol->setType(Type); 470 } 471 472 bool AMDGPUTargetELFStreamer::EmitISAVersion(StringRef IsaVersionString) { 473 // Create two labels to mark the beginning and end of the desc field 474 // and a MCExpr to calculate the size of the desc field. 475 auto &Context = getContext(); 476 auto *DescBegin = Context.createTempSymbol(); 477 auto *DescEnd = Context.createTempSymbol(); 478 auto *DescSZ = MCBinaryExpr::createSub( 479 MCSymbolRefExpr::create(DescEnd, Context), 480 MCSymbolRefExpr::create(DescBegin, Context), Context); 481 482 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_ISA, 483 [&](MCELFStreamer &OS) { 484 OS.EmitLabel(DescBegin); 485 OS.EmitBytes(IsaVersionString); 486 OS.EmitLabel(DescEnd); 487 }); 488 return true; 489 } 490 491 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 492 bool Strict) { 493 V3::MetadataVerifier Verifier(Strict); 494 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 495 return false; 496 497 std::string HSAMetadataString; 498 HSAMetadataDoc.writeToBlob(HSAMetadataString); 499 500 // Create two labels to mark the beginning and end of the desc field 501 // and a MCExpr to calculate the size of the desc field. 502 auto &Context = getContext(); 503 auto *DescBegin = Context.createTempSymbol(); 504 auto *DescEnd = Context.createTempSymbol(); 505 auto *DescSZ = MCBinaryExpr::createSub( 506 MCSymbolRefExpr::create(DescEnd, Context), 507 MCSymbolRefExpr::create(DescBegin, Context), Context); 508 509 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 510 [&](MCELFStreamer &OS) { 511 OS.EmitLabel(DescBegin); 512 OS.EmitBytes(HSAMetadataString); 513 OS.EmitLabel(DescEnd); 514 }); 515 return true; 516 } 517 518 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 519 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 520 std::string HSAMetadataString; 521 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 522 return false; 523 524 // Create two labels to mark the beginning and end of the desc field 525 // and a MCExpr to calculate the size of the desc field. 526 auto &Context = getContext(); 527 auto *DescBegin = Context.createTempSymbol(); 528 auto *DescEnd = Context.createTempSymbol(); 529 auto *DescSZ = MCBinaryExpr::createSub( 530 MCSymbolRefExpr::create(DescEnd, Context), 531 MCSymbolRefExpr::create(DescBegin, Context), Context); 532 533 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_HSA_METADATA, 534 [&](MCELFStreamer &OS) { 535 OS.EmitLabel(DescBegin); 536 OS.EmitBytes(HSAMetadataString); 537 OS.EmitLabel(DescEnd); 538 }); 539 return true; 540 } 541 542 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 543 const MCSubtargetInfo &STI, StringRef KernelName, 544 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 545 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, 546 bool ReserveXNACK) { 547 auto &Streamer = getStreamer(); 548 auto &Context = Streamer.getContext(); 549 550 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 551 Context.getOrCreateSymbol(Twine(KernelName))); 552 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 553 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 554 555 // Copy kernel descriptor symbol's binding, other and visibility from the 556 // kernel code symbol. 557 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 558 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 559 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 560 // Kernel descriptor symbol's type and size are fixed. 561 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 562 KernelDescriptorSymbol->setSize( 563 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 564 565 // The visibility of the kernel code symbol must be protected or less to allow 566 // static relocations from the kernel descriptor to be used. 567 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 568 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 569 570 Streamer.EmitLabel(KernelDescriptorSymbol); 571 Streamer.EmitBytes(StringRef( 572 (const char*)&(KernelDescriptor), 573 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset))); 574 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 575 // expression being created is: 576 // (start of kernel code) - (start of kernel descriptor) 577 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 578 Streamer.EmitValue(MCBinaryExpr::createSub( 579 MCSymbolRefExpr::create( 580 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 581 MCSymbolRefExpr::create( 582 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 583 Context), 584 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 585 Streamer.EmitBytes(StringRef( 586 (const char*)&(KernelDescriptor) + 587 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) + 588 sizeof(KernelDescriptor.kernel_code_entry_byte_offset), 589 sizeof(KernelDescriptor) - 590 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) - 591 sizeof(KernelDescriptor.kernel_code_entry_byte_offset))); 592 } 593