1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPUPTNote.h" 15 #include "AMDKernelCodeT.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCELFStreamer.h" 22 #include "llvm/MC/MCSectionELF.h" 23 #include "llvm/Support/AMDGPUMetadata.h" 24 #include "llvm/Support/AMDHSAKernelDescriptor.h" 25 #include "llvm/Support/FormattedStream.h" 26 27 using namespace llvm; 28 using namespace llvm::AMDGPU; 29 30 //===----------------------------------------------------------------------===// 31 // AMDGPUTargetStreamer 32 //===----------------------------------------------------------------------===// 33 34 static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, 35 uint32_t &Stepping, bool Sramecc, bool Xnack) { 36 if (Major == 9 && Minor == 0) { 37 switch (Stepping) { 38 case 0: 39 case 2: 40 case 4: 41 case 6: 42 if (Xnack) 43 Stepping++; 44 } 45 } 46 } 47 48 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 49 HSAMD::Metadata HSAMetadata; 50 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 51 return false; 52 return EmitHSAMetadata(HSAMetadata); 53 } 54 55 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 56 msgpack::Document HSAMetadataDoc; 57 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 58 return false; 59 return EmitHSAMetadata(HSAMetadataDoc, false); 60 } 61 62 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 63 AMDGPU::GPUKind AK; 64 65 switch (ElfMach) { 66 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type"); 67 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 68 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 69 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 70 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 71 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 72 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 73 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 74 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 75 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 76 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 77 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 78 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 79 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 80 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 81 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 82 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break; 104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break; 105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break; 111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break; 112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break; 113 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 114 } 115 116 StringRef GPUName = getArchNameAMDGCN(AK); 117 if (GPUName != "") 118 return GPUName; 119 return getArchNameR600(AK); 120 } 121 122 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 123 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 124 if (AK == AMDGPU::GPUKind::GK_NONE) 125 AK = parseArchR600(GPU); 126 127 switch (AK) { 128 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 129 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 130 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 131 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 132 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 133 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 134 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 135 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 136 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 137 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 138 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 139 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 140 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 141 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 142 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 143 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 144 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 145 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 146 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602; 147 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 148 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 149 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 150 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 151 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 152 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705; 153 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 154 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 155 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 156 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805; 157 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 158 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 159 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 160 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 161 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 162 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 163 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 164 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A; 165 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C; 166 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 167 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 168 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 169 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 170 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 171 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032; 172 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033; 173 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034; 174 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 175 } 176 177 llvm_unreachable("unknown GPU"); 178 } 179 180 //===----------------------------------------------------------------------===// 181 // AMDGPUTargetAsmStreamer 182 //===----------------------------------------------------------------------===// 183 184 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 185 formatted_raw_ostream &OS) 186 : AMDGPUTargetStreamer(S), OS(OS) { } 187 188 // A hook for emitting stuff at the end. 189 // We use it for emitting the accumulated PAL metadata as directives. 190 // The PAL metadata is reset after it is emitted. 191 void AMDGPUTargetAsmStreamer::finish() { 192 std::string S; 193 getPALMetadata()->toString(S); 194 OS << S; 195 196 // Reset the pal metadata so its data will not affect a compilation that 197 // reuses this object. 198 getPALMetadata()->reset(); 199 } 200 201 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() { 202 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n"; 203 } 204 205 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 206 uint32_t Major, uint32_t Minor) { 207 OS << "\t.hsa_code_object_version " << 208 Twine(Major) << "," << Twine(Minor) << '\n'; 209 } 210 211 void 212 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 213 uint32_t Minor, 214 uint32_t Stepping, 215 StringRef VendorName, 216 StringRef ArchName) { 217 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 218 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << "," 219 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 220 } 221 222 void 223 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 224 OS << "\t.amd_kernel_code_t\n"; 225 dumpAmdKernelCode(&Header, OS, "\t\t"); 226 OS << "\t.end_amd_kernel_code_t\n"; 227 } 228 229 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 230 unsigned Type) { 231 switch (Type) { 232 default: llvm_unreachable("Invalid AMDGPU symbol type"); 233 case ELF::STT_AMDGPU_HSA_KERNEL: 234 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 235 break; 236 } 237 } 238 239 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 240 Align Alignment) { 241 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 242 << Alignment.value() << '\n'; 243 } 244 245 bool AMDGPUTargetAsmStreamer::EmitISAVersion() { 246 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n"; 247 return true; 248 } 249 250 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 251 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 252 std::string HSAMetadataString; 253 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 254 return false; 255 256 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n'; 257 OS << HSAMetadataString << '\n'; 258 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n'; 259 return true; 260 } 261 262 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 263 msgpack::Document &HSAMetadataDoc, bool Strict) { 264 HSAMD::V3::MetadataVerifier Verifier(Strict); 265 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 266 return false; 267 268 std::string HSAMetadataString; 269 raw_string_ostream StrOS(HSAMetadataString); 270 HSAMetadataDoc.toYAML(StrOS); 271 272 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n'; 273 OS << StrOS.str() << '\n'; 274 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n'; 275 return true; 276 } 277 278 bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 279 const uint32_t Encoded_s_code_end = 0xbf9f0000; 280 const uint32_t Encoded_s_nop = 0xbf800000; 281 uint32_t Encoded_pad = Encoded_s_code_end; 282 283 // Instruction cache line size in bytes. 284 const unsigned Log2CacheLineSize = 6; 285 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 286 287 // Extra padding amount in bytes to support prefetch mode 3. 288 unsigned FillSize = 3 * CacheLineSize; 289 290 if (AMDGPU::isGFX90A(STI)) { 291 Encoded_pad = Encoded_s_nop; 292 FillSize = 16 * CacheLineSize; 293 } 294 295 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n'; 296 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n'; 297 return true; 298 } 299 300 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 301 const MCSubtargetInfo &STI, StringRef KernelName, 302 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 303 bool ReserveVCC, bool ReserveFlatScr) { 304 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 305 306 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 307 308 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 309 STREAM << "\t\t" << DIRECTIVE << " " \ 310 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 311 312 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 313 << '\n'; 314 OS << "\t\t.amdhsa_private_segment_fixed_size " 315 << KD.private_segment_fixed_size << '\n'; 316 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n'; 317 318 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 319 kernel_code_properties, 320 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 321 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 322 kernel_code_properties, 323 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 324 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 325 kernel_code_properties, 326 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 327 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 328 kernel_code_properties, 329 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 330 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 331 kernel_code_properties, 332 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 333 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 334 kernel_code_properties, 335 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 336 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 337 kernel_code_properties, 338 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 339 if (IVersion.Major >= 10) 340 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 341 kernel_code_properties, 342 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 343 PRINT_FIELD( 344 OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, 345 compute_pgm_rsrc2, 346 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 347 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 348 compute_pgm_rsrc2, 349 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 350 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 351 compute_pgm_rsrc2, 352 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 353 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 354 compute_pgm_rsrc2, 355 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 356 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 357 compute_pgm_rsrc2, 358 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 359 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 360 compute_pgm_rsrc2, 361 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 362 363 // These directives are required. 364 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 365 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 366 367 if (AMDGPU::isGFX90A(STI)) 368 OS << "\t\t.amdhsa_accum_offset " << 369 (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3, 370 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 371 << '\n'; 372 373 if (!ReserveVCC) 374 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 375 if (IVersion.Major >= 7 && !ReserveFlatScr) 376 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 377 378 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 379 switch (*HsaAbiVer) { 380 default: 381 break; 382 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 383 break; 384 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 385 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 386 if (getTargetID()->isXnackSupported()) 387 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n'; 388 break; 389 } 390 } 391 392 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 393 compute_pgm_rsrc1, 394 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 395 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 396 compute_pgm_rsrc1, 397 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 398 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 399 compute_pgm_rsrc1, 400 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 401 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 402 compute_pgm_rsrc1, 403 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 404 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 405 compute_pgm_rsrc1, 406 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 407 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 408 compute_pgm_rsrc1, 409 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 410 if (IVersion.Major >= 9) 411 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 412 compute_pgm_rsrc1, 413 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 414 if (AMDGPU::isGFX90A(STI)) 415 PRINT_FIELD(OS, ".amdhsa_tg_split", KD, 416 compute_pgm_rsrc3, 417 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 418 if (IVersion.Major >= 10) { 419 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 420 compute_pgm_rsrc1, 421 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 422 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 423 compute_pgm_rsrc1, 424 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 425 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 426 compute_pgm_rsrc1, 427 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 428 } 429 PRINT_FIELD( 430 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 431 compute_pgm_rsrc2, 432 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 433 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 434 compute_pgm_rsrc2, 435 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 436 PRINT_FIELD( 437 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 438 compute_pgm_rsrc2, 439 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 440 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 441 compute_pgm_rsrc2, 442 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 443 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 444 compute_pgm_rsrc2, 445 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 446 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 447 compute_pgm_rsrc2, 448 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 449 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 450 compute_pgm_rsrc2, 451 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 452 #undef PRINT_FIELD 453 454 OS << "\t.end_amdhsa_kernel\n"; 455 } 456 457 //===----------------------------------------------------------------------===// 458 // AMDGPUTargetELFStreamer 459 //===----------------------------------------------------------------------===// 460 461 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 462 const MCSubtargetInfo &STI) 463 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {} 464 465 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 466 return static_cast<MCELFStreamer &>(Streamer); 467 } 468 469 // A hook for emitting stuff at the end. 470 // We use it for emitting the accumulated PAL metadata as a .note record. 471 // The PAL metadata is reset after it is emitted. 472 void AMDGPUTargetELFStreamer::finish() { 473 MCAssembler &MCA = getStreamer().getAssembler(); 474 MCA.setELFHeaderEFlags(getEFlags()); 475 476 std::string Blob; 477 const char *Vendor = getPALMetadata()->getVendor(); 478 unsigned Type = getPALMetadata()->getType(); 479 getPALMetadata()->toBlob(Type, Blob); 480 if (Blob.empty()) 481 return; 482 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 483 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 484 485 // Reset the pal metadata so its data will not affect a compilation that 486 // reuses this object. 487 getPALMetadata()->reset(); 488 } 489 490 void AMDGPUTargetELFStreamer::EmitNote( 491 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 492 function_ref<void(MCELFStreamer &)> EmitDesc) { 493 auto &S = getStreamer(); 494 auto &Context = S.getContext(); 495 496 auto NameSZ = Name.size() + 1; 497 498 unsigned NoteFlags = 0; 499 // TODO Apparently, this is currently needed for OpenCL as mentioned in 500 // https://reviews.llvm.org/D74995 501 if (STI.getTargetTriple().getOS() == Triple::AMDHSA) 502 NoteFlags = ELF::SHF_ALLOC; 503 504 S.PushSection(); 505 S.SwitchSection( 506 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 507 S.emitInt32(NameSZ); // namesz 508 S.emitValue(DescSZ, 4); // descz 509 S.emitInt32(NoteType); // type 510 S.emitBytes(Name); // name 511 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 512 EmitDesc(S); // desc 513 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 514 S.PopSection(); 515 } 516 517 unsigned AMDGPUTargetELFStreamer::getEFlags() { 518 switch (STI.getTargetTriple().getArch()) { 519 default: 520 llvm_unreachable("Unsupported Arch"); 521 case Triple::r600: 522 return getEFlagsR600(); 523 case Triple::amdgcn: 524 return getEFlagsAMDGCN(); 525 } 526 } 527 528 unsigned AMDGPUTargetELFStreamer::getEFlagsR600() { 529 assert(STI.getTargetTriple().getArch() == Triple::r600); 530 531 return getElfMach(STI.getCPU()); 532 } 533 534 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() { 535 assert(STI.getTargetTriple().getArch() == Triple::amdgcn); 536 537 switch (STI.getTargetTriple().getOS()) { 538 default: 539 // TODO: Why are some tests have "mingw" listed as OS? 540 // llvm_unreachable("Unsupported OS"); 541 case Triple::UnknownOS: 542 return getEFlagsUnknownOS(); 543 case Triple::AMDHSA: 544 return getEFlagsAMDHSA(); 545 case Triple::AMDPAL: 546 return getEFlagsAMDPAL(); 547 case Triple::Mesa3D: 548 return getEFlagsMesa3D(); 549 } 550 } 551 552 unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() { 553 // TODO: Why are some tests have "mingw" listed as OS? 554 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS); 555 556 return getEFlagsV3(); 557 } 558 559 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() { 560 assert(STI.getTargetTriple().getOS() == Triple::AMDHSA); 561 562 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 563 switch (*HsaAbiVer) { 564 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 565 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 566 return getEFlagsV3(); 567 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 568 return getEFlagsV4(); 569 } 570 } 571 572 llvm_unreachable("HSA OS ABI Version identification must be defined"); 573 } 574 575 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() { 576 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL); 577 578 return getEFlagsV3(); 579 } 580 581 unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() { 582 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D); 583 584 return getEFlagsV3(); 585 } 586 587 unsigned AMDGPUTargetELFStreamer::getEFlagsV3() { 588 unsigned EFlagsV3 = 0; 589 590 // mach. 591 EFlagsV3 |= getElfMach(STI.getCPU()); 592 593 // xnack. 594 if (getTargetID()->isXnackOnOrAny()) 595 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3; 596 // sramecc. 597 if (getTargetID()->isSramEccOnOrAny()) 598 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3; 599 600 return EFlagsV3; 601 } 602 603 unsigned AMDGPUTargetELFStreamer::getEFlagsV4() { 604 unsigned EFlagsV4 = 0; 605 606 // mach. 607 EFlagsV4 |= getElfMach(STI.getCPU()); 608 609 // xnack. 610 switch (getTargetID()->getXnackSetting()) { 611 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 612 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4; 613 break; 614 case AMDGPU::IsaInfo::TargetIDSetting::Any: 615 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4; 616 break; 617 case AMDGPU::IsaInfo::TargetIDSetting::Off: 618 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4; 619 break; 620 case AMDGPU::IsaInfo::TargetIDSetting::On: 621 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4; 622 break; 623 } 624 // sramecc. 625 switch (getTargetID()->getSramEccSetting()) { 626 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 627 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4; 628 break; 629 case AMDGPU::IsaInfo::TargetIDSetting::Any: 630 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4; 631 break; 632 case AMDGPU::IsaInfo::TargetIDSetting::Off: 633 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4; 634 break; 635 case AMDGPU::IsaInfo::TargetIDSetting::On: 636 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4; 637 break; 638 } 639 640 return EFlagsV4; 641 } 642 643 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {} 644 645 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 646 uint32_t Major, uint32_t Minor) { 647 648 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 649 ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 650 OS.emitInt32(Major); 651 OS.emitInt32(Minor); 652 }); 653 } 654 655 void 656 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 657 uint32_t Minor, 658 uint32_t Stepping, 659 StringRef VendorName, 660 StringRef ArchName) { 661 uint16_t VendorNameSize = VendorName.size() + 1; 662 uint16_t ArchNameSize = ArchName.size() + 1; 663 664 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 665 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 666 VendorNameSize + ArchNameSize; 667 668 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 669 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 670 ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) { 671 OS.emitInt16(VendorNameSize); 672 OS.emitInt16(ArchNameSize); 673 OS.emitInt32(Major); 674 OS.emitInt32(Minor); 675 OS.emitInt32(Stepping); 676 OS.emitBytes(VendorName); 677 OS.emitInt8(0); // NULL terminate VendorName 678 OS.emitBytes(ArchName); 679 OS.emitInt8(0); // NULL terminte ArchName 680 }); 681 } 682 683 void 684 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 685 686 MCStreamer &OS = getStreamer(); 687 OS.PushSection(); 688 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 689 OS.PopSection(); 690 } 691 692 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 693 unsigned Type) { 694 MCSymbolELF *Symbol = cast<MCSymbolELF>( 695 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 696 Symbol->setType(Type); 697 } 698 699 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 700 Align Alignment) { 701 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 702 SymbolELF->setType(ELF::STT_OBJECT); 703 704 if (!SymbolELF->isBindingSet()) { 705 SymbolELF->setBinding(ELF::STB_GLOBAL); 706 SymbolELF->setExternal(true); 707 } 708 709 if (SymbolELF->declareCommon(Size, Alignment.value(), true)) { 710 report_fatal_error("Symbol: " + Symbol->getName() + 711 " redeclared as different type"); 712 } 713 714 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 715 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 716 } 717 718 bool AMDGPUTargetELFStreamer::EmitISAVersion() { 719 // Create two labels to mark the beginning and end of the desc field 720 // and a MCExpr to calculate the size of the desc field. 721 auto &Context = getContext(); 722 auto *DescBegin = Context.createTempSymbol(); 723 auto *DescEnd = Context.createTempSymbol(); 724 auto *DescSZ = MCBinaryExpr::createSub( 725 MCSymbolRefExpr::create(DescEnd, Context), 726 MCSymbolRefExpr::create(DescBegin, Context), Context); 727 728 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME, 729 [&](MCELFStreamer &OS) { 730 OS.emitLabel(DescBegin); 731 OS.emitBytes(getTargetID()->toString()); 732 OS.emitLabel(DescEnd); 733 }); 734 return true; 735 } 736 737 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 738 bool Strict) { 739 HSAMD::V3::MetadataVerifier Verifier(Strict); 740 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 741 return false; 742 743 std::string HSAMetadataString; 744 HSAMetadataDoc.writeToBlob(HSAMetadataString); 745 746 // Create two labels to mark the beginning and end of the desc field 747 // and a MCExpr to calculate the size of the desc field. 748 auto &Context = getContext(); 749 auto *DescBegin = Context.createTempSymbol(); 750 auto *DescEnd = Context.createTempSymbol(); 751 auto *DescSZ = MCBinaryExpr::createSub( 752 MCSymbolRefExpr::create(DescEnd, Context), 753 MCSymbolRefExpr::create(DescBegin, Context), Context); 754 755 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 756 [&](MCELFStreamer &OS) { 757 OS.emitLabel(DescBegin); 758 OS.emitBytes(HSAMetadataString); 759 OS.emitLabel(DescEnd); 760 }); 761 return true; 762 } 763 764 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 765 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 766 std::string HSAMetadataString; 767 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 768 return false; 769 770 // Create two labels to mark the beginning and end of the desc field 771 // and a MCExpr to calculate the size of the desc field. 772 auto &Context = getContext(); 773 auto *DescBegin = Context.createTempSymbol(); 774 auto *DescEnd = Context.createTempSymbol(); 775 auto *DescSZ = MCBinaryExpr::createSub( 776 MCSymbolRefExpr::create(DescEnd, Context), 777 MCSymbolRefExpr::create(DescBegin, Context), Context); 778 779 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA, 780 [&](MCELFStreamer &OS) { 781 OS.emitLabel(DescBegin); 782 OS.emitBytes(HSAMetadataString); 783 OS.emitLabel(DescEnd); 784 }); 785 return true; 786 } 787 788 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 789 const uint32_t Encoded_s_code_end = 0xbf9f0000; 790 const uint32_t Encoded_s_nop = 0xbf800000; 791 uint32_t Encoded_pad = Encoded_s_code_end; 792 793 // Instruction cache line size in bytes. 794 const unsigned Log2CacheLineSize = 6; 795 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 796 797 // Extra padding amount in bytes to support prefetch mode 3. 798 unsigned FillSize = 3 * CacheLineSize; 799 800 if (AMDGPU::isGFX90A(STI)) { 801 Encoded_pad = Encoded_s_nop; 802 FillSize = 16 * CacheLineSize; 803 } 804 805 MCStreamer &OS = getStreamer(); 806 OS.PushSection(); 807 OS.emitValueToAlignment(CacheLineSize, Encoded_pad, 4); 808 for (unsigned I = 0; I < FillSize; I += 4) 809 OS.emitInt32(Encoded_pad); 810 OS.PopSection(); 811 return true; 812 } 813 814 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 815 const MCSubtargetInfo &STI, StringRef KernelName, 816 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 817 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) { 818 auto &Streamer = getStreamer(); 819 auto &Context = Streamer.getContext(); 820 821 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 822 Context.getOrCreateSymbol(Twine(KernelName))); 823 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 824 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 825 826 // Copy kernel descriptor symbol's binding, other and visibility from the 827 // kernel code symbol. 828 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 829 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 830 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 831 // Kernel descriptor symbol's type and size are fixed. 832 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 833 KernelDescriptorSymbol->setSize( 834 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 835 836 // The visibility of the kernel code symbol must be protected or less to allow 837 // static relocations from the kernel descriptor to be used. 838 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 839 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 840 841 Streamer.emitLabel(KernelDescriptorSymbol); 842 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size); 843 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size); 844 Streamer.emitInt32(KernelDescriptor.kernarg_size); 845 846 for (uint8_t Res : KernelDescriptor.reserved0) 847 Streamer.emitInt8(Res); 848 849 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 850 // expression being created is: 851 // (start of kernel code) - (start of kernel descriptor) 852 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 853 Streamer.emitValue(MCBinaryExpr::createSub( 854 MCSymbolRefExpr::create( 855 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 856 MCSymbolRefExpr::create( 857 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 858 Context), 859 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 860 for (uint8_t Res : KernelDescriptor.reserved1) 861 Streamer.emitInt8(Res); 862 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3); 863 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1); 864 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2); 865 Streamer.emitInt16(KernelDescriptor.kernel_code_properties); 866 for (uint8_t Res : KernelDescriptor.reserved2) 867 Streamer.emitInt8(Res); 868 } 869