1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPUPTNote.h" 15 #include "AMDKernelCodeT.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCELFStreamer.h" 22 #include "llvm/MC/MCSectionELF.h" 23 #include "llvm/Support/AMDGPUMetadata.h" 24 #include "llvm/Support/AMDHSAKernelDescriptor.h" 25 #include "llvm/Support/FormattedStream.h" 26 27 using namespace llvm; 28 using namespace llvm::AMDGPU; 29 30 //===----------------------------------------------------------------------===// 31 // AMDGPUTargetStreamer 32 //===----------------------------------------------------------------------===// 33 34 static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, 35 uint32_t &Stepping, bool Sramecc, bool Xnack) { 36 if (Major == 9 && Minor == 0) { 37 switch (Stepping) { 38 case 0: 39 case 2: 40 case 4: 41 case 6: 42 if (Xnack) 43 Stepping++; 44 } 45 } 46 } 47 48 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 49 HSAMD::Metadata HSAMetadata; 50 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 51 return false; 52 return EmitHSAMetadata(HSAMetadata); 53 } 54 55 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 56 msgpack::Document HSAMetadataDoc; 57 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 58 return false; 59 return EmitHSAMetadata(HSAMetadataDoc, false); 60 } 61 62 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 63 AMDGPU::GPUKind AK; 64 65 switch (ElfMach) { 66 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type"); 67 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 68 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 69 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 70 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 71 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 72 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 73 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 74 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 75 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 76 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 77 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 78 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 79 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 80 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 81 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 82 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break; 104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break; 105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break; 109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break; 112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break; 113 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break; 114 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: AK = GK_GFX1035; break; 115 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 116 } 117 118 StringRef GPUName = getArchNameAMDGCN(AK); 119 if (GPUName != "") 120 return GPUName; 121 return getArchNameR600(AK); 122 } 123 124 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 125 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 126 if (AK == AMDGPU::GPUKind::GK_NONE) 127 AK = parseArchR600(GPU); 128 129 switch (AK) { 130 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 131 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 132 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 133 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 134 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 135 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 136 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 137 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 138 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 139 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 140 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 141 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 142 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 143 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 144 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 145 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 146 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 147 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 148 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602; 149 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 150 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 151 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 152 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 153 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 154 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705; 155 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 156 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 157 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 158 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805; 159 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 160 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 161 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 162 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 163 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 164 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 165 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 166 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A; 167 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C; 168 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 169 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 170 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 171 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013; 172 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 173 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 174 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032; 175 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033; 176 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034; 177 case GK_GFX1035: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035; 178 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 179 } 180 181 llvm_unreachable("unknown GPU"); 182 } 183 184 //===----------------------------------------------------------------------===// 185 // AMDGPUTargetAsmStreamer 186 //===----------------------------------------------------------------------===// 187 188 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 189 formatted_raw_ostream &OS) 190 : AMDGPUTargetStreamer(S), OS(OS) { } 191 192 // A hook for emitting stuff at the end. 193 // We use it for emitting the accumulated PAL metadata as directives. 194 // The PAL metadata is reset after it is emitted. 195 void AMDGPUTargetAsmStreamer::finish() { 196 std::string S; 197 getPALMetadata()->toString(S); 198 OS << S; 199 200 // Reset the pal metadata so its data will not affect a compilation that 201 // reuses this object. 202 getPALMetadata()->reset(); 203 } 204 205 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() { 206 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n"; 207 } 208 209 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 210 uint32_t Major, uint32_t Minor) { 211 OS << "\t.hsa_code_object_version " << 212 Twine(Major) << "," << Twine(Minor) << '\n'; 213 } 214 215 void 216 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 217 uint32_t Minor, 218 uint32_t Stepping, 219 StringRef VendorName, 220 StringRef ArchName) { 221 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 222 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << "," 223 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 224 } 225 226 void 227 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 228 OS << "\t.amd_kernel_code_t\n"; 229 dumpAmdKernelCode(&Header, OS, "\t\t"); 230 OS << "\t.end_amd_kernel_code_t\n"; 231 } 232 233 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 234 unsigned Type) { 235 switch (Type) { 236 default: llvm_unreachable("Invalid AMDGPU symbol type"); 237 case ELF::STT_AMDGPU_HSA_KERNEL: 238 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 239 break; 240 } 241 } 242 243 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 244 Align Alignment) { 245 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 246 << Alignment.value() << '\n'; 247 } 248 249 bool AMDGPUTargetAsmStreamer::EmitISAVersion() { 250 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n"; 251 return true; 252 } 253 254 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 255 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 256 std::string HSAMetadataString; 257 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 258 return false; 259 260 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n'; 261 OS << HSAMetadataString << '\n'; 262 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n'; 263 return true; 264 } 265 266 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 267 msgpack::Document &HSAMetadataDoc, bool Strict) { 268 HSAMD::V3::MetadataVerifier Verifier(Strict); 269 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 270 return false; 271 272 std::string HSAMetadataString; 273 raw_string_ostream StrOS(HSAMetadataString); 274 HSAMetadataDoc.toYAML(StrOS); 275 276 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n'; 277 OS << StrOS.str() << '\n'; 278 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n'; 279 return true; 280 } 281 282 bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 283 const uint32_t Encoded_s_code_end = 0xbf9f0000; 284 const uint32_t Encoded_s_nop = 0xbf800000; 285 uint32_t Encoded_pad = Encoded_s_code_end; 286 287 // Instruction cache line size in bytes. 288 const unsigned Log2CacheLineSize = 6; 289 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 290 291 // Extra padding amount in bytes to support prefetch mode 3. 292 unsigned FillSize = 3 * CacheLineSize; 293 294 if (AMDGPU::isGFX90A(STI)) { 295 Encoded_pad = Encoded_s_nop; 296 FillSize = 16 * CacheLineSize; 297 } 298 299 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n'; 300 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n'; 301 return true; 302 } 303 304 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 305 const MCSubtargetInfo &STI, StringRef KernelName, 306 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 307 bool ReserveVCC, bool ReserveFlatScr) { 308 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 309 310 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 311 312 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 313 STREAM << "\t\t" << DIRECTIVE << " " \ 314 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 315 316 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 317 << '\n'; 318 OS << "\t\t.amdhsa_private_segment_fixed_size " 319 << KD.private_segment_fixed_size << '\n'; 320 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n'; 321 322 PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD, 323 compute_pgm_rsrc2, 324 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT); 325 326 if (!hasArchitectedFlatScratch(STI)) 327 PRINT_FIELD( 328 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 329 kernel_code_properties, 330 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 331 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 332 kernel_code_properties, 333 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 334 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 335 kernel_code_properties, 336 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 337 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 338 kernel_code_properties, 339 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 340 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 341 kernel_code_properties, 342 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 343 if (!hasArchitectedFlatScratch(STI)) 344 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 345 kernel_code_properties, 346 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 347 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 348 kernel_code_properties, 349 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 350 if (IVersion.Major >= 10) 351 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 352 kernel_code_properties, 353 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 354 PRINT_FIELD(OS, 355 (hasArchitectedFlatScratch(STI) 356 ? ".amdhsa_enable_private_segment" 357 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"), 358 KD, compute_pgm_rsrc2, 359 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 360 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 361 compute_pgm_rsrc2, 362 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 363 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 364 compute_pgm_rsrc2, 365 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 366 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 367 compute_pgm_rsrc2, 368 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 369 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 370 compute_pgm_rsrc2, 371 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 372 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 373 compute_pgm_rsrc2, 374 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 375 376 // These directives are required. 377 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 378 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 379 380 if (AMDGPU::isGFX90A(STI)) 381 OS << "\t\t.amdhsa_accum_offset " << 382 (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3, 383 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 384 << '\n'; 385 386 if (!ReserveVCC) 387 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 388 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI)) 389 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 390 391 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 392 switch (*HsaAbiVer) { 393 default: 394 break; 395 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 396 break; 397 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 398 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 399 if (getTargetID()->isXnackSupported()) 400 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n'; 401 break; 402 } 403 } 404 405 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 406 compute_pgm_rsrc1, 407 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 408 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 409 compute_pgm_rsrc1, 410 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 411 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 412 compute_pgm_rsrc1, 413 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 414 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 415 compute_pgm_rsrc1, 416 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 417 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 418 compute_pgm_rsrc1, 419 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 420 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 421 compute_pgm_rsrc1, 422 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 423 if (IVersion.Major >= 9) 424 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 425 compute_pgm_rsrc1, 426 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 427 if (AMDGPU::isGFX90A(STI)) 428 PRINT_FIELD(OS, ".amdhsa_tg_split", KD, 429 compute_pgm_rsrc3, 430 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 431 if (IVersion.Major >= 10) { 432 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 433 compute_pgm_rsrc1, 434 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 435 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 436 compute_pgm_rsrc1, 437 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 438 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 439 compute_pgm_rsrc1, 440 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 441 } 442 PRINT_FIELD( 443 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 444 compute_pgm_rsrc2, 445 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 446 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 447 compute_pgm_rsrc2, 448 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 449 PRINT_FIELD( 450 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 451 compute_pgm_rsrc2, 452 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 453 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 454 compute_pgm_rsrc2, 455 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 456 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 457 compute_pgm_rsrc2, 458 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 459 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 460 compute_pgm_rsrc2, 461 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 462 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 463 compute_pgm_rsrc2, 464 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 465 #undef PRINT_FIELD 466 467 OS << "\t.end_amdhsa_kernel\n"; 468 } 469 470 //===----------------------------------------------------------------------===// 471 // AMDGPUTargetELFStreamer 472 //===----------------------------------------------------------------------===// 473 474 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 475 const MCSubtargetInfo &STI) 476 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {} 477 478 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 479 return static_cast<MCELFStreamer &>(Streamer); 480 } 481 482 // A hook for emitting stuff at the end. 483 // We use it for emitting the accumulated PAL metadata as a .note record. 484 // The PAL metadata is reset after it is emitted. 485 void AMDGPUTargetELFStreamer::finish() { 486 MCAssembler &MCA = getStreamer().getAssembler(); 487 MCA.setELFHeaderEFlags(getEFlags()); 488 489 std::string Blob; 490 const char *Vendor = getPALMetadata()->getVendor(); 491 unsigned Type = getPALMetadata()->getType(); 492 getPALMetadata()->toBlob(Type, Blob); 493 if (Blob.empty()) 494 return; 495 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 496 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 497 498 // Reset the pal metadata so its data will not affect a compilation that 499 // reuses this object. 500 getPALMetadata()->reset(); 501 } 502 503 void AMDGPUTargetELFStreamer::EmitNote( 504 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 505 function_ref<void(MCELFStreamer &)> EmitDesc) { 506 auto &S = getStreamer(); 507 auto &Context = S.getContext(); 508 509 auto NameSZ = Name.size() + 1; 510 511 unsigned NoteFlags = 0; 512 // TODO Apparently, this is currently needed for OpenCL as mentioned in 513 // https://reviews.llvm.org/D74995 514 if (STI.getTargetTriple().getOS() == Triple::AMDHSA) 515 NoteFlags = ELF::SHF_ALLOC; 516 517 S.PushSection(); 518 S.SwitchSection( 519 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 520 S.emitInt32(NameSZ); // namesz 521 S.emitValue(DescSZ, 4); // descz 522 S.emitInt32(NoteType); // type 523 S.emitBytes(Name); // name 524 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 525 EmitDesc(S); // desc 526 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 527 S.PopSection(); 528 } 529 530 unsigned AMDGPUTargetELFStreamer::getEFlags() { 531 switch (STI.getTargetTriple().getArch()) { 532 default: 533 llvm_unreachable("Unsupported Arch"); 534 case Triple::r600: 535 return getEFlagsR600(); 536 case Triple::amdgcn: 537 return getEFlagsAMDGCN(); 538 } 539 } 540 541 unsigned AMDGPUTargetELFStreamer::getEFlagsR600() { 542 assert(STI.getTargetTriple().getArch() == Triple::r600); 543 544 return getElfMach(STI.getCPU()); 545 } 546 547 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() { 548 assert(STI.getTargetTriple().getArch() == Triple::amdgcn); 549 550 switch (STI.getTargetTriple().getOS()) { 551 default: 552 // TODO: Why are some tests have "mingw" listed as OS? 553 // llvm_unreachable("Unsupported OS"); 554 case Triple::UnknownOS: 555 return getEFlagsUnknownOS(); 556 case Triple::AMDHSA: 557 return getEFlagsAMDHSA(); 558 case Triple::AMDPAL: 559 return getEFlagsAMDPAL(); 560 case Triple::Mesa3D: 561 return getEFlagsMesa3D(); 562 } 563 } 564 565 unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() { 566 // TODO: Why are some tests have "mingw" listed as OS? 567 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS); 568 569 return getEFlagsV3(); 570 } 571 572 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() { 573 assert(STI.getTargetTriple().getOS() == Triple::AMDHSA); 574 575 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 576 switch (*HsaAbiVer) { 577 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 578 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 579 return getEFlagsV3(); 580 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 581 return getEFlagsV4(); 582 } 583 } 584 585 llvm_unreachable("HSA OS ABI Version identification must be defined"); 586 } 587 588 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() { 589 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL); 590 591 return getEFlagsV3(); 592 } 593 594 unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() { 595 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D); 596 597 return getEFlagsV3(); 598 } 599 600 unsigned AMDGPUTargetELFStreamer::getEFlagsV3() { 601 unsigned EFlagsV3 = 0; 602 603 // mach. 604 EFlagsV3 |= getElfMach(STI.getCPU()); 605 606 // xnack. 607 if (getTargetID()->isXnackOnOrAny()) 608 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3; 609 // sramecc. 610 if (getTargetID()->isSramEccOnOrAny()) 611 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3; 612 613 return EFlagsV3; 614 } 615 616 unsigned AMDGPUTargetELFStreamer::getEFlagsV4() { 617 unsigned EFlagsV4 = 0; 618 619 // mach. 620 EFlagsV4 |= getElfMach(STI.getCPU()); 621 622 // xnack. 623 switch (getTargetID()->getXnackSetting()) { 624 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 625 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4; 626 break; 627 case AMDGPU::IsaInfo::TargetIDSetting::Any: 628 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4; 629 break; 630 case AMDGPU::IsaInfo::TargetIDSetting::Off: 631 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4; 632 break; 633 case AMDGPU::IsaInfo::TargetIDSetting::On: 634 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4; 635 break; 636 } 637 // sramecc. 638 switch (getTargetID()->getSramEccSetting()) { 639 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 640 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4; 641 break; 642 case AMDGPU::IsaInfo::TargetIDSetting::Any: 643 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4; 644 break; 645 case AMDGPU::IsaInfo::TargetIDSetting::Off: 646 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4; 647 break; 648 case AMDGPU::IsaInfo::TargetIDSetting::On: 649 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4; 650 break; 651 } 652 653 return EFlagsV4; 654 } 655 656 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {} 657 658 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 659 uint32_t Major, uint32_t Minor) { 660 661 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 662 ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 663 OS.emitInt32(Major); 664 OS.emitInt32(Minor); 665 }); 666 } 667 668 void 669 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 670 uint32_t Minor, 671 uint32_t Stepping, 672 StringRef VendorName, 673 StringRef ArchName) { 674 uint16_t VendorNameSize = VendorName.size() + 1; 675 uint16_t ArchNameSize = ArchName.size() + 1; 676 677 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 678 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 679 VendorNameSize + ArchNameSize; 680 681 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 682 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 683 ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) { 684 OS.emitInt16(VendorNameSize); 685 OS.emitInt16(ArchNameSize); 686 OS.emitInt32(Major); 687 OS.emitInt32(Minor); 688 OS.emitInt32(Stepping); 689 OS.emitBytes(VendorName); 690 OS.emitInt8(0); // NULL terminate VendorName 691 OS.emitBytes(ArchName); 692 OS.emitInt8(0); // NULL terminte ArchName 693 }); 694 } 695 696 void 697 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 698 699 MCStreamer &OS = getStreamer(); 700 OS.PushSection(); 701 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 702 OS.PopSection(); 703 } 704 705 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 706 unsigned Type) { 707 MCSymbolELF *Symbol = cast<MCSymbolELF>( 708 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 709 Symbol->setType(Type); 710 } 711 712 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 713 Align Alignment) { 714 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 715 SymbolELF->setType(ELF::STT_OBJECT); 716 717 if (!SymbolELF->isBindingSet()) { 718 SymbolELF->setBinding(ELF::STB_GLOBAL); 719 SymbolELF->setExternal(true); 720 } 721 722 if (SymbolELF->declareCommon(Size, Alignment.value(), true)) { 723 report_fatal_error("Symbol: " + Symbol->getName() + 724 " redeclared as different type"); 725 } 726 727 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 728 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 729 } 730 731 bool AMDGPUTargetELFStreamer::EmitISAVersion() { 732 // Create two labels to mark the beginning and end of the desc field 733 // and a MCExpr to calculate the size of the desc field. 734 auto &Context = getContext(); 735 auto *DescBegin = Context.createTempSymbol(); 736 auto *DescEnd = Context.createTempSymbol(); 737 auto *DescSZ = MCBinaryExpr::createSub( 738 MCSymbolRefExpr::create(DescEnd, Context), 739 MCSymbolRefExpr::create(DescBegin, Context), Context); 740 741 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME, 742 [&](MCELFStreamer &OS) { 743 OS.emitLabel(DescBegin); 744 OS.emitBytes(getTargetID()->toString()); 745 OS.emitLabel(DescEnd); 746 }); 747 return true; 748 } 749 750 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 751 bool Strict) { 752 HSAMD::V3::MetadataVerifier Verifier(Strict); 753 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 754 return false; 755 756 std::string HSAMetadataString; 757 HSAMetadataDoc.writeToBlob(HSAMetadataString); 758 759 // Create two labels to mark the beginning and end of the desc field 760 // and a MCExpr to calculate the size of the desc field. 761 auto &Context = getContext(); 762 auto *DescBegin = Context.createTempSymbol(); 763 auto *DescEnd = Context.createTempSymbol(); 764 auto *DescSZ = MCBinaryExpr::createSub( 765 MCSymbolRefExpr::create(DescEnd, Context), 766 MCSymbolRefExpr::create(DescBegin, Context), Context); 767 768 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 769 [&](MCELFStreamer &OS) { 770 OS.emitLabel(DescBegin); 771 OS.emitBytes(HSAMetadataString); 772 OS.emitLabel(DescEnd); 773 }); 774 return true; 775 } 776 777 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 778 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 779 std::string HSAMetadataString; 780 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 781 return false; 782 783 // Create two labels to mark the beginning and end of the desc field 784 // and a MCExpr to calculate the size of the desc field. 785 auto &Context = getContext(); 786 auto *DescBegin = Context.createTempSymbol(); 787 auto *DescEnd = Context.createTempSymbol(); 788 auto *DescSZ = MCBinaryExpr::createSub( 789 MCSymbolRefExpr::create(DescEnd, Context), 790 MCSymbolRefExpr::create(DescBegin, Context), Context); 791 792 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA, 793 [&](MCELFStreamer &OS) { 794 OS.emitLabel(DescBegin); 795 OS.emitBytes(HSAMetadataString); 796 OS.emitLabel(DescEnd); 797 }); 798 return true; 799 } 800 801 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 802 const uint32_t Encoded_s_code_end = 0xbf9f0000; 803 const uint32_t Encoded_s_nop = 0xbf800000; 804 uint32_t Encoded_pad = Encoded_s_code_end; 805 806 // Instruction cache line size in bytes. 807 const unsigned Log2CacheLineSize = 6; 808 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 809 810 // Extra padding amount in bytes to support prefetch mode 3. 811 unsigned FillSize = 3 * CacheLineSize; 812 813 if (AMDGPU::isGFX90A(STI)) { 814 Encoded_pad = Encoded_s_nop; 815 FillSize = 16 * CacheLineSize; 816 } 817 818 MCStreamer &OS = getStreamer(); 819 OS.PushSection(); 820 OS.emitValueToAlignment(CacheLineSize, Encoded_pad, 4); 821 for (unsigned I = 0; I < FillSize; I += 4) 822 OS.emitInt32(Encoded_pad); 823 OS.PopSection(); 824 return true; 825 } 826 827 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 828 const MCSubtargetInfo &STI, StringRef KernelName, 829 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 830 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) { 831 auto &Streamer = getStreamer(); 832 auto &Context = Streamer.getContext(); 833 834 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 835 Context.getOrCreateSymbol(Twine(KernelName))); 836 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 837 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 838 839 // Copy kernel descriptor symbol's binding, other and visibility from the 840 // kernel code symbol. 841 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 842 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 843 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 844 // Kernel descriptor symbol's type and size are fixed. 845 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 846 KernelDescriptorSymbol->setSize( 847 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 848 849 // The visibility of the kernel code symbol must be protected or less to allow 850 // static relocations from the kernel descriptor to be used. 851 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 852 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 853 854 Streamer.emitLabel(KernelDescriptorSymbol); 855 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size); 856 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size); 857 Streamer.emitInt32(KernelDescriptor.kernarg_size); 858 859 for (uint8_t Res : KernelDescriptor.reserved0) 860 Streamer.emitInt8(Res); 861 862 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 863 // expression being created is: 864 // (start of kernel code) - (start of kernel descriptor) 865 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 866 Streamer.emitValue(MCBinaryExpr::createSub( 867 MCSymbolRefExpr::create( 868 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 869 MCSymbolRefExpr::create( 870 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 871 Context), 872 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 873 for (uint8_t Res : KernelDescriptor.reserved1) 874 Streamer.emitInt8(Res); 875 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3); 876 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1); 877 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2); 878 Streamer.emitInt16(KernelDescriptor.kernel_code_properties); 879 for (uint8_t Res : KernelDescriptor.reserved2) 880 Streamer.emitInt8(Res); 881 } 882