1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides AMDGPU specific target streamer methods. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "AMDGPUTargetStreamer.h" 15 #include "AMDGPU.h" 16 #include "SIDefines.h" 17 #include "Utils/AMDGPUBaseInfo.h" 18 #include "Utils/AMDKernelCodeTUtils.h" 19 #include "llvm/ADT/Twine.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/IR/Constants.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/IR/Metadata.h" 24 #include "llvm/IR/Module.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCELFStreamer.h" 27 #include "llvm/MC/MCObjectFileInfo.h" 28 #include "llvm/MC/MCSectionELF.h" 29 #include "llvm/Support/FormattedStream.h" 30 #include "llvm/Support/TargetParser.h" 31 32 namespace llvm { 33 #include "AMDGPUPTNote.h" 34 } 35 36 using namespace llvm; 37 using namespace llvm::AMDGPU; 38 39 //===----------------------------------------------------------------------===// 40 // AMDGPUTargetStreamer 41 //===----------------------------------------------------------------------===// 42 43 bool AMDGPUTargetStreamer::EmitHSAMetadata(StringRef HSAMetadataString) { 44 HSAMD::Metadata HSAMetadata; 45 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 46 return false; 47 48 return EmitHSAMetadata(HSAMetadata); 49 } 50 51 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 52 AMDGPU::GPUKind AK; 53 54 switch (ElfMach) { 55 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 56 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 57 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 58 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 59 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 60 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 61 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 62 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 63 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 64 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 65 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 66 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 67 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 68 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 69 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 70 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 71 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 72 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 73 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 74 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 75 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 76 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 77 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 78 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 79 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 80 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 81 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 82 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 87 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 88 } 89 90 StringRef GPUName = getArchNameAMDGCN(AK); 91 if (GPUName != "") 92 return GPUName; 93 return getArchNameR600(AK); 94 } 95 96 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 97 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 98 if (AK == AMDGPU::GPUKind::GK_NONE) 99 AK = parseArchR600(GPU); 100 101 switch (AK) { 102 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 103 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 104 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 105 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 106 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 107 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 108 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 109 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 110 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 111 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 112 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 113 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 114 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 115 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 116 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 117 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 118 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 119 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 120 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 121 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 122 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 123 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 124 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 125 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 126 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 127 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 128 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 129 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 130 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 131 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 132 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 133 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 134 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 135 } 136 137 llvm_unreachable("unknown GPU"); 138 } 139 140 //===----------------------------------------------------------------------===// 141 // AMDGPUTargetAsmStreamer 142 //===----------------------------------------------------------------------===// 143 144 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 145 formatted_raw_ostream &OS) 146 : AMDGPUTargetStreamer(S), OS(OS) { } 147 148 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) { 149 OS << "\t.amdgcn_target \"" << Target << "\"\n"; 150 } 151 152 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 153 uint32_t Major, uint32_t Minor) { 154 OS << "\t.hsa_code_object_version " << 155 Twine(Major) << "," << Twine(Minor) << '\n'; 156 } 157 158 void 159 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 160 uint32_t Minor, 161 uint32_t Stepping, 162 StringRef VendorName, 163 StringRef ArchName) { 164 OS << "\t.hsa_code_object_isa " << 165 Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) << 166 ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 167 168 } 169 170 void 171 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 172 OS << "\t.amd_kernel_code_t\n"; 173 dumpAmdKernelCode(&Header, OS, "\t\t"); 174 OS << "\t.end_amd_kernel_code_t\n"; 175 } 176 177 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 178 unsigned Type) { 179 switch (Type) { 180 default: llvm_unreachable("Invalid AMDGPU symbol type"); 181 case ELF::STT_AMDGPU_HSA_KERNEL: 182 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 183 break; 184 } 185 } 186 187 bool AMDGPUTargetAsmStreamer::EmitISAVersion(StringRef IsaVersionString) { 188 OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n"; 189 return true; 190 } 191 192 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 193 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 194 std::string HSAMetadataString; 195 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 196 return false; 197 198 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n'; 199 OS << HSAMetadataString << '\n'; 200 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n'; 201 return true; 202 } 203 204 bool AMDGPUTargetAsmStreamer::EmitPALMetadata( 205 const PALMD::Metadata &PALMetadata) { 206 std::string PALMetadataString; 207 if (PALMD::toString(PALMetadata, PALMetadataString)) 208 return false; 209 210 OS << '\t' << PALMD::AssemblerDirective << PALMetadataString << '\n'; 211 return true; 212 } 213 214 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 215 const MCSubtargetInfo &STI, StringRef KernelName, 216 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 217 bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) { 218 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 219 220 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 221 222 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 223 STREAM << "\t\t" << DIRECTIVE << " " \ 224 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 225 226 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 227 << '\n'; 228 OS << "\t\t.amdhsa_private_segment_fixed_size " 229 << KD.private_segment_fixed_size << '\n'; 230 231 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 232 kernel_code_properties, 233 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 234 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 235 kernel_code_properties, 236 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 237 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 238 kernel_code_properties, 239 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 240 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 241 kernel_code_properties, 242 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 243 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 244 kernel_code_properties, 245 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 246 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 247 kernel_code_properties, 248 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 249 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 250 kernel_code_properties, 251 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 252 PRINT_FIELD( 253 OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, 254 compute_pgm_rsrc2, 255 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET); 256 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 257 compute_pgm_rsrc2, 258 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 259 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 260 compute_pgm_rsrc2, 261 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 262 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 263 compute_pgm_rsrc2, 264 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 265 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 266 compute_pgm_rsrc2, 267 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 268 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 269 compute_pgm_rsrc2, 270 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 271 272 // These directives are required. 273 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 274 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 275 276 if (!ReserveVCC) 277 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 278 if (IVersion.Major >= 7 && !ReserveFlatScr) 279 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 280 if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI)) 281 OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n'; 282 283 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 284 compute_pgm_rsrc1, 285 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 286 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 287 compute_pgm_rsrc1, 288 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 289 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 290 compute_pgm_rsrc1, 291 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 292 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 293 compute_pgm_rsrc1, 294 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 295 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 296 compute_pgm_rsrc1, 297 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 298 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 299 compute_pgm_rsrc1, 300 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 301 if (IVersion.Major >= 9) 302 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 303 compute_pgm_rsrc1, 304 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 305 PRINT_FIELD( 306 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 307 compute_pgm_rsrc2, 308 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 309 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 310 compute_pgm_rsrc2, 311 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 312 PRINT_FIELD( 313 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 314 compute_pgm_rsrc2, 315 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 316 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 317 compute_pgm_rsrc2, 318 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 319 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 320 compute_pgm_rsrc2, 321 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 322 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 323 compute_pgm_rsrc2, 324 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 325 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 326 compute_pgm_rsrc2, 327 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 328 #undef PRINT_FIELD 329 330 OS << "\t.end_amdhsa_kernel\n"; 331 } 332 333 //===----------------------------------------------------------------------===// 334 // AMDGPUTargetELFStreamer 335 //===----------------------------------------------------------------------===// 336 337 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer( 338 MCStreamer &S, const MCSubtargetInfo &STI) 339 : AMDGPUTargetStreamer(S), Streamer(S) { 340 MCAssembler &MCA = getStreamer().getAssembler(); 341 unsigned EFlags = MCA.getELFHeaderEFlags(); 342 343 EFlags &= ~ELF::EF_AMDGPU_MACH; 344 EFlags |= getElfMach(STI.getCPU()); 345 346 EFlags &= ~ELF::EF_AMDGPU_XNACK; 347 if (AMDGPU::hasXNACK(STI)) 348 EFlags |= ELF::EF_AMDGPU_XNACK; 349 350 EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC; 351 if (AMDGPU::hasSRAMECC(STI)) 352 EFlags |= ELF::EF_AMDGPU_SRAM_ECC; 353 354 MCA.setELFHeaderEFlags(EFlags); 355 } 356 357 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 358 return static_cast<MCELFStreamer &>(Streamer); 359 } 360 361 void AMDGPUTargetELFStreamer::EmitAMDGPUNote( 362 const MCExpr *DescSZ, unsigned NoteType, 363 function_ref<void(MCELFStreamer &)> EmitDesc) { 364 auto &S = getStreamer(); 365 auto &Context = S.getContext(); 366 367 auto NameSZ = sizeof(ElfNote::NoteName); 368 369 S.PushSection(); 370 S.SwitchSection(Context.getELFSection( 371 ElfNote::SectionName, ELF::SHT_NOTE, ELF::SHF_ALLOC)); 372 S.EmitIntValue(NameSZ, 4); // namesz 373 S.EmitValue(DescSZ, 4); // descz 374 S.EmitIntValue(NoteType, 4); // type 375 S.EmitBytes(StringRef(ElfNote::NoteName, NameSZ)); // name 376 S.EmitValueToAlignment(4, 0, 1, 0); // padding 0 377 EmitDesc(S); // desc 378 S.EmitValueToAlignment(4, 0, 1, 0); // padding 0 379 S.PopSection(); 380 } 381 382 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {} 383 384 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 385 uint32_t Major, uint32_t Minor) { 386 387 EmitAMDGPUNote( 388 MCConstantExpr::create(8, getContext()), 389 ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION, 390 [&](MCELFStreamer &OS){ 391 OS.EmitIntValue(Major, 4); 392 OS.EmitIntValue(Minor, 4); 393 } 394 ); 395 } 396 397 void 398 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major, 399 uint32_t Minor, 400 uint32_t Stepping, 401 StringRef VendorName, 402 StringRef ArchName) { 403 uint16_t VendorNameSize = VendorName.size() + 1; 404 uint16_t ArchNameSize = ArchName.size() + 1; 405 406 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 407 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 408 VendorNameSize + ArchNameSize; 409 410 EmitAMDGPUNote( 411 MCConstantExpr::create(DescSZ, getContext()), 412 ElfNote::NT_AMDGPU_HSA_ISA, 413 [&](MCELFStreamer &OS) { 414 OS.EmitIntValue(VendorNameSize, 2); 415 OS.EmitIntValue(ArchNameSize, 2); 416 OS.EmitIntValue(Major, 4); 417 OS.EmitIntValue(Minor, 4); 418 OS.EmitIntValue(Stepping, 4); 419 OS.EmitBytes(VendorName); 420 OS.EmitIntValue(0, 1); // NULL terminate VendorName 421 OS.EmitBytes(ArchName); 422 OS.EmitIntValue(0, 1); // NULL terminte ArchName 423 } 424 ); 425 } 426 427 void 428 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 429 430 MCStreamer &OS = getStreamer(); 431 OS.PushSection(); 432 OS.EmitBytes(StringRef((const char*)&Header, sizeof(Header))); 433 OS.PopSection(); 434 } 435 436 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 437 unsigned Type) { 438 MCSymbolELF *Symbol = cast<MCSymbolELF>( 439 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 440 Symbol->setType(Type); 441 } 442 443 bool AMDGPUTargetELFStreamer::EmitISAVersion(StringRef IsaVersionString) { 444 // Create two labels to mark the beginning and end of the desc field 445 // and a MCExpr to calculate the size of the desc field. 446 auto &Context = getContext(); 447 auto *DescBegin = Context.createTempSymbol(); 448 auto *DescEnd = Context.createTempSymbol(); 449 auto *DescSZ = MCBinaryExpr::createSub( 450 MCSymbolRefExpr::create(DescEnd, Context), 451 MCSymbolRefExpr::create(DescBegin, Context), Context); 452 453 EmitAMDGPUNote( 454 DescSZ, 455 ELF::NT_AMD_AMDGPU_ISA, 456 [&](MCELFStreamer &OS) { 457 OS.EmitLabel(DescBegin); 458 OS.EmitBytes(IsaVersionString); 459 OS.EmitLabel(DescEnd); 460 } 461 ); 462 return true; 463 } 464 465 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 466 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 467 std::string HSAMetadataString; 468 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 469 return false; 470 471 // Create two labels to mark the beginning and end of the desc field 472 // and a MCExpr to calculate the size of the desc field. 473 auto &Context = getContext(); 474 auto *DescBegin = Context.createTempSymbol(); 475 auto *DescEnd = Context.createTempSymbol(); 476 auto *DescSZ = MCBinaryExpr::createSub( 477 MCSymbolRefExpr::create(DescEnd, Context), 478 MCSymbolRefExpr::create(DescBegin, Context), Context); 479 480 EmitAMDGPUNote( 481 DescSZ, 482 ELF::NT_AMD_AMDGPU_HSA_METADATA, 483 [&](MCELFStreamer &OS) { 484 OS.EmitLabel(DescBegin); 485 OS.EmitBytes(HSAMetadataString); 486 OS.EmitLabel(DescEnd); 487 } 488 ); 489 return true; 490 } 491 492 bool AMDGPUTargetELFStreamer::EmitPALMetadata( 493 const PALMD::Metadata &PALMetadata) { 494 EmitAMDGPUNote( 495 MCConstantExpr::create(PALMetadata.size() * sizeof(uint32_t), getContext()), 496 ELF::NT_AMD_AMDGPU_PAL_METADATA, 497 [&](MCELFStreamer &OS){ 498 for (auto I : PALMetadata) 499 OS.EmitIntValue(I, sizeof(uint32_t)); 500 } 501 ); 502 return true; 503 } 504 505 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 506 const MCSubtargetInfo &STI, StringRef KernelName, 507 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 508 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, 509 bool ReserveXNACK) { 510 auto &Streamer = getStreamer(); 511 auto &Context = Streamer.getContext(); 512 513 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 514 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 515 KernelDescriptorSymbol->setBinding(ELF::STB_GLOBAL); 516 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 517 KernelDescriptorSymbol->setSize( 518 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 519 520 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 521 Context.getOrCreateSymbol(Twine(KernelName))); 522 KernelCodeSymbol->setBinding(ELF::STB_LOCAL); 523 524 Streamer.EmitLabel(KernelDescriptorSymbol); 525 Streamer.EmitBytes(StringRef( 526 (const char*)&(KernelDescriptor), 527 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset))); 528 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 529 // expression being created is: 530 // (start of kernel code) - (start of kernel descriptor) 531 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 532 Streamer.EmitValue(MCBinaryExpr::createSub( 533 MCSymbolRefExpr::create( 534 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 535 MCSymbolRefExpr::create( 536 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 537 Context), 538 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 539 Streamer.EmitBytes(StringRef( 540 (const char*)&(KernelDescriptor) + 541 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) + 542 sizeof(KernelDescriptor.kernel_code_entry_byte_offset), 543 sizeof(KernelDescriptor) - 544 offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) - 545 sizeof(KernelDescriptor.kernel_code_entry_byte_offset))); 546 } 547