1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPUPTNote.h" 15 #include "AMDKernelCodeT.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/MC/MCAssembler.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCELFStreamer.h" 23 #include "llvm/MC/MCSectionELF.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/AMDGPUMetadata.h" 26 #include "llvm/Support/AMDHSAKernelDescriptor.h" 27 #include "llvm/Support/Casting.h" 28 #include "llvm/Support/FormattedStream.h" 29 #include "llvm/Support/TargetParser.h" 30 31 using namespace llvm; 32 using namespace llvm::AMDGPU; 33 34 //===----------------------------------------------------------------------===// 35 // AMDGPUTargetStreamer 36 //===----------------------------------------------------------------------===// 37 38 static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, 39 uint32_t &Stepping, bool Sramecc, bool Xnack) { 40 if (Major == 9 && Minor == 0) { 41 switch (Stepping) { 42 case 0: 43 case 2: 44 case 4: 45 case 6: 46 if (Xnack) 47 Stepping++; 48 } 49 } 50 } 51 52 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 53 HSAMD::Metadata HSAMetadata; 54 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 55 return false; 56 return EmitHSAMetadata(HSAMetadata); 57 } 58 59 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 60 msgpack::Document HSAMetadataDoc; 61 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 62 return false; 63 return EmitHSAMetadata(HSAMetadataDoc, false); 64 } 65 66 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 67 AMDGPU::GPUKind AK; 68 69 switch (ElfMach) { 70 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type"); 71 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 72 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 73 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 74 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 75 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 76 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 77 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 78 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 79 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 80 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 81 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 82 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 83 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 84 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 85 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 86 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break; 100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break; 108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break; 109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break; 113 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 114 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 115 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break; 116 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break; 117 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break; 118 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: AK = GK_GFX1035; break; 119 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 120 } 121 122 StringRef GPUName = getArchNameAMDGCN(AK); 123 if (GPUName != "") 124 return GPUName; 125 return getArchNameR600(AK); 126 } 127 128 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 129 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 130 if (AK == AMDGPU::GPUKind::GK_NONE) 131 AK = parseArchR600(GPU); 132 133 switch (AK) { 134 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 135 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 136 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 137 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 138 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 139 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 140 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 141 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 142 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 143 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 144 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 145 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 146 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 147 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 148 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 149 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 150 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 151 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 152 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602; 153 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 154 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 155 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 156 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 157 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 158 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705; 159 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 160 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 161 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 162 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805; 163 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 164 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 165 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 166 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 167 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 168 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 169 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 170 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A; 171 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C; 172 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 173 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 174 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 175 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013; 176 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 177 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 178 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032; 179 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033; 180 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034; 181 case GK_GFX1035: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035; 182 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 183 } 184 185 llvm_unreachable("unknown GPU"); 186 } 187 188 //===----------------------------------------------------------------------===// 189 // AMDGPUTargetAsmStreamer 190 //===----------------------------------------------------------------------===// 191 192 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 193 formatted_raw_ostream &OS) 194 : AMDGPUTargetStreamer(S), OS(OS) { } 195 196 // A hook for emitting stuff at the end. 197 // We use it for emitting the accumulated PAL metadata as directives. 198 // The PAL metadata is reset after it is emitted. 199 void AMDGPUTargetAsmStreamer::finish() { 200 std::string S; 201 getPALMetadata()->toString(S); 202 OS << S; 203 204 // Reset the pal metadata so its data will not affect a compilation that 205 // reuses this object. 206 getPALMetadata()->reset(); 207 } 208 209 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() { 210 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n"; 211 } 212 213 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 214 uint32_t Major, uint32_t Minor) { 215 OS << "\t.hsa_code_object_version " << 216 Twine(Major) << "," << Twine(Minor) << '\n'; 217 } 218 219 void 220 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 221 uint32_t Minor, 222 uint32_t Stepping, 223 StringRef VendorName, 224 StringRef ArchName) { 225 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 226 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << "," 227 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 228 } 229 230 void 231 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 232 OS << "\t.amd_kernel_code_t\n"; 233 dumpAmdKernelCode(&Header, OS, "\t\t"); 234 OS << "\t.end_amd_kernel_code_t\n"; 235 } 236 237 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 238 unsigned Type) { 239 switch (Type) { 240 default: llvm_unreachable("Invalid AMDGPU symbol type"); 241 case ELF::STT_AMDGPU_HSA_KERNEL: 242 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 243 break; 244 } 245 } 246 247 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 248 Align Alignment) { 249 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 250 << Alignment.value() << '\n'; 251 } 252 253 bool AMDGPUTargetAsmStreamer::EmitISAVersion() { 254 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n"; 255 return true; 256 } 257 258 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 259 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 260 std::string HSAMetadataString; 261 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 262 return false; 263 264 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n'; 265 OS << HSAMetadataString << '\n'; 266 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n'; 267 return true; 268 } 269 270 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 271 msgpack::Document &HSAMetadataDoc, bool Strict) { 272 HSAMD::V3::MetadataVerifier Verifier(Strict); 273 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 274 return false; 275 276 std::string HSAMetadataString; 277 raw_string_ostream StrOS(HSAMetadataString); 278 HSAMetadataDoc.toYAML(StrOS); 279 280 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n'; 281 OS << StrOS.str() << '\n'; 282 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n'; 283 return true; 284 } 285 286 bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 287 const uint32_t Encoded_s_code_end = 0xbf9f0000; 288 const uint32_t Encoded_s_nop = 0xbf800000; 289 uint32_t Encoded_pad = Encoded_s_code_end; 290 291 // Instruction cache line size in bytes. 292 const unsigned Log2CacheLineSize = 6; 293 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 294 295 // Extra padding amount in bytes to support prefetch mode 3. 296 unsigned FillSize = 3 * CacheLineSize; 297 298 if (AMDGPU::isGFX90A(STI)) { 299 Encoded_pad = Encoded_s_nop; 300 FillSize = 16 * CacheLineSize; 301 } 302 303 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n'; 304 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n'; 305 return true; 306 } 307 308 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 309 const MCSubtargetInfo &STI, StringRef KernelName, 310 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 311 bool ReserveVCC, bool ReserveFlatScr) { 312 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 313 314 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 315 316 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 317 STREAM << "\t\t" << DIRECTIVE << " " \ 318 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 319 320 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 321 << '\n'; 322 OS << "\t\t.amdhsa_private_segment_fixed_size " 323 << KD.private_segment_fixed_size << '\n'; 324 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n'; 325 326 PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD, 327 compute_pgm_rsrc2, 328 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT); 329 330 if (!hasArchitectedFlatScratch(STI)) 331 PRINT_FIELD( 332 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 333 kernel_code_properties, 334 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 335 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 336 kernel_code_properties, 337 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 338 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 339 kernel_code_properties, 340 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 341 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 342 kernel_code_properties, 343 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 344 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 345 kernel_code_properties, 346 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 347 if (!hasArchitectedFlatScratch(STI)) 348 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 349 kernel_code_properties, 350 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 351 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 352 kernel_code_properties, 353 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 354 if (IVersion.Major >= 10) 355 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 356 kernel_code_properties, 357 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 358 PRINT_FIELD(OS, 359 (hasArchitectedFlatScratch(STI) 360 ? ".amdhsa_enable_private_segment" 361 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"), 362 KD, compute_pgm_rsrc2, 363 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 364 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 365 compute_pgm_rsrc2, 366 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 367 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 368 compute_pgm_rsrc2, 369 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 370 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 371 compute_pgm_rsrc2, 372 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 373 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 374 compute_pgm_rsrc2, 375 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 376 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 377 compute_pgm_rsrc2, 378 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 379 380 // These directives are required. 381 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 382 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 383 384 if (AMDGPU::isGFX90A(STI)) 385 OS << "\t\t.amdhsa_accum_offset " << 386 (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3, 387 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 388 << '\n'; 389 390 if (!ReserveVCC) 391 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 392 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI)) 393 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 394 395 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 396 switch (*HsaAbiVer) { 397 default: 398 break; 399 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 400 break; 401 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 402 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 403 case ELF::ELFABIVERSION_AMDGPU_HSA_V5: 404 if (getTargetID()->isXnackSupported()) 405 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n'; 406 break; 407 } 408 } 409 410 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 411 compute_pgm_rsrc1, 412 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 413 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 414 compute_pgm_rsrc1, 415 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 416 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 417 compute_pgm_rsrc1, 418 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 419 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 420 compute_pgm_rsrc1, 421 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 422 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 423 compute_pgm_rsrc1, 424 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 425 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 426 compute_pgm_rsrc1, 427 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 428 if (IVersion.Major >= 9) 429 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 430 compute_pgm_rsrc1, 431 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 432 if (AMDGPU::isGFX90A(STI)) 433 PRINT_FIELD(OS, ".amdhsa_tg_split", KD, 434 compute_pgm_rsrc3, 435 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 436 if (IVersion.Major >= 10) { 437 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 438 compute_pgm_rsrc1, 439 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 440 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 441 compute_pgm_rsrc1, 442 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 443 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 444 compute_pgm_rsrc1, 445 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 446 } 447 PRINT_FIELD( 448 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 449 compute_pgm_rsrc2, 450 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 451 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 452 compute_pgm_rsrc2, 453 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 454 PRINT_FIELD( 455 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 456 compute_pgm_rsrc2, 457 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 458 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 459 compute_pgm_rsrc2, 460 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 461 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 462 compute_pgm_rsrc2, 463 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 464 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 465 compute_pgm_rsrc2, 466 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 467 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 468 compute_pgm_rsrc2, 469 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 470 #undef PRINT_FIELD 471 472 OS << "\t.end_amdhsa_kernel\n"; 473 } 474 475 //===----------------------------------------------------------------------===// 476 // AMDGPUTargetELFStreamer 477 //===----------------------------------------------------------------------===// 478 479 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 480 const MCSubtargetInfo &STI) 481 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {} 482 483 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 484 return static_cast<MCELFStreamer &>(Streamer); 485 } 486 487 // A hook for emitting stuff at the end. 488 // We use it for emitting the accumulated PAL metadata as a .note record. 489 // The PAL metadata is reset after it is emitted. 490 void AMDGPUTargetELFStreamer::finish() { 491 MCAssembler &MCA = getStreamer().getAssembler(); 492 MCA.setELFHeaderEFlags(getEFlags()); 493 494 std::string Blob; 495 const char *Vendor = getPALMetadata()->getVendor(); 496 unsigned Type = getPALMetadata()->getType(); 497 getPALMetadata()->toBlob(Type, Blob); 498 if (Blob.empty()) 499 return; 500 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 501 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 502 503 // Reset the pal metadata so its data will not affect a compilation that 504 // reuses this object. 505 getPALMetadata()->reset(); 506 } 507 508 void AMDGPUTargetELFStreamer::EmitNote( 509 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 510 function_ref<void(MCELFStreamer &)> EmitDesc) { 511 auto &S = getStreamer(); 512 auto &Context = S.getContext(); 513 514 auto NameSZ = Name.size() + 1; 515 516 unsigned NoteFlags = 0; 517 // TODO Apparently, this is currently needed for OpenCL as mentioned in 518 // https://reviews.llvm.org/D74995 519 if (STI.getTargetTriple().getOS() == Triple::AMDHSA) 520 NoteFlags = ELF::SHF_ALLOC; 521 522 S.PushSection(); 523 S.SwitchSection( 524 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 525 S.emitInt32(NameSZ); // namesz 526 S.emitValue(DescSZ, 4); // descz 527 S.emitInt32(NoteType); // type 528 S.emitBytes(Name); // name 529 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 530 EmitDesc(S); // desc 531 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 532 S.PopSection(); 533 } 534 535 unsigned AMDGPUTargetELFStreamer::getEFlags() { 536 switch (STI.getTargetTriple().getArch()) { 537 default: 538 llvm_unreachable("Unsupported Arch"); 539 case Triple::r600: 540 return getEFlagsR600(); 541 case Triple::amdgcn: 542 return getEFlagsAMDGCN(); 543 } 544 } 545 546 unsigned AMDGPUTargetELFStreamer::getEFlagsR600() { 547 assert(STI.getTargetTriple().getArch() == Triple::r600); 548 549 return getElfMach(STI.getCPU()); 550 } 551 552 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() { 553 assert(STI.getTargetTriple().getArch() == Triple::amdgcn); 554 555 switch (STI.getTargetTriple().getOS()) { 556 default: 557 // TODO: Why are some tests have "mingw" listed as OS? 558 // llvm_unreachable("Unsupported OS"); 559 case Triple::UnknownOS: 560 return getEFlagsUnknownOS(); 561 case Triple::AMDHSA: 562 return getEFlagsAMDHSA(); 563 case Triple::AMDPAL: 564 return getEFlagsAMDPAL(); 565 case Triple::Mesa3D: 566 return getEFlagsMesa3D(); 567 } 568 } 569 570 unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() { 571 // TODO: Why are some tests have "mingw" listed as OS? 572 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS); 573 574 return getEFlagsV3(); 575 } 576 577 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() { 578 assert(STI.getTargetTriple().getOS() == Triple::AMDHSA); 579 580 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 581 switch (*HsaAbiVer) { 582 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 583 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 584 return getEFlagsV3(); 585 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 586 case ELF::ELFABIVERSION_AMDGPU_HSA_V5: 587 return getEFlagsV4(); 588 } 589 } 590 591 llvm_unreachable("HSA OS ABI Version identification must be defined"); 592 } 593 594 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() { 595 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL); 596 597 return getEFlagsV3(); 598 } 599 600 unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() { 601 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D); 602 603 return getEFlagsV3(); 604 } 605 606 unsigned AMDGPUTargetELFStreamer::getEFlagsV3() { 607 unsigned EFlagsV3 = 0; 608 609 // mach. 610 EFlagsV3 |= getElfMach(STI.getCPU()); 611 612 // xnack. 613 if (getTargetID()->isXnackOnOrAny()) 614 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3; 615 // sramecc. 616 if (getTargetID()->isSramEccOnOrAny()) 617 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3; 618 619 return EFlagsV3; 620 } 621 622 unsigned AMDGPUTargetELFStreamer::getEFlagsV4() { 623 unsigned EFlagsV4 = 0; 624 625 // mach. 626 EFlagsV4 |= getElfMach(STI.getCPU()); 627 628 // xnack. 629 switch (getTargetID()->getXnackSetting()) { 630 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 631 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4; 632 break; 633 case AMDGPU::IsaInfo::TargetIDSetting::Any: 634 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4; 635 break; 636 case AMDGPU::IsaInfo::TargetIDSetting::Off: 637 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4; 638 break; 639 case AMDGPU::IsaInfo::TargetIDSetting::On: 640 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4; 641 break; 642 } 643 // sramecc. 644 switch (getTargetID()->getSramEccSetting()) { 645 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 646 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4; 647 break; 648 case AMDGPU::IsaInfo::TargetIDSetting::Any: 649 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4; 650 break; 651 case AMDGPU::IsaInfo::TargetIDSetting::Off: 652 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4; 653 break; 654 case AMDGPU::IsaInfo::TargetIDSetting::On: 655 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4; 656 break; 657 } 658 659 return EFlagsV4; 660 } 661 662 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {} 663 664 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 665 uint32_t Major, uint32_t Minor) { 666 667 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 668 ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 669 OS.emitInt32(Major); 670 OS.emitInt32(Minor); 671 }); 672 } 673 674 void 675 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 676 uint32_t Minor, 677 uint32_t Stepping, 678 StringRef VendorName, 679 StringRef ArchName) { 680 uint16_t VendorNameSize = VendorName.size() + 1; 681 uint16_t ArchNameSize = ArchName.size() + 1; 682 683 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 684 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 685 VendorNameSize + ArchNameSize; 686 687 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 688 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 689 ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) { 690 OS.emitInt16(VendorNameSize); 691 OS.emitInt16(ArchNameSize); 692 OS.emitInt32(Major); 693 OS.emitInt32(Minor); 694 OS.emitInt32(Stepping); 695 OS.emitBytes(VendorName); 696 OS.emitInt8(0); // NULL terminate VendorName 697 OS.emitBytes(ArchName); 698 OS.emitInt8(0); // NULL terminte ArchName 699 }); 700 } 701 702 void 703 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 704 705 MCStreamer &OS = getStreamer(); 706 OS.PushSection(); 707 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 708 OS.PopSection(); 709 } 710 711 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 712 unsigned Type) { 713 MCSymbolELF *Symbol = cast<MCSymbolELF>( 714 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 715 Symbol->setType(Type); 716 } 717 718 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 719 Align Alignment) { 720 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 721 SymbolELF->setType(ELF::STT_OBJECT); 722 723 if (!SymbolELF->isBindingSet()) { 724 SymbolELF->setBinding(ELF::STB_GLOBAL); 725 SymbolELF->setExternal(true); 726 } 727 728 if (SymbolELF->declareCommon(Size, Alignment.value(), true)) { 729 report_fatal_error("Symbol: " + Symbol->getName() + 730 " redeclared as different type"); 731 } 732 733 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 734 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 735 } 736 737 bool AMDGPUTargetELFStreamer::EmitISAVersion() { 738 // Create two labels to mark the beginning and end of the desc field 739 // and a MCExpr to calculate the size of the desc field. 740 auto &Context = getContext(); 741 auto *DescBegin = Context.createTempSymbol(); 742 auto *DescEnd = Context.createTempSymbol(); 743 auto *DescSZ = MCBinaryExpr::createSub( 744 MCSymbolRefExpr::create(DescEnd, Context), 745 MCSymbolRefExpr::create(DescBegin, Context), Context); 746 747 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME, 748 [&](MCELFStreamer &OS) { 749 OS.emitLabel(DescBegin); 750 OS.emitBytes(getTargetID()->toString()); 751 OS.emitLabel(DescEnd); 752 }); 753 return true; 754 } 755 756 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 757 bool Strict) { 758 HSAMD::V3::MetadataVerifier Verifier(Strict); 759 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 760 return false; 761 762 std::string HSAMetadataString; 763 HSAMetadataDoc.writeToBlob(HSAMetadataString); 764 765 // Create two labels to mark the beginning and end of the desc field 766 // and a MCExpr to calculate the size of the desc field. 767 auto &Context = getContext(); 768 auto *DescBegin = Context.createTempSymbol(); 769 auto *DescEnd = Context.createTempSymbol(); 770 auto *DescSZ = MCBinaryExpr::createSub( 771 MCSymbolRefExpr::create(DescEnd, Context), 772 MCSymbolRefExpr::create(DescBegin, Context), Context); 773 774 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 775 [&](MCELFStreamer &OS) { 776 OS.emitLabel(DescBegin); 777 OS.emitBytes(HSAMetadataString); 778 OS.emitLabel(DescEnd); 779 }); 780 return true; 781 } 782 783 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 784 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 785 std::string HSAMetadataString; 786 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 787 return false; 788 789 // Create two labels to mark the beginning and end of the desc field 790 // and a MCExpr to calculate the size of the desc field. 791 auto &Context = getContext(); 792 auto *DescBegin = Context.createTempSymbol(); 793 auto *DescEnd = Context.createTempSymbol(); 794 auto *DescSZ = MCBinaryExpr::createSub( 795 MCSymbolRefExpr::create(DescEnd, Context), 796 MCSymbolRefExpr::create(DescBegin, Context), Context); 797 798 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA, 799 [&](MCELFStreamer &OS) { 800 OS.emitLabel(DescBegin); 801 OS.emitBytes(HSAMetadataString); 802 OS.emitLabel(DescEnd); 803 }); 804 return true; 805 } 806 807 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 808 const uint32_t Encoded_s_code_end = 0xbf9f0000; 809 const uint32_t Encoded_s_nop = 0xbf800000; 810 uint32_t Encoded_pad = Encoded_s_code_end; 811 812 // Instruction cache line size in bytes. 813 const unsigned Log2CacheLineSize = 6; 814 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 815 816 // Extra padding amount in bytes to support prefetch mode 3. 817 unsigned FillSize = 3 * CacheLineSize; 818 819 if (AMDGPU::isGFX90A(STI)) { 820 Encoded_pad = Encoded_s_nop; 821 FillSize = 16 * CacheLineSize; 822 } 823 824 MCStreamer &OS = getStreamer(); 825 OS.PushSection(); 826 OS.emitValueToAlignment(CacheLineSize, Encoded_pad, 4); 827 for (unsigned I = 0; I < FillSize; I += 4) 828 OS.emitInt32(Encoded_pad); 829 OS.PopSection(); 830 return true; 831 } 832 833 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 834 const MCSubtargetInfo &STI, StringRef KernelName, 835 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 836 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) { 837 auto &Streamer = getStreamer(); 838 auto &Context = Streamer.getContext(); 839 840 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 841 Context.getOrCreateSymbol(Twine(KernelName))); 842 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 843 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 844 845 // Copy kernel descriptor symbol's binding, other and visibility from the 846 // kernel code symbol. 847 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 848 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 849 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 850 // Kernel descriptor symbol's type and size are fixed. 851 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 852 KernelDescriptorSymbol->setSize( 853 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 854 855 // The visibility of the kernel code symbol must be protected or less to allow 856 // static relocations from the kernel descriptor to be used. 857 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 858 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 859 860 Streamer.emitLabel(KernelDescriptorSymbol); 861 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size); 862 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size); 863 Streamer.emitInt32(KernelDescriptor.kernarg_size); 864 865 for (uint8_t Res : KernelDescriptor.reserved0) 866 Streamer.emitInt8(Res); 867 868 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 869 // expression being created is: 870 // (start of kernel code) - (start of kernel descriptor) 871 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 872 Streamer.emitValue(MCBinaryExpr::createSub( 873 MCSymbolRefExpr::create( 874 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 875 MCSymbolRefExpr::create( 876 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 877 Context), 878 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 879 for (uint8_t Res : KernelDescriptor.reserved1) 880 Streamer.emitInt8(Res); 881 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3); 882 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1); 883 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2); 884 Streamer.emitInt16(KernelDescriptor.kernel_code_properties); 885 for (uint8_t Res : KernelDescriptor.reserved2) 886 Streamer.emitInt8(Res); 887 } 888