1 //===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUSubtarget.h"
16 #include "R600ISelLowering.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineScheduler.h"
19 #include "SIFrameLowering.h"
20 #include "SIISelLowering.h"
21 #include "SIInstrInfo.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "amdgpu-subtarget"
29 
30 #define GET_SUBTARGETINFO_ENUM
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "AMDGPUGenSubtargetInfo.inc"
34 
35 AMDGPUSubtarget &
36 AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,
37                                                  StringRef GPU, StringRef FS) {
38   // Determine default and user-specified characteristics
39   // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
40   // enabled, but some instructions do not respect them and they run at the
41   // double precision rate, so don't enable by default.
42   //
43   // We want to be able to turn these off, but making this a subtarget feature
44   // for SI has the unhelpful behavior that it unsets everything else if you
45   // disable it.
46 
47   SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
48   if (isAmdHsaOS()) // Turn on FlatForGlobal for HSA.
49     FullFS += "+flat-for-global,";
50   FullFS += FS;
51 
52   ParseSubtargetFeatures(GPU, FullFS);
53 
54   // FIXME: I don't think think Evergreen has any useful support for
55   // denormals, but should be checked. Should we issue a warning somewhere
56   // if someone tries to enable these?
57   if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
58     FP32Denormals = false;
59     FP64Denormals = false;
60   }
61 
62   // Set defaults if needed.
63   if (MaxPrivateElementSize == 0)
64     MaxPrivateElementSize = 16;
65 
66   return *this;
67 }
68 
69 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
70                                  TargetMachine &TM)
71     : AMDGPUGenSubtargetInfo(TT, GPU, FS),
72       DumpCode(false), R600ALUInst(false), HasVertexCache(false),
73       TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
74       FP64Denormals(false), FP32Denormals(false), FPExceptions(false),
75       FastFMAF32(false), HalfRate64Ops(false), CaymanISA(false),
76       FlatAddressSpace(false), FlatForGlobal(false), EnableIRStructurizer(true),
77       EnablePromoteAlloca(false),
78       EnableIfCvt(true), EnableLoadStoreOpt(false),
79       EnableUnsafeDSOffsetFolding(false),
80       EnableXNACK(false),
81       WavefrontSize(0), CFALUBug(false),
82       LocalMemorySize(0), MaxPrivateElementSize(0),
83       EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
84       GCN1Encoding(false), GCN3Encoding(false), CIInsts(false),
85       HasSMemRealTime(false), Has16BitInsts(false),
86       LDSBankCount(0),
87       IsaVersion(ISAVersion0_0_0),
88       EnableSIScheduler(false), FrameLowering(nullptr),
89       InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
90 
91   initializeSubtargetDependencies(TT, GPU, FS);
92 
93   const unsigned MaxStackAlign = 64 * 16; // Maximum stack alignment (long16)
94 
95   if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
96     InstrInfo.reset(new R600InstrInfo(*this));
97     TLInfo.reset(new R600TargetLowering(TM, *this));
98 
99     // FIXME: Should have R600 specific FrameLowering
100     FrameLowering.reset(new AMDGPUFrameLowering(
101                           TargetFrameLowering::StackGrowsUp,
102                           MaxStackAlign,
103                           0));
104   } else {
105     InstrInfo.reset(new SIInstrInfo(*this));
106     TLInfo.reset(new SITargetLowering(TM, *this));
107     FrameLowering.reset(new SIFrameLowering(
108                           TargetFrameLowering::StackGrowsUp,
109                           MaxStackAlign,
110                           0));
111   }
112 }
113 
114 unsigned AMDGPUSubtarget::getStackEntrySize() const {
115   assert(getGeneration() <= NORTHERN_ISLANDS);
116   switch(getWavefrontSize()) {
117   case 16:
118     return 8;
119   case 32:
120     return hasCaymanISA() ? 4 : 8;
121   case 64:
122     return 4;
123   default:
124     llvm_unreachable("Illegal wavefront size.");
125   }
126 }
127 
128 unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
129   switch(getGeneration()) {
130   default: llvm_unreachable("ChipID unknown");
131   case SEA_ISLANDS: return 12;
132   }
133 }
134 
135 AMDGPU::IsaVersion AMDGPUSubtarget::getIsaVersion() const {
136   return AMDGPU::getIsaVersion(getFeatureBits());
137 }
138 
139 bool AMDGPUSubtarget::isVGPRSpillingEnabled(const Function& F) const {
140   return !AMDGPU::isShader(F.getCallingConv()) || EnableVGPRSpilling;
141 }
142 
143 void AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
144                                           MachineInstr *begin,
145                                           MachineInstr *end,
146                                           unsigned NumRegionInstrs) const {
147   if (getGeneration() >= SOUTHERN_ISLANDS) {
148 
149     // Track register pressure so the scheduler can try to decrease
150     // pressure once register usage is above the threshold defined by
151     // SIRegisterInfo::getRegPressureSetLimit()
152     Policy.ShouldTrackPressure = true;
153 
154     // Enabling both top down and bottom up scheduling seems to give us less
155     // register spills than just using one of these approaches on its own.
156     Policy.OnlyTopDown = false;
157     Policy.OnlyBottomUp = false;
158 
159     // Enabling ShouldTrackLaneMasks crashes the SI Machine Scheduler.
160     if (!enableSIScheduler())
161       Policy.ShouldTrackLaneMasks = true;
162   }
163 }
164 
165