1 //===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUSubtarget.h"
16 #include "R600ISelLowering.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineScheduler.h"
19 #include "SIISelLowering.h"
20 #include "SIInstrInfo.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/ADT/SmallString.h"
23 #include "llvm/CodeGen/MachineScheduler.h"
24 
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "amdgpu-subtarget"
28 
29 #define GET_SUBTARGETINFO_ENUM
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "AMDGPUGenSubtargetInfo.inc"
33 
34 AMDGPUSubtarget &
35 AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,
36                                                  StringRef GPU, StringRef FS) {
37   // Determine default and user-specified characteristics
38   // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
39   // enabled, but some instructions do not respect them and they run at the
40   // double precision rate, so don't enable by default.
41   //
42   // We want to be able to turn these off, but making this a subtarget feature
43   // for SI has the unhelpful behavior that it unsets everything else if you
44   // disable it.
45 
46   SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
47   FullFS += FS;
48 
49   if (GPU == "" && TT.getArch() == Triple::amdgcn)
50     GPU = "SI";
51 
52   ParseSubtargetFeatures(GPU, FullFS);
53 
54   // FIXME: I don't think think Evergreen has any useful support for
55   // denormals, but should be checked. Should we issue a warning somewhere
56   // if someone tries to enable these?
57   if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
58     FP32Denormals = false;
59     FP64Denormals = false;
60   }
61   return *this;
62 }
63 
64 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
65                                  TargetMachine &TM)
66     : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
67       DumpCode(false), R600ALUInst(false), HasVertexCache(false),
68       TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
69       FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
70       CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true),
71       EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false),
72       WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
73       EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
74       GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
75       IsaVersion(ISAVersion0_0_0),
76       FrameLowering(TargetFrameLowering::StackGrowsUp,
77                     64 * 16, // Maximum stack alignment (long16)
78                     0),
79       InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
80 
81   initializeSubtargetDependencies(TT, GPU, FS);
82 
83   if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
84     InstrInfo.reset(new R600InstrInfo(*this));
85     TLInfo.reset(new R600TargetLowering(TM, *this));
86   } else {
87     InstrInfo.reset(new SIInstrInfo(*this));
88     TLInfo.reset(new SITargetLowering(TM, *this));
89   }
90 }
91 
92 unsigned AMDGPUSubtarget::getStackEntrySize() const {
93   assert(getGeneration() <= NORTHERN_ISLANDS);
94   switch(getWavefrontSize()) {
95   case 16:
96     return 8;
97   case 32:
98     return hasCaymanISA() ? 4 : 8;
99   case 64:
100     return 4;
101   default:
102     llvm_unreachable("Illegal wavefront size.");
103   }
104 }
105 
106 unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
107   switch(getGeneration()) {
108   default: llvm_unreachable("ChipID unknown");
109   case SEA_ISLANDS: return 12;
110   }
111 }
112 
113 AMDGPU::IsaVersion AMDGPUSubtarget::getIsaVersion() const {
114   return AMDGPU::getIsaVersion(getFeatureBits());
115 }
116 
117 bool AMDGPUSubtarget::isVGPRSpillingEnabled(
118                                        const SIMachineFunctionInfo *MFI) const {
119   return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;
120 }
121 
122 void AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
123                                           MachineInstr *begin,
124                                           MachineInstr *end,
125                                           unsigned NumRegionInstrs) const {
126   if (getGeneration() >= SOUTHERN_ISLANDS) {
127 
128     // Track register pressure so the scheduler can try to decrease
129     // pressure once register usage is above the threshold defined by
130     // SIRegisterInfo::getRegPressureSetLimit()
131     Policy.ShouldTrackPressure = true;
132 
133     // Enabling both top down and bottom up scheduling seems to give us less
134     // register spills than just using one of these approaches on its own.
135     Policy.OnlyTopDown = false;
136     Policy.OnlyBottomUp = false;
137   }
138 }
139 
140