1 //===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUSubtarget.h"
16 #include "R600ISelLowering.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineScheduler.h"
19 #include "SIFrameLowering.h"
20 #include "SIISelLowering.h"
21 #include "SIInstrInfo.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "amdgpu-subtarget"
29 
30 #define GET_SUBTARGETINFO_ENUM
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "AMDGPUGenSubtargetInfo.inc"
34 
35 AMDGPUSubtarget &
36 AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,
37                                                  StringRef GPU, StringRef FS) {
38   // Determine default and user-specified characteristics
39   // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
40   // enabled, but some instructions do not respect them and they run at the
41   // double precision rate, so don't enable by default.
42   //
43   // We want to be able to turn these off, but making this a subtarget feature
44   // for SI has the unhelpful behavior that it unsets everything else if you
45   // disable it.
46 
47   SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
48   if (isAmdHsaOS()) // Turn on FlatForGlobal for HSA.
49     FullFS += "+flat-for-global,";
50   FullFS += FS;
51 
52   if (GPU == "" && TT.getArch() == Triple::amdgcn)
53     GPU = "SI";
54 
55   ParseSubtargetFeatures(GPU, FullFS);
56 
57   // FIXME: I don't think think Evergreen has any useful support for
58   // denormals, but should be checked. Should we issue a warning somewhere
59   // if someone tries to enable these?
60   if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
61     FP32Denormals = false;
62     FP64Denormals = false;
63   }
64   return *this;
65 }
66 
67 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
68                                  TargetMachine &TM)
69     : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU),
70       DumpCode(false), R600ALUInst(false), HasVertexCache(false),
71       TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
72       FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
73       HalfRate64Ops(false), CaymanISA(false), FlatAddressSpace(false),
74       FlatForGlobal(false), EnableIRStructurizer(true),
75       EnablePromoteAlloca(false),
76       EnableIfCvt(true), EnableLoadStoreOpt(false),
77       EnableUnsafeDSOffsetFolding(false),
78       EnableXNACK(false),
79       WavefrontSize(0), CFALUBug(false),
80       LocalMemorySize(0),
81       EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
82       GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
83       IsaVersion(ISAVersion0_0_0), EnableHugeScratchBuffer(false),
84       EnableSIScheduler(false), FrameLowering(nullptr),
85       InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
86 
87   initializeSubtargetDependencies(TT, GPU, FS);
88 
89   const unsigned MaxStackAlign = 64 * 16; // Maximum stack alignment (long16)
90 
91   if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
92     InstrInfo.reset(new R600InstrInfo(*this));
93     TLInfo.reset(new R600TargetLowering(TM, *this));
94 
95     // FIXME: Should have R600 specific FrameLowering
96     FrameLowering.reset(new AMDGPUFrameLowering(
97                           TargetFrameLowering::StackGrowsUp,
98                           MaxStackAlign,
99                           0));
100   } else {
101     InstrInfo.reset(new SIInstrInfo(*this));
102     TLInfo.reset(new SITargetLowering(TM, *this));
103     FrameLowering.reset(new SIFrameLowering(
104                           TargetFrameLowering::StackGrowsUp,
105                           MaxStackAlign,
106                           0));
107   }
108 }
109 
110 unsigned AMDGPUSubtarget::getStackEntrySize() const {
111   assert(getGeneration() <= NORTHERN_ISLANDS);
112   switch(getWavefrontSize()) {
113   case 16:
114     return 8;
115   case 32:
116     return hasCaymanISA() ? 4 : 8;
117   case 64:
118     return 4;
119   default:
120     llvm_unreachable("Illegal wavefront size.");
121   }
122 }
123 
124 unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
125   switch(getGeneration()) {
126   default: llvm_unreachable("ChipID unknown");
127   case SEA_ISLANDS: return 12;
128   }
129 }
130 
131 AMDGPU::IsaVersion AMDGPUSubtarget::getIsaVersion() const {
132   return AMDGPU::getIsaVersion(getFeatureBits());
133 }
134 
135 bool AMDGPUSubtarget::isVGPRSpillingEnabled(
136                                        const SIMachineFunctionInfo *MFI) const {
137   return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;
138 }
139 
140 void AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
141                                           MachineInstr *begin,
142                                           MachineInstr *end,
143                                           unsigned NumRegionInstrs) const {
144   if (getGeneration() >= SOUTHERN_ISLANDS) {
145 
146     // Track register pressure so the scheduler can try to decrease
147     // pressure once register usage is above the threshold defined by
148     // SIRegisterInfo::getRegPressureSetLimit()
149     Policy.ShouldTrackPressure = true;
150 
151     // Enabling both top down and bottom up scheduling seems to give us less
152     // register spills than just using one of these approaches on its own.
153     Policy.OnlyTopDown = false;
154     Policy.OnlyBottomUp = false;
155   }
156 }
157 
158