1 //===-- AMDGPUISelDAGToDAG.cpp - A dag to dag inst selector for AMDGPU ----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //==-----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Defines an instruction selector for the AMDGPU target.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPU.h"
16 #include "AMDGPUInstrInfo.h"
17 #include "AMDGPURegisterInfo.h"
18 #include "AMDGPUISelLowering.h" // For AMDGPUISD
19 #include "AMDGPUSubtarget.h"
20 #include "SIDefines.h"
21 #include "SIInstrInfo.h"
22 #include "SIRegisterInfo.h"
23 #include "SIISelLowering.h"
24 #include "SIMachineFunctionInfo.h"
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/ADT/StringRef.h"
28 #include "llvm/Analysis/ValueTracking.h"
29 #include "llvm/CodeGen/FunctionLoweringInfo.h"
30 #include "llvm/CodeGen/ISDOpcodes.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/MachineValueType.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/SelectionDAGISel.h"
36 #include "llvm/CodeGen/SelectionDAGNodes.h"
37 #include "llvm/CodeGen/ValueTypes.h"
38 #include "llvm/IR/BasicBlock.h"
39 #include "llvm/IR/Instruction.h"
40 #include "llvm/MC/MCInstrDesc.h"
41 #include "llvm/Support/Casting.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/MathExtras.h"
45 #include <cassert>
46 #include <cstdint>
47 #include <new>
48 #include <vector>
49 
50 using namespace llvm;
51 
52 namespace llvm {
53 
54 class R600InstrInfo;
55 
56 } // end namespace llvm
57 
58 //===----------------------------------------------------------------------===//
59 // Instruction Selector Implementation
60 //===----------------------------------------------------------------------===//
61 
62 namespace {
63 
64 /// AMDGPU specific code to select AMDGPU machine instructions for
65 /// SelectionDAG operations.
66 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
67   // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
68   // make the right decision when generating code for different targets.
69   const AMDGPUSubtarget *Subtarget;
70 
71 public:
72   explicit AMDGPUDAGToDAGISel(TargetMachine &TM, CodeGenOpt::Level OptLevel)
73       : SelectionDAGISel(TM, OptLevel) {}
74   ~AMDGPUDAGToDAGISel() override = default;
75 
76   bool runOnMachineFunction(MachineFunction &MF) override;
77   void Select(SDNode *N) override;
78   StringRef getPassName() const override;
79   void PostprocessISelDAG() override;
80 
81 private:
82   SDValue foldFrameIndex(SDValue N) const;
83   bool isInlineImmediate(const SDNode *N) const;
84   bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
85                    const R600InstrInfo *TII);
86   bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
87   bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
88 
89   bool isConstantLoad(const MemSDNode *N, int cbID) const;
90   bool isUniformBr(const SDNode *N) const;
91 
92   SDNode *glueCopyToM0(SDNode *N) const;
93 
94   const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
95   bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
96   bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
97                                        SDValue& Offset);
98   bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
99   bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
100   bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
101                        unsigned OffsetBits) const;
102   bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
103   bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
104                                  SDValue &Offset1) const;
105   bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
106                    SDValue &SOffset, SDValue &Offset, SDValue &Offen,
107                    SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
108                    SDValue &TFE) const;
109   bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
110                          SDValue &SOffset, SDValue &Offset, SDValue &GLC,
111                          SDValue &SLC, SDValue &TFE) const;
112   bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
113                          SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
114                          SDValue &SLC) const;
115   bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
116                           SDValue &SOffset, SDValue &ImmOffset) const;
117   bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
118                          SDValue &Offset, SDValue &GLC, SDValue &SLC,
119                          SDValue &TFE) const;
120   bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
121                          SDValue &Offset, SDValue &SLC) const;
122   bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
123                          SDValue &Offset) const;
124   bool SelectMUBUFConstant(SDValue Constant,
125                            SDValue &SOffset,
126                            SDValue &ImmOffset) const;
127   bool SelectMUBUFIntrinsicOffset(SDValue Offset, SDValue &SOffset,
128                                   SDValue &ImmOffset) const;
129   bool SelectMUBUFIntrinsicVOffset(SDValue Offset, SDValue &SOffset,
130                                    SDValue &ImmOffset, SDValue &VOffset) const;
131 
132   bool SelectFlat(SDValue Addr, SDValue &VAddr,
133                   SDValue &SLC, SDValue &TFE) const;
134 
135   bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
136                         bool &Imm) const;
137   bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
138                   bool &Imm) const;
139   bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
140   bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
141   bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
142   bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
143   bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
144   bool SelectSMRDBufferSgpr(SDValue Addr, SDValue &Offset) const;
145   bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
146   bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
147   bool SelectVOP3NoMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
148   bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
149                        SDValue &Clamp, SDValue &Omod) const;
150   bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
151                          SDValue &Clamp, SDValue &Omod) const;
152 
153   bool SelectVOP3Mods0Clamp(SDValue In, SDValue &Src, SDValue &SrcMods,
154                             SDValue &Omod) const;
155   bool SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, SDValue &SrcMods,
156                                  SDValue &Clamp,
157                                  SDValue &Omod) const;
158 
159   void SelectADD_SUB_I64(SDNode *N);
160   void SelectDIV_SCALE(SDNode *N);
161   void SelectFMA_W_CHAIN(SDNode *N);
162   void SelectFMUL_W_CHAIN(SDNode *N);
163 
164   SDNode *getS_BFE(unsigned Opcode, const SDLoc &DL, SDValue Val,
165                    uint32_t Offset, uint32_t Width);
166   void SelectS_BFEFromShifts(SDNode *N);
167   void SelectS_BFE(SDNode *N);
168   bool isCBranchSCC(const SDNode *N) const;
169   void SelectBRCOND(SDNode *N);
170   void SelectATOMIC_CMP_SWAP(SDNode *N);
171 
172   // Include the pieces autogenerated from the target description.
173 #include "AMDGPUGenDAGISel.inc"
174 };
175 
176 }  // end anonymous namespace
177 
178 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
179 // DAG, ready for instruction scheduling.
180 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM,
181                                         CodeGenOpt::Level OptLevel) {
182   return new AMDGPUDAGToDAGISel(TM, OptLevel);
183 }
184 
185 bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
186   Subtarget = &MF.getSubtarget<AMDGPUSubtarget>();
187   return SelectionDAGISel::runOnMachineFunction(MF);
188 }
189 
190 bool AMDGPUDAGToDAGISel::isInlineImmediate(const SDNode *N) const {
191   const SIInstrInfo *TII
192     = static_cast<const SISubtarget *>(Subtarget)->getInstrInfo();
193 
194   if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N))
195     return TII->isInlineConstant(C->getAPIntValue());
196 
197   if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N))
198     return TII->isInlineConstant(C->getValueAPF().bitcastToAPInt());
199 
200   return false;
201 }
202 
203 /// \brief Determine the register class for \p OpNo
204 /// \returns The register class of the virtual register that will be used for
205 /// the given operand number \OpNo or NULL if the register class cannot be
206 /// determined.
207 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
208                                                           unsigned OpNo) const {
209   if (!N->isMachineOpcode()) {
210     if (N->getOpcode() == ISD::CopyToReg) {
211       unsigned Reg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
212       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
213         MachineRegisterInfo &MRI = CurDAG->getMachineFunction().getRegInfo();
214         return MRI.getRegClass(Reg);
215       }
216 
217       const SIRegisterInfo *TRI
218         = static_cast<const SISubtarget *>(Subtarget)->getRegisterInfo();
219       return TRI->getPhysRegClass(Reg);
220     }
221 
222     return nullptr;
223   }
224 
225   switch (N->getMachineOpcode()) {
226   default: {
227     const MCInstrDesc &Desc =
228         Subtarget->getInstrInfo()->get(N->getMachineOpcode());
229     unsigned OpIdx = Desc.getNumDefs() + OpNo;
230     if (OpIdx >= Desc.getNumOperands())
231       return nullptr;
232     int RegClass = Desc.OpInfo[OpIdx].RegClass;
233     if (RegClass == -1)
234       return nullptr;
235 
236     return Subtarget->getRegisterInfo()->getRegClass(RegClass);
237   }
238   case AMDGPU::REG_SEQUENCE: {
239     unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
240     const TargetRegisterClass *SuperRC =
241         Subtarget->getRegisterInfo()->getRegClass(RCID);
242 
243     SDValue SubRegOp = N->getOperand(OpNo + 1);
244     unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
245     return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
246                                                               SubRegIdx);
247   }
248   }
249 }
250 
251 SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const {
252   if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
253       cast<MemSDNode>(N)->getAddressSpace() != AMDGPUAS::LOCAL_ADDRESS)
254     return N;
255 
256   const SITargetLowering& Lowering =
257       *static_cast<const SITargetLowering*>(getTargetLowering());
258 
259   // Write max value to m0 before each load operation
260 
261   SDValue M0 = Lowering.copyToM0(*CurDAG, CurDAG->getEntryNode(), SDLoc(N),
262                                  CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
263 
264   SDValue Glue = M0.getValue(1);
265 
266   SmallVector <SDValue, 8> Ops;
267   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
268      Ops.push_back(N->getOperand(i));
269   }
270   Ops.push_back(Glue);
271   CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops);
272 
273   return N;
274 }
275 
276 static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) {
277   switch (NumVectorElts) {
278   case 1:
279     return AMDGPU::SReg_32_XM0RegClassID;
280   case 2:
281     return AMDGPU::SReg_64RegClassID;
282   case 4:
283     return AMDGPU::SReg_128RegClassID;
284   case 8:
285     return AMDGPU::SReg_256RegClassID;
286   case 16:
287     return AMDGPU::SReg_512RegClassID;
288   }
289 
290   llvm_unreachable("invalid vector size");
291 }
292 
293 void AMDGPUDAGToDAGISel::Select(SDNode *N) {
294   unsigned int Opc = N->getOpcode();
295   if (N->isMachineOpcode()) {
296     N->setNodeId(-1);
297     return;   // Already selected.
298   }
299 
300   if (isa<AtomicSDNode>(N) ||
301       (Opc == AMDGPUISD::ATOMIC_INC || Opc == AMDGPUISD::ATOMIC_DEC))
302     N = glueCopyToM0(N);
303 
304   switch (Opc) {
305   default: break;
306   // We are selecting i64 ADD here instead of custom lower it during
307   // DAG legalization, so we can fold some i64 ADDs used for address
308   // calculation into the LOAD and STORE instructions.
309   case ISD::ADD:
310   case ISD::ADDC:
311   case ISD::ADDE:
312   case ISD::SUB:
313   case ISD::SUBC:
314   case ISD::SUBE: {
315     if (N->getValueType(0) != MVT::i64 ||
316         Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
317       break;
318 
319     SelectADD_SUB_I64(N);
320     return;
321   }
322   case AMDGPUISD::FMUL_W_CHAIN: {
323     SelectFMUL_W_CHAIN(N);
324     return;
325   }
326   case AMDGPUISD::FMA_W_CHAIN: {
327     SelectFMA_W_CHAIN(N);
328     return;
329   }
330 
331   case ISD::SCALAR_TO_VECTOR:
332   case AMDGPUISD::BUILD_VERTICAL_VECTOR:
333   case ISD::BUILD_VECTOR: {
334     unsigned RegClassID;
335     const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo();
336     EVT VT = N->getValueType(0);
337     unsigned NumVectorElts = VT.getVectorNumElements();
338     EVT EltVT = VT.getVectorElementType();
339     assert(EltVT.bitsEq(MVT::i32));
340     if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
341       RegClassID = selectSGPRVectorRegClassID(NumVectorElts);
342     } else {
343       // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
344       // that adds a 128 bits reg copy when going through TwoAddressInstructions
345       // pass. We want to avoid 128 bits copies as much as possible because they
346       // can't be bundled by our scheduler.
347       switch(NumVectorElts) {
348       case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
349       case 4:
350         if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
351           RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
352         else
353           RegClassID = AMDGPU::R600_Reg128RegClassID;
354         break;
355       default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
356       }
357     }
358 
359     SDLoc DL(N);
360     SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
361 
362     if (NumVectorElts == 1) {
363       CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT, N->getOperand(0),
364                            RegClass);
365       return;
366     }
367 
368     assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
369                                   "supported yet");
370     // 16 = Max Num Vector Elements
371     // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
372     // 1 = Vector Register Class
373     SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
374 
375     RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
376     bool IsRegSeq = true;
377     unsigned NOps = N->getNumOperands();
378     for (unsigned i = 0; i < NOps; i++) {
379       // XXX: Why is this here?
380       if (isa<RegisterSDNode>(N->getOperand(i))) {
381         IsRegSeq = false;
382         break;
383       }
384       RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
385       RegSeqArgs[1 + (2 * i) + 1] =
386               CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL,
387                                         MVT::i32);
388     }
389 
390     if (NOps != NumVectorElts) {
391       // Fill in the missing undef elements if this was a scalar_to_vector.
392       assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
393 
394       MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
395                                                      DL, EltVT);
396       for (unsigned i = NOps; i < NumVectorElts; ++i) {
397         RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
398         RegSeqArgs[1 + (2 * i) + 1] =
399           CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32);
400       }
401     }
402 
403     if (!IsRegSeq)
404       break;
405     CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(), RegSeqArgs);
406     return;
407   }
408   case ISD::BUILD_PAIR: {
409     SDValue RC, SubReg0, SubReg1;
410     if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
411       break;
412     }
413     SDLoc DL(N);
414     if (N->getValueType(0) == MVT::i128) {
415       RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32);
416       SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
417       SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
418     } else if (N->getValueType(0) == MVT::i64) {
419       RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32);
420       SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
421       SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
422     } else {
423       llvm_unreachable("Unhandled value type for BUILD_PAIR");
424     }
425     const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
426                             N->getOperand(1), SubReg1 };
427     ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
428                                           N->getValueType(0), Ops));
429     return;
430   }
431 
432   case ISD::Constant:
433   case ISD::ConstantFP: {
434     if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
435         N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
436       break;
437 
438     uint64_t Imm;
439     if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
440       Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
441     else {
442       ConstantSDNode *C = cast<ConstantSDNode>(N);
443       Imm = C->getZExtValue();
444     }
445 
446     SDLoc DL(N);
447     SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
448                                 CurDAG->getConstant(Imm & 0xFFFFFFFF, DL,
449                                                     MVT::i32));
450     SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
451                                 CurDAG->getConstant(Imm >> 32, DL, MVT::i32));
452     const SDValue Ops[] = {
453       CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
454       SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
455       SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
456     };
457 
458     ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
459                                           N->getValueType(0), Ops));
460     return;
461   }
462   case ISD::LOAD:
463   case ISD::STORE: {
464     N = glueCopyToM0(N);
465     break;
466   }
467 
468   case AMDGPUISD::BFE_I32:
469   case AMDGPUISD::BFE_U32: {
470     if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
471       break;
472 
473     // There is a scalar version available, but unlike the vector version which
474     // has a separate operand for the offset and width, the scalar version packs
475     // the width and offset into a single operand. Try to move to the scalar
476     // version if the offsets are constant, so that we can try to keep extended
477     // loads of kernel arguments in SGPRs.
478 
479     // TODO: Technically we could try to pattern match scalar bitshifts of
480     // dynamic values, but it's probably not useful.
481     ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
482     if (!Offset)
483       break;
484 
485     ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
486     if (!Width)
487       break;
488 
489     bool Signed = Opc == AMDGPUISD::BFE_I32;
490 
491     uint32_t OffsetVal = Offset->getZExtValue();
492     uint32_t WidthVal = Width->getZExtValue();
493 
494     ReplaceNode(N, getS_BFE(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32,
495                             SDLoc(N), N->getOperand(0), OffsetVal, WidthVal));
496     return;
497   }
498   case AMDGPUISD::DIV_SCALE: {
499     SelectDIV_SCALE(N);
500     return;
501   }
502   case ISD::CopyToReg: {
503     const SITargetLowering& Lowering =
504       *static_cast<const SITargetLowering*>(getTargetLowering());
505     Lowering.legalizeTargetIndependentNode(N, *CurDAG);
506     break;
507   }
508   case ISD::AND:
509   case ISD::SRL:
510   case ISD::SRA:
511   case ISD::SIGN_EXTEND_INREG:
512     if (N->getValueType(0) != MVT::i32 ||
513         Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
514       break;
515 
516     SelectS_BFE(N);
517     return;
518   case ISD::BRCOND:
519     SelectBRCOND(N);
520     return;
521 
522   case AMDGPUISD::ATOMIC_CMP_SWAP:
523     SelectATOMIC_CMP_SWAP(N);
524     return;
525   }
526 
527   SelectCode(N);
528 }
529 
530 bool AMDGPUDAGToDAGISel::isConstantLoad(const MemSDNode *N, int CbId) const {
531   if (!N->readMem())
532     return false;
533   if (CbId == -1)
534     return N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS;
535 
536   return N->getAddressSpace() == AMDGPUAS::CONSTANT_BUFFER_0 + CbId;
537 }
538 
539 bool AMDGPUDAGToDAGISel::isUniformBr(const SDNode *N) const {
540   const BasicBlock *BB = FuncInfo->MBB->getBasicBlock();
541   const Instruction *Term = BB->getTerminator();
542   return Term->getMetadata("amdgpu.uniform") ||
543          Term->getMetadata("structurizecfg.uniform");
544 }
545 
546 StringRef AMDGPUDAGToDAGISel::getPassName() const {
547   return "AMDGPU DAG->DAG Pattern Instruction Selection";
548 }
549 
550 //===----------------------------------------------------------------------===//
551 // Complex Patterns
552 //===----------------------------------------------------------------------===//
553 
554 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
555                                                          SDValue& IntPtr) {
556   if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
557     IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, SDLoc(Addr),
558                                        true);
559     return true;
560   }
561   return false;
562 }
563 
564 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
565     SDValue& BaseReg, SDValue &Offset) {
566   if (!isa<ConstantSDNode>(Addr)) {
567     BaseReg = Addr;
568     Offset = CurDAG->getIntPtrConstant(0, SDLoc(Addr), true);
569     return true;
570   }
571   return false;
572 }
573 
574 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
575                                            SDValue &Offset) {
576   ConstantSDNode *IMMOffset;
577 
578   if (Addr.getOpcode() == ISD::ADD
579       && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
580       && isInt<16>(IMMOffset->getZExtValue())) {
581 
582       Base = Addr.getOperand(0);
583       Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
584                                          MVT::i32);
585       return true;
586   // If the pointer address is constant, we can move it to the offset field.
587   } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
588              && isInt<16>(IMMOffset->getZExtValue())) {
589     Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
590                                   SDLoc(CurDAG->getEntryNode()),
591                                   AMDGPU::ZERO, MVT::i32);
592     Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
593                                        MVT::i32);
594     return true;
595   }
596 
597   // Default case, no offset
598   Base = Addr;
599   Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
600   return true;
601 }
602 
603 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
604                                             SDValue &Offset) {
605   ConstantSDNode *C;
606   SDLoc DL(Addr);
607 
608   if ((C = dyn_cast<ConstantSDNode>(Addr))) {
609     Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
610     Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
611   } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
612             (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
613     Base = Addr.getOperand(0);
614     Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
615   } else {
616     Base = Addr;
617     Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
618   }
619 
620   return true;
621 }
622 
623 void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
624   SDLoc DL(N);
625   SDValue LHS = N->getOperand(0);
626   SDValue RHS = N->getOperand(1);
627 
628   unsigned Opcode = N->getOpcode();
629   bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE);
630   bool ProduceCarry =
631       ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC;
632   bool IsAdd =
633       (Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE);
634 
635   SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
636   SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
637 
638   SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
639                                        DL, MVT::i32, LHS, Sub0);
640   SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
641                                        DL, MVT::i32, LHS, Sub1);
642 
643   SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
644                                        DL, MVT::i32, RHS, Sub0);
645   SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
646                                        DL, MVT::i32, RHS, Sub1);
647 
648   SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
649 
650   unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
651   unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
652 
653   SDNode *AddLo;
654   if (!ConsumeCarry) {
655     SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
656     AddLo = CurDAG->getMachineNode(Opc, DL, VTList, Args);
657   } else {
658     SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0), N->getOperand(2) };
659     AddLo = CurDAG->getMachineNode(CarryOpc, DL, VTList, Args);
660   }
661   SDValue AddHiArgs[] = {
662     SDValue(Hi0, 0),
663     SDValue(Hi1, 0),
664     SDValue(AddLo, 1)
665   };
666   SDNode *AddHi = CurDAG->getMachineNode(CarryOpc, DL, VTList, AddHiArgs);
667 
668   SDValue RegSequenceArgs[] = {
669     CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
670     SDValue(AddLo,0),
671     Sub0,
672     SDValue(AddHi,0),
673     Sub1,
674   };
675   SDNode *RegSequence = CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
676                                                MVT::i64, RegSequenceArgs);
677 
678   if (ProduceCarry) {
679     // Replace the carry-use
680     CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(AddHi, 1));
681   }
682 
683   // Replace the remaining uses.
684   CurDAG->ReplaceAllUsesWith(N, RegSequence);
685   CurDAG->RemoveDeadNode(N);
686 }
687 
688 void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
689   SDLoc SL(N);
690   //  src0_modifiers, src0,  src1_modifiers, src1, src2_modifiers, src2, clamp, omod
691   SDValue Ops[10];
692 
693   SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[6], Ops[7]);
694   SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
695   SelectVOP3Mods(N->getOperand(3), Ops[5], Ops[4]);
696   Ops[8] = N->getOperand(0);
697   Ops[9] = N->getOperand(4);
698 
699   CurDAG->SelectNodeTo(N, AMDGPU::V_FMA_F32, N->getVTList(), Ops);
700 }
701 
702 void AMDGPUDAGToDAGISel::SelectFMUL_W_CHAIN(SDNode *N) {
703   SDLoc SL(N);
704   //	src0_modifiers, src0,  src1_modifiers, src1, clamp, omod
705   SDValue Ops[8];
706 
707   SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[4], Ops[5]);
708   SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
709   Ops[6] = N->getOperand(0);
710   Ops[7] = N->getOperand(3);
711 
712   CurDAG->SelectNodeTo(N, AMDGPU::V_MUL_F32_e64, N->getVTList(), Ops);
713 }
714 
715 // We need to handle this here because tablegen doesn't support matching
716 // instructions with multiple outputs.
717 void AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
718   SDLoc SL(N);
719   EVT VT = N->getValueType(0);
720 
721   assert(VT == MVT::f32 || VT == MVT::f64);
722 
723   unsigned Opc
724     = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
725 
726   // src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp,
727   // omod
728   SDValue Ops[8];
729 
730   SelectVOP3Mods0(N->getOperand(0), Ops[1], Ops[0], Ops[6], Ops[7]);
731   SelectVOP3Mods(N->getOperand(1), Ops[3], Ops[2]);
732   SelectVOP3Mods(N->getOperand(2), Ops[5], Ops[4]);
733   CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
734 }
735 
736 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
737                                          unsigned OffsetBits) const {
738   if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
739       (OffsetBits == 8 && !isUInt<8>(Offset)))
740     return false;
741 
742   if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS ||
743       Subtarget->unsafeDSOffsetFoldingEnabled())
744     return true;
745 
746   // On Southern Islands instruction with a negative base value and an offset
747   // don't seem to work.
748   return CurDAG->SignBitIsZero(Base);
749 }
750 
751 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
752                                               SDValue &Offset) const {
753   SDLoc DL(Addr);
754   if (CurDAG->isBaseWithConstantOffset(Addr)) {
755     SDValue N0 = Addr.getOperand(0);
756     SDValue N1 = Addr.getOperand(1);
757     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
758     if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
759       // (add n0, c0)
760       Base = N0;
761       Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
762       return true;
763     }
764   } else if (Addr.getOpcode() == ISD::SUB) {
765     // sub C, x -> add (sub 0, x), C
766     if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
767       int64_t ByteOffset = C->getSExtValue();
768       if (isUInt<16>(ByteOffset)) {
769         SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
770 
771         // XXX - This is kind of hacky. Create a dummy sub node so we can check
772         // the known bits in isDSOffsetLegal. We need to emit the selected node
773         // here, so this is thrown away.
774         SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
775                                       Zero, Addr.getOperand(1));
776 
777         if (isDSOffsetLegal(Sub, ByteOffset, 16)) {
778           MachineSDNode *MachineSub
779             = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
780                                      Zero, Addr.getOperand(1));
781 
782           Base = SDValue(MachineSub, 0);
783           Offset = CurDAG->getTargetConstant(ByteOffset, DL, MVT::i16);
784           return true;
785         }
786       }
787     }
788   } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
789     // If we have a constant address, prefer to put the constant into the
790     // offset. This can save moves to load the constant address since multiple
791     // operations can share the zero base address register, and enables merging
792     // into read2 / write2 instructions.
793 
794     SDLoc DL(Addr);
795 
796     if (isUInt<16>(CAddr->getZExtValue())) {
797       SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
798       MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
799                                  DL, MVT::i32, Zero);
800       Base = SDValue(MovZero, 0);
801       Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16);
802       return true;
803     }
804   }
805 
806   // default case
807   Base = Addr;
808   Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i16);
809   return true;
810 }
811 
812 // TODO: If offset is too big, put low 16-bit into offset.
813 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
814                                                    SDValue &Offset0,
815                                                    SDValue &Offset1) const {
816   SDLoc DL(Addr);
817 
818   if (CurDAG->isBaseWithConstantOffset(Addr)) {
819     SDValue N0 = Addr.getOperand(0);
820     SDValue N1 = Addr.getOperand(1);
821     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
822     unsigned DWordOffset0 = C1->getZExtValue() / 4;
823     unsigned DWordOffset1 = DWordOffset0 + 1;
824     // (add n0, c0)
825     if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
826       Base = N0;
827       Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
828       Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
829       return true;
830     }
831   } else if (Addr.getOpcode() == ISD::SUB) {
832     // sub C, x -> add (sub 0, x), C
833     if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
834       unsigned DWordOffset0 = C->getZExtValue() / 4;
835       unsigned DWordOffset1 = DWordOffset0 + 1;
836 
837       if (isUInt<8>(DWordOffset0)) {
838         SDLoc DL(Addr);
839         SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
840 
841         // XXX - This is kind of hacky. Create a dummy sub node so we can check
842         // the known bits in isDSOffsetLegal. We need to emit the selected node
843         // here, so this is thrown away.
844         SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
845                                       Zero, Addr.getOperand(1));
846 
847         if (isDSOffsetLegal(Sub, DWordOffset1, 8)) {
848           MachineSDNode *MachineSub
849             = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
850                                      Zero, Addr.getOperand(1));
851 
852           Base = SDValue(MachineSub, 0);
853           Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
854           Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
855           return true;
856         }
857       }
858     }
859   } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
860     unsigned DWordOffset0 = CAddr->getZExtValue() / 4;
861     unsigned DWordOffset1 = DWordOffset0 + 1;
862     assert(4 * DWordOffset0 == CAddr->getZExtValue());
863 
864     if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) {
865       SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
866       MachineSDNode *MovZero
867         = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
868                                  DL, MVT::i32, Zero);
869       Base = SDValue(MovZero, 0);
870       Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
871       Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
872       return true;
873     }
874   }
875 
876   // default case
877 
878   // FIXME: This is broken on SI where we still need to check if the base
879   // pointer is positive here.
880   Base = Addr;
881   Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8);
882   Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8);
883   return true;
884 }
885 
886 static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
887   return isUInt<12>(Imm->getZExtValue());
888 }
889 
890 bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
891                                      SDValue &VAddr, SDValue &SOffset,
892                                      SDValue &Offset, SDValue &Offen,
893                                      SDValue &Idxen, SDValue &Addr64,
894                                      SDValue &GLC, SDValue &SLC,
895                                      SDValue &TFE) const {
896   // Subtarget prefers to use flat instruction
897   if (Subtarget->useFlatForGlobal())
898     return false;
899 
900   SDLoc DL(Addr);
901 
902   if (!GLC.getNode())
903     GLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
904   if (!SLC.getNode())
905     SLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
906   TFE = CurDAG->getTargetConstant(0, DL, MVT::i1);
907 
908   Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1);
909   Offen = CurDAG->getTargetConstant(0, DL, MVT::i1);
910   Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1);
911   SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
912 
913   if (CurDAG->isBaseWithConstantOffset(Addr)) {
914     SDValue N0 = Addr.getOperand(0);
915     SDValue N1 = Addr.getOperand(1);
916     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
917 
918     if (N0.getOpcode() == ISD::ADD) {
919       // (add (add N2, N3), C1) -> addr64
920       SDValue N2 = N0.getOperand(0);
921       SDValue N3 = N0.getOperand(1);
922       Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
923       Ptr = N2;
924       VAddr = N3;
925     } else {
926       // (add N0, C1) -> offset
927       VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
928       Ptr = N0;
929     }
930 
931     if (isLegalMUBUFImmOffset(C1)) {
932       Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
933       return true;
934     }
935 
936     if (isUInt<32>(C1->getZExtValue())) {
937       // Illegal offset, store it in soffset.
938       Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
939       SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
940                    CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)),
941                         0);
942       return true;
943     }
944   }
945 
946   if (Addr.getOpcode() == ISD::ADD) {
947     // (add N0, N1) -> addr64
948     SDValue N0 = Addr.getOperand(0);
949     SDValue N1 = Addr.getOperand(1);
950     Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
951     Ptr = N0;
952     VAddr = N1;
953     Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
954     return true;
955   }
956 
957   // default case -> offset
958   VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
959   Ptr = Addr;
960   Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
961 
962   return true;
963 }
964 
965 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
966                                            SDValue &VAddr, SDValue &SOffset,
967                                            SDValue &Offset, SDValue &GLC,
968                                            SDValue &SLC, SDValue &TFE) const {
969   SDValue Ptr, Offen, Idxen, Addr64;
970 
971   // addr64 bit was removed for volcanic islands.
972   if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
973     return false;
974 
975   if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
976               GLC, SLC, TFE))
977     return false;
978 
979   ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
980   if (C->getSExtValue()) {
981     SDLoc DL(Addr);
982 
983     const SITargetLowering& Lowering =
984       *static_cast<const SITargetLowering*>(getTargetLowering());
985 
986     SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
987     return true;
988   }
989 
990   return false;
991 }
992 
993 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
994                                            SDValue &VAddr, SDValue &SOffset,
995                                            SDValue &Offset,
996                                            SDValue &SLC) const {
997   SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1);
998   SDValue GLC, TFE;
999 
1000   return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE);
1001 }
1002 
1003 SDValue AMDGPUDAGToDAGISel::foldFrameIndex(SDValue N) const {
1004   if (auto FI = dyn_cast<FrameIndexSDNode>(N))
1005     return CurDAG->getTargetFrameIndex(FI->getIndex(), FI->getValueType(0));
1006   return N;
1007 }
1008 
1009 bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
1010                                             SDValue &VAddr, SDValue &SOffset,
1011                                             SDValue &ImmOffset) const {
1012 
1013   SDLoc DL(Addr);
1014   MachineFunction &MF = CurDAG->getMachineFunction();
1015   const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1016 
1017   Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
1018   SOffset = CurDAG->getRegister(Info->getScratchWaveOffsetReg(), MVT::i32);
1019 
1020   // (add n0, c1)
1021   if (CurDAG->isBaseWithConstantOffset(Addr)) {
1022     SDValue N0 = Addr.getOperand(0);
1023     SDValue N1 = Addr.getOperand(1);
1024 
1025     // Offsets in vaddr must be positive.
1026     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1027     if (isLegalMUBUFImmOffset(C1)) {
1028       VAddr = foldFrameIndex(N0);
1029       ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1030       return true;
1031     }
1032   }
1033 
1034   // (node)
1035   VAddr = foldFrameIndex(Addr);
1036   ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1037   return true;
1038 }
1039 
1040 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1041                                            SDValue &SOffset, SDValue &Offset,
1042                                            SDValue &GLC, SDValue &SLC,
1043                                            SDValue &TFE) const {
1044   SDValue Ptr, VAddr, Offen, Idxen, Addr64;
1045   const SIInstrInfo *TII =
1046     static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1047 
1048   if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1049               GLC, SLC, TFE))
1050     return false;
1051 
1052   if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
1053       !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
1054       !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
1055     uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
1056                     APInt::getAllOnesValue(32).getZExtValue(); // Size
1057     SDLoc DL(Addr);
1058 
1059     const SITargetLowering& Lowering =
1060       *static_cast<const SITargetLowering*>(getTargetLowering());
1061 
1062     SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
1063     return true;
1064   }
1065   return false;
1066 }
1067 
1068 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1069                                            SDValue &Soffset, SDValue &Offset
1070                                            ) const {
1071   SDValue GLC, SLC, TFE;
1072 
1073   return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1074 }
1075 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1076                                            SDValue &Soffset, SDValue &Offset,
1077                                            SDValue &SLC) const {
1078   SDValue GLC, TFE;
1079 
1080   return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1081 }
1082 
1083 bool AMDGPUDAGToDAGISel::SelectMUBUFConstant(SDValue Constant,
1084                                              SDValue &SOffset,
1085                                              SDValue &ImmOffset) const {
1086   SDLoc DL(Constant);
1087   uint32_t Imm = cast<ConstantSDNode>(Constant)->getZExtValue();
1088   uint32_t Overflow = 0;
1089 
1090   if (Imm >= 4096) {
1091     if (Imm <= 4095 + 64) {
1092       // Use an SOffset inline constant for 1..64
1093       Overflow = Imm - 4095;
1094       Imm = 4095;
1095     } else {
1096       // Try to keep the same value in SOffset for adjacent loads, so that
1097       // the corresponding register contents can be re-used.
1098       //
1099       // Load values with all low-bits set into SOffset, so that a larger
1100       // range of values can be covered using s_movk_i32
1101       uint32_t High = (Imm + 1) & ~4095;
1102       uint32_t Low = (Imm + 1) & 4095;
1103       Imm = Low;
1104       Overflow = High - 1;
1105     }
1106   }
1107 
1108   // There is a hardware bug in SI and CI which prevents address clamping in
1109   // MUBUF instructions from working correctly with SOffsets. The immediate
1110   // offset is unaffected.
1111   if (Overflow > 0 &&
1112       Subtarget->getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS)
1113     return false;
1114 
1115   ImmOffset = CurDAG->getTargetConstant(Imm, DL, MVT::i16);
1116 
1117   if (Overflow <= 64)
1118     SOffset = CurDAG->getTargetConstant(Overflow, DL, MVT::i32);
1119   else
1120     SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1121                       CurDAG->getTargetConstant(Overflow, DL, MVT::i32)),
1122                       0);
1123 
1124   return true;
1125 }
1126 
1127 bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicOffset(SDValue Offset,
1128                                                     SDValue &SOffset,
1129                                                     SDValue &ImmOffset) const {
1130   SDLoc DL(Offset);
1131 
1132   if (!isa<ConstantSDNode>(Offset))
1133     return false;
1134 
1135   return SelectMUBUFConstant(Offset, SOffset, ImmOffset);
1136 }
1137 
1138 bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicVOffset(SDValue Offset,
1139                                                      SDValue &SOffset,
1140                                                      SDValue &ImmOffset,
1141                                                      SDValue &VOffset) const {
1142   SDLoc DL(Offset);
1143 
1144   // Don't generate an unnecessary voffset for constant offsets.
1145   if (isa<ConstantSDNode>(Offset)) {
1146     SDValue Tmp1, Tmp2;
1147 
1148     // When necessary, use a voffset in <= CI anyway to work around a hardware
1149     // bug.
1150     if (Subtarget->getGeneration() > AMDGPUSubtarget::SEA_ISLANDS ||
1151         SelectMUBUFConstant(Offset, Tmp1, Tmp2))
1152       return false;
1153   }
1154 
1155   if (CurDAG->isBaseWithConstantOffset(Offset)) {
1156     SDValue N0 = Offset.getOperand(0);
1157     SDValue N1 = Offset.getOperand(1);
1158     if (cast<ConstantSDNode>(N1)->getSExtValue() >= 0 &&
1159         SelectMUBUFConstant(N1, SOffset, ImmOffset)) {
1160       VOffset = N0;
1161       return true;
1162     }
1163   }
1164 
1165   SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
1166   ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1167   VOffset = Offset;
1168 
1169   return true;
1170 }
1171 
1172 bool AMDGPUDAGToDAGISel::SelectFlat(SDValue Addr,
1173                                     SDValue &VAddr,
1174                                     SDValue &SLC,
1175                                     SDValue &TFE) const {
1176   VAddr = Addr;
1177   TFE = SLC = CurDAG->getTargetConstant(0, SDLoc(), MVT::i1);
1178   return true;
1179 }
1180 
1181 ///
1182 /// \param EncodedOffset This is the immediate value that will be encoded
1183 ///        directly into the instruction.  On SI/CI the \p EncodedOffset
1184 ///        will be in units of dwords and on VI+ it will be units of bytes.
1185 static bool isLegalSMRDImmOffset(const AMDGPUSubtarget *ST,
1186                                  int64_t EncodedOffset) {
1187   return ST->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS ?
1188      isUInt<8>(EncodedOffset) : isUInt<20>(EncodedOffset);
1189 }
1190 
1191 bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
1192                                           SDValue &Offset, bool &Imm) const {
1193 
1194   // FIXME: Handle non-constant offsets.
1195   ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode);
1196   if (!C)
1197     return false;
1198 
1199   SDLoc SL(ByteOffsetNode);
1200   AMDGPUSubtarget::Generation Gen = Subtarget->getGeneration();
1201   int64_t ByteOffset = C->getSExtValue();
1202   int64_t EncodedOffset = Gen < AMDGPUSubtarget::VOLCANIC_ISLANDS ?
1203       ByteOffset >> 2 : ByteOffset;
1204 
1205   if (isLegalSMRDImmOffset(Subtarget, EncodedOffset)) {
1206     Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1207     Imm = true;
1208     return true;
1209   }
1210 
1211   if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset))
1212     return false;
1213 
1214   if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) {
1215     // 32-bit Immediates are supported on Sea Islands.
1216     Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1217   } else {
1218     SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
1219     Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32,
1220                                             C32Bit), 0);
1221   }
1222   Imm = false;
1223   return true;
1224 }
1225 
1226 bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
1227                                      SDValue &Offset, bool &Imm) const {
1228   SDLoc SL(Addr);
1229   if (CurDAG->isBaseWithConstantOffset(Addr)) {
1230     SDValue N0 = Addr.getOperand(0);
1231     SDValue N1 = Addr.getOperand(1);
1232 
1233     if (SelectSMRDOffset(N1, Offset, Imm)) {
1234       SBase = N0;
1235       return true;
1236     }
1237   }
1238   SBase = Addr;
1239   Offset = CurDAG->getTargetConstant(0, SL, MVT::i32);
1240   Imm = true;
1241   return true;
1242 }
1243 
1244 bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase,
1245                                        SDValue &Offset) const {
1246   bool Imm;
1247   return SelectSMRD(Addr, SBase, Offset, Imm) && Imm;
1248 }
1249 
1250 bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase,
1251                                          SDValue &Offset) const {
1252 
1253   if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1254     return false;
1255 
1256   bool Imm;
1257   if (!SelectSMRD(Addr, SBase, Offset, Imm))
1258     return false;
1259 
1260   return !Imm && isa<ConstantSDNode>(Offset);
1261 }
1262 
1263 bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
1264                                         SDValue &Offset) const {
1265   bool Imm;
1266   return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm &&
1267          !isa<ConstantSDNode>(Offset);
1268 }
1269 
1270 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
1271                                              SDValue &Offset) const {
1272   bool Imm;
1273   return SelectSMRDOffset(Addr, Offset, Imm) && Imm;
1274 }
1275 
1276 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr,
1277                                                SDValue &Offset) const {
1278   if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1279     return false;
1280 
1281   bool Imm;
1282   if (!SelectSMRDOffset(Addr, Offset, Imm))
1283     return false;
1284 
1285   return !Imm && isa<ConstantSDNode>(Offset);
1286 }
1287 
1288 bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
1289                                               SDValue &Offset) const {
1290   bool Imm;
1291   return SelectSMRDOffset(Addr, Offset, Imm) && !Imm &&
1292          !isa<ConstantSDNode>(Offset);
1293 }
1294 
1295 bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
1296                                             SDValue &Base,
1297                                             SDValue &Offset) const {
1298   SDLoc DL(Index);
1299 
1300   if (CurDAG->isBaseWithConstantOffset(Index)) {
1301     SDValue N0 = Index.getOperand(0);
1302     SDValue N1 = Index.getOperand(1);
1303     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1304 
1305     // (add n0, c0)
1306     Base = N0;
1307     Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32);
1308     return true;
1309   }
1310 
1311   if (isa<ConstantSDNode>(Index))
1312     return false;
1313 
1314   Base = Index;
1315   Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
1316   return true;
1317 }
1318 
1319 SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, const SDLoc &DL,
1320                                      SDValue Val, uint32_t Offset,
1321                                      uint32_t Width) {
1322   // Transformation function, pack the offset and width of a BFE into
1323   // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
1324   // source, bits [5:0] contain the offset and bits [22:16] the width.
1325   uint32_t PackedVal = Offset | (Width << 16);
1326   SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32);
1327 
1328   return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst);
1329 }
1330 
1331 void AMDGPUDAGToDAGISel::SelectS_BFEFromShifts(SDNode *N) {
1332   // "(a << b) srl c)" ---> "BFE_U32 a, (c-b), (32-c)
1333   // "(a << b) sra c)" ---> "BFE_I32 a, (c-b), (32-c)
1334   // Predicate: 0 < b <= c < 32
1335 
1336   const SDValue &Shl = N->getOperand(0);
1337   ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
1338   ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1339 
1340   if (B && C) {
1341     uint32_t BVal = B->getZExtValue();
1342     uint32_t CVal = C->getZExtValue();
1343 
1344     if (0 < BVal && BVal <= CVal && CVal < 32) {
1345       bool Signed = N->getOpcode() == ISD::SRA;
1346       unsigned Opcode = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;
1347 
1348       ReplaceNode(N, getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0), CVal - BVal,
1349                               32 - CVal));
1350       return;
1351     }
1352   }
1353   SelectCode(N);
1354 }
1355 
1356 void AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
1357   switch (N->getOpcode()) {
1358   case ISD::AND:
1359     if (N->getOperand(0).getOpcode() == ISD::SRL) {
1360       // "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
1361       // Predicate: isMask(mask)
1362       const SDValue &Srl = N->getOperand(0);
1363       ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1));
1364       ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
1365 
1366       if (Shift && Mask) {
1367         uint32_t ShiftVal = Shift->getZExtValue();
1368         uint32_t MaskVal = Mask->getZExtValue();
1369 
1370         if (isMask_32(MaskVal)) {
1371           uint32_t WidthVal = countPopulation(MaskVal);
1372 
1373           ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N),
1374                                   Srl.getOperand(0), ShiftVal, WidthVal));
1375           return;
1376         }
1377       }
1378     }
1379     break;
1380   case ISD::SRL:
1381     if (N->getOperand(0).getOpcode() == ISD::AND) {
1382       // "(a & mask) srl b)" ---> "BFE_U32 a, b, popcount(mask >> b)"
1383       // Predicate: isMask(mask >> b)
1384       const SDValue &And = N->getOperand(0);
1385       ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1));
1386       ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1));
1387 
1388       if (Shift && Mask) {
1389         uint32_t ShiftVal = Shift->getZExtValue();
1390         uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal;
1391 
1392         if (isMask_32(MaskVal)) {
1393           uint32_t WidthVal = countPopulation(MaskVal);
1394 
1395           ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N),
1396                                   And.getOperand(0), ShiftVal, WidthVal));
1397           return;
1398         }
1399       }
1400     } else if (N->getOperand(0).getOpcode() == ISD::SHL) {
1401       SelectS_BFEFromShifts(N);
1402       return;
1403     }
1404     break;
1405   case ISD::SRA:
1406     if (N->getOperand(0).getOpcode() == ISD::SHL) {
1407       SelectS_BFEFromShifts(N);
1408       return;
1409     }
1410     break;
1411 
1412   case ISD::SIGN_EXTEND_INREG: {
1413     // sext_inreg (srl x, 16), i8 -> bfe_i32 x, 16, 8
1414     SDValue Src = N->getOperand(0);
1415     if (Src.getOpcode() != ISD::SRL)
1416       break;
1417 
1418     const ConstantSDNode *Amt = dyn_cast<ConstantSDNode>(Src.getOperand(1));
1419     if (!Amt)
1420       break;
1421 
1422     unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
1423     ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_I32, SDLoc(N), Src.getOperand(0),
1424                             Amt->getZExtValue(), Width));
1425     return;
1426   }
1427   }
1428 
1429   SelectCode(N);
1430 }
1431 
1432 bool AMDGPUDAGToDAGISel::isCBranchSCC(const SDNode *N) const {
1433   assert(N->getOpcode() == ISD::BRCOND);
1434   if (!N->hasOneUse())
1435     return false;
1436 
1437   SDValue Cond = N->getOperand(1);
1438   if (Cond.getOpcode() == ISD::CopyToReg)
1439     Cond = Cond.getOperand(2);
1440 
1441   if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse())
1442     return false;
1443 
1444   MVT VT = Cond.getOperand(0).getSimpleValueType();
1445   if (VT == MVT::i32)
1446     return true;
1447 
1448   if (VT == MVT::i64) {
1449     auto ST = static_cast<const SISubtarget *>(Subtarget);
1450 
1451     ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
1452     return (CC == ISD::SETEQ || CC == ISD::SETNE) && ST->hasScalarCompareEq64();
1453   }
1454 
1455   return false;
1456 }
1457 
1458 void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
1459   SDValue Cond = N->getOperand(1);
1460 
1461   if (isCBranchSCC(N)) {
1462     // This brcond will use S_CBRANCH_SCC*, so let tablegen handle it.
1463     SelectCode(N);
1464     return;
1465   }
1466 
1467   SDLoc SL(N);
1468 
1469   SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, AMDGPU::VCC, Cond);
1470   CurDAG->SelectNodeTo(N, AMDGPU::S_CBRANCH_VCCNZ, MVT::Other,
1471                        N->getOperand(2), // Basic Block
1472                        VCC.getValue(0));
1473 }
1474 
1475 // This is here because there isn't a way to use the generated sub0_sub1 as the
1476 // subreg index to EXTRACT_SUBREG in tablegen.
1477 void AMDGPUDAGToDAGISel::SelectATOMIC_CMP_SWAP(SDNode *N) {
1478   MemSDNode *Mem = cast<MemSDNode>(N);
1479   unsigned AS = Mem->getAddressSpace();
1480   if (AS == AMDGPUAS::FLAT_ADDRESS) {
1481     SelectCode(N);
1482     return;
1483   }
1484 
1485   MVT VT = N->getSimpleValueType(0);
1486   bool Is32 = (VT == MVT::i32);
1487   SDLoc SL(N);
1488 
1489   MachineSDNode *CmpSwap = nullptr;
1490   if (Subtarget->hasAddr64()) {
1491     SDValue SRsrc, VAddr, SOffset, Offset, GLC, SLC;
1492 
1493     if (SelectMUBUFAddr64(Mem->getBasePtr(), SRsrc, VAddr, SOffset, Offset, SLC)) {
1494       unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_RTN_ADDR64 :
1495         AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_RTN_ADDR64;
1496       SDValue CmpVal = Mem->getOperand(2);
1497 
1498       // XXX - Do we care about glue operands?
1499 
1500       SDValue Ops[] = {
1501         CmpVal, VAddr, SRsrc, SOffset, Offset, SLC, Mem->getChain()
1502       };
1503 
1504       CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
1505     }
1506   }
1507 
1508   if (!CmpSwap) {
1509     SDValue SRsrc, SOffset, Offset, SLC;
1510     if (SelectMUBUFOffset(Mem->getBasePtr(), SRsrc, SOffset, Offset, SLC)) {
1511       unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET :
1512         AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_RTN_OFFSET;
1513 
1514       SDValue CmpVal = Mem->getOperand(2);
1515       SDValue Ops[] = {
1516         CmpVal, SRsrc, SOffset, Offset, SLC, Mem->getChain()
1517       };
1518 
1519       CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
1520     }
1521   }
1522 
1523   if (!CmpSwap) {
1524     SelectCode(N);
1525     return;
1526   }
1527 
1528   MachineSDNode::mmo_iterator MMOs = MF->allocateMemRefsArray(1);
1529   *MMOs = Mem->getMemOperand();
1530   CmpSwap->setMemRefs(MMOs, MMOs + 1);
1531 
1532   unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1;
1533   SDValue Extract
1534     = CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0));
1535 
1536   ReplaceUses(SDValue(N, 0), Extract);
1537   ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 1));
1538   CurDAG->RemoveDeadNode(N);
1539 }
1540 
1541 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
1542                                         SDValue &SrcMods) const {
1543   unsigned Mods = 0;
1544 
1545   Src = In;
1546 
1547   if (Src.getOpcode() == ISD::FNEG) {
1548     Mods |= SISrcMods::NEG;
1549     Src = Src.getOperand(0);
1550   }
1551 
1552   if (Src.getOpcode() == ISD::FABS) {
1553     Mods |= SISrcMods::ABS;
1554     Src = Src.getOperand(0);
1555   }
1556 
1557   SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
1558 
1559   return true;
1560 }
1561 
1562 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src,
1563                                          SDValue &SrcMods) const {
1564   bool Res = SelectVOP3Mods(In, Src, SrcMods);
1565   return Res && cast<ConstantSDNode>(SrcMods)->isNullValue();
1566 }
1567 
1568 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
1569                                          SDValue &SrcMods, SDValue &Clamp,
1570                                          SDValue &Omod) const {
1571   SDLoc DL(In);
1572   // FIXME: Handle Clamp and Omod
1573   Clamp = CurDAG->getTargetConstant(0, DL, MVT::i32);
1574   Omod = CurDAG->getTargetConstant(0, DL, MVT::i32);
1575 
1576   return SelectVOP3Mods(In, Src, SrcMods);
1577 }
1578 
1579 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods0(SDValue In, SDValue &Src,
1580                                            SDValue &SrcMods, SDValue &Clamp,
1581                                            SDValue &Omod) const {
1582   bool Res = SelectVOP3Mods0(In, Src, SrcMods, Clamp, Omod);
1583 
1584   return Res && cast<ConstantSDNode>(SrcMods)->isNullValue() &&
1585                 cast<ConstantSDNode>(Clamp)->isNullValue() &&
1586                 cast<ConstantSDNode>(Omod)->isNullValue();
1587 }
1588 
1589 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp(SDValue In, SDValue &Src,
1590                                               SDValue &SrcMods,
1591                                               SDValue &Omod) const {
1592   // FIXME: Handle Omod
1593   Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1594 
1595   return SelectVOP3Mods(In, Src, SrcMods);
1596 }
1597 
1598 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src,
1599                                                    SDValue &SrcMods,
1600                                                    SDValue &Clamp,
1601                                                    SDValue &Omod) const {
1602   Clamp = Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1603   return SelectVOP3Mods(In, Src, SrcMods);
1604 }
1605 
1606 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
1607   const AMDGPUTargetLowering& Lowering =
1608     *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
1609   bool IsModified = false;
1610   do {
1611     IsModified = false;
1612     // Go over all selected nodes and try to fold them a bit more
1613     for (SDNode &Node : CurDAG->allnodes()) {
1614       MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(&Node);
1615       if (!MachineNode)
1616         continue;
1617 
1618       SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
1619       if (ResNode != &Node) {
1620         ReplaceUses(&Node, ResNode);
1621         IsModified = true;
1622       }
1623     }
1624     CurDAG->RemoveDeadNodes();
1625   } while (IsModified);
1626 }
1627