1 //===-- AMDGPUISelDAGToDAG.cpp - A dag to dag inst selector for AMDGPU ----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //==-----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Defines an instruction selector for the AMDGPU target.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPU.h"
16 #include "AMDGPUInstrInfo.h"
17 #include "AMDGPURegisterInfo.h"
18 #include "AMDGPUISelLowering.h" // For AMDGPUISD
19 #include "AMDGPUSubtarget.h"
20 #include "SIDefines.h"
21 #include "SIInstrInfo.h"
22 #include "SIRegisterInfo.h"
23 #include "SIISelLowering.h"
24 #include "SIMachineFunctionInfo.h"
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/ADT/StringRef.h"
28 #include "llvm/Analysis/ValueTracking.h"
29 #include "llvm/CodeGen/FunctionLoweringInfo.h"
30 #include "llvm/CodeGen/ISDOpcodes.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/MachineValueType.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/SelectionDAGISel.h"
36 #include "llvm/CodeGen/SelectionDAGNodes.h"
37 #include "llvm/CodeGen/ValueTypes.h"
38 #include "llvm/IR/BasicBlock.h"
39 #include "llvm/IR/Instruction.h"
40 #include "llvm/MC/MCInstrDesc.h"
41 #include "llvm/Support/Casting.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/MathExtras.h"
45 #include <cassert>
46 #include <cstdint>
47 #include <new>
48 #include <vector>
49 
50 using namespace llvm;
51 
52 namespace llvm {
53 
54 class R600InstrInfo;
55 
56 } // end namespace llvm
57 
58 //===----------------------------------------------------------------------===//
59 // Instruction Selector Implementation
60 //===----------------------------------------------------------------------===//
61 
62 namespace {
63 
64 /// AMDGPU specific code to select AMDGPU machine instructions for
65 /// SelectionDAG operations.
66 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
67   // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
68   // make the right decision when generating code for different targets.
69   const AMDGPUSubtarget *Subtarget;
70 
71 public:
72   explicit AMDGPUDAGToDAGISel(TargetMachine &TM, CodeGenOpt::Level OptLevel)
73       : SelectionDAGISel(TM, OptLevel) {}
74   ~AMDGPUDAGToDAGISel() override = default;
75 
76   bool runOnMachineFunction(MachineFunction &MF) override;
77   void Select(SDNode *N) override;
78   StringRef getPassName() const override;
79   void PostprocessISelDAG() override;
80 
81 private:
82   SDValue foldFrameIndex(SDValue N) const;
83   bool isInlineImmediate(const SDNode *N) const;
84   bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
85                    const R600InstrInfo *TII);
86   bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
87   bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
88 
89   bool isConstantLoad(const MemSDNode *N, int cbID) const;
90   bool isUniformBr(const SDNode *N) const;
91 
92   SDNode *glueCopyToM0(SDNode *N) const;
93 
94   const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
95   bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
96   bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
97                                        SDValue& Offset);
98   bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
99   bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
100   bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
101                        unsigned OffsetBits) const;
102   bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
103   bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
104                                  SDValue &Offset1) const;
105   bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
106                    SDValue &SOffset, SDValue &Offset, SDValue &Offen,
107                    SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
108                    SDValue &TFE) const;
109   bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
110                          SDValue &SOffset, SDValue &Offset, SDValue &GLC,
111                          SDValue &SLC, SDValue &TFE) const;
112   bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
113                          SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
114                          SDValue &SLC) const;
115   bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
116                           SDValue &SOffset, SDValue &ImmOffset) const;
117   bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
118                          SDValue &Offset, SDValue &GLC, SDValue &SLC,
119                          SDValue &TFE) const;
120   bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
121                          SDValue &Offset, SDValue &SLC) const;
122   bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
123                          SDValue &Offset) const;
124   bool SelectMUBUFConstant(SDValue Constant,
125                            SDValue &SOffset,
126                            SDValue &ImmOffset) const;
127   bool SelectMUBUFIntrinsicOffset(SDValue Offset, SDValue &SOffset,
128                                   SDValue &ImmOffset) const;
129   bool SelectMUBUFIntrinsicVOffset(SDValue Offset, SDValue &SOffset,
130                                    SDValue &ImmOffset, SDValue &VOffset) const;
131 
132   bool SelectFlat(SDValue Addr, SDValue &VAddr,
133                   SDValue &SLC, SDValue &TFE) const;
134 
135   bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
136                         bool &Imm) const;
137   bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
138                   bool &Imm) const;
139   bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
140   bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
141   bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
142   bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
143   bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
144   bool SelectSMRDBufferSgpr(SDValue Addr, SDValue &Offset) const;
145   bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
146   bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
147   bool SelectVOP3NoMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
148   bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
149                        SDValue &Clamp, SDValue &Omod) const;
150   bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
151                          SDValue &Clamp, SDValue &Omod) const;
152 
153   bool SelectVOP3Mods0Clamp(SDValue In, SDValue &Src, SDValue &SrcMods,
154                             SDValue &Omod) const;
155   bool SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, SDValue &SrcMods,
156                                  SDValue &Clamp,
157                                  SDValue &Omod) const;
158 
159   void SelectADD_SUB_I64(SDNode *N);
160   void SelectDIV_SCALE(SDNode *N);
161   void SelectFMA_W_CHAIN(SDNode *N);
162   void SelectFMUL_W_CHAIN(SDNode *N);
163 
164   SDNode *getS_BFE(unsigned Opcode, const SDLoc &DL, SDValue Val,
165                    uint32_t Offset, uint32_t Width);
166   void SelectS_BFEFromShifts(SDNode *N);
167   void SelectS_BFE(SDNode *N);
168   bool isCBranchSCC(const SDNode *N) const;
169   void SelectBRCOND(SDNode *N);
170   void SelectATOMIC_CMP_SWAP(SDNode *N);
171 
172   // Include the pieces autogenerated from the target description.
173 #include "AMDGPUGenDAGISel.inc"
174 };
175 
176 }  // end anonymous namespace
177 
178 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
179 // DAG, ready for instruction scheduling.
180 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM,
181                                         CodeGenOpt::Level OptLevel) {
182   return new AMDGPUDAGToDAGISel(TM, OptLevel);
183 }
184 
185 bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
186   Subtarget = &MF.getSubtarget<AMDGPUSubtarget>();
187   return SelectionDAGISel::runOnMachineFunction(MF);
188 }
189 
190 bool AMDGPUDAGToDAGISel::isInlineImmediate(const SDNode *N) const {
191   const SIInstrInfo *TII
192     = static_cast<const SISubtarget *>(Subtarget)->getInstrInfo();
193 
194   if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N))
195     return TII->isInlineConstant(C->getAPIntValue());
196 
197   if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N))
198     return TII->isInlineConstant(C->getValueAPF().bitcastToAPInt());
199 
200   return false;
201 }
202 
203 /// \brief Determine the register class for \p OpNo
204 /// \returns The register class of the virtual register that will be used for
205 /// the given operand number \OpNo or NULL if the register class cannot be
206 /// determined.
207 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
208                                                           unsigned OpNo) const {
209   if (!N->isMachineOpcode()) {
210     if (N->getOpcode() == ISD::CopyToReg) {
211       unsigned Reg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
212       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
213         MachineRegisterInfo &MRI = CurDAG->getMachineFunction().getRegInfo();
214         return MRI.getRegClass(Reg);
215       }
216 
217       const SIRegisterInfo *TRI
218         = static_cast<const SISubtarget *>(Subtarget)->getRegisterInfo();
219       return TRI->getPhysRegClass(Reg);
220     }
221 
222     return nullptr;
223   }
224 
225   switch (N->getMachineOpcode()) {
226   default: {
227     const MCInstrDesc &Desc =
228         Subtarget->getInstrInfo()->get(N->getMachineOpcode());
229     unsigned OpIdx = Desc.getNumDefs() + OpNo;
230     if (OpIdx >= Desc.getNumOperands())
231       return nullptr;
232     int RegClass = Desc.OpInfo[OpIdx].RegClass;
233     if (RegClass == -1)
234       return nullptr;
235 
236     return Subtarget->getRegisterInfo()->getRegClass(RegClass);
237   }
238   case AMDGPU::REG_SEQUENCE: {
239     unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
240     const TargetRegisterClass *SuperRC =
241         Subtarget->getRegisterInfo()->getRegClass(RCID);
242 
243     SDValue SubRegOp = N->getOperand(OpNo + 1);
244     unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
245     return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
246                                                               SubRegIdx);
247   }
248   }
249 }
250 
251 SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const {
252   if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
253       cast<MemSDNode>(N)->getAddressSpace() != AMDGPUAS::LOCAL_ADDRESS)
254     return N;
255 
256   const SITargetLowering& Lowering =
257       *static_cast<const SITargetLowering*>(getTargetLowering());
258 
259   // Write max value to m0 before each load operation
260 
261   SDValue M0 = Lowering.copyToM0(*CurDAG, CurDAG->getEntryNode(), SDLoc(N),
262                                  CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
263 
264   SDValue Glue = M0.getValue(1);
265 
266   SmallVector <SDValue, 8> Ops;
267   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
268      Ops.push_back(N->getOperand(i));
269   }
270   Ops.push_back(Glue);
271   CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops);
272 
273   return N;
274 }
275 
276 static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) {
277   switch (NumVectorElts) {
278   case 1:
279     return AMDGPU::SReg_32_XM0RegClassID;
280   case 2:
281     return AMDGPU::SReg_64RegClassID;
282   case 4:
283     return AMDGPU::SReg_128RegClassID;
284   case 8:
285     return AMDGPU::SReg_256RegClassID;
286   case 16:
287     return AMDGPU::SReg_512RegClassID;
288   }
289 
290   llvm_unreachable("invalid vector size");
291 }
292 
293 void AMDGPUDAGToDAGISel::Select(SDNode *N) {
294   unsigned int Opc = N->getOpcode();
295   if (N->isMachineOpcode()) {
296     N->setNodeId(-1);
297     return;   // Already selected.
298   }
299 
300   if (isa<AtomicSDNode>(N) ||
301       (Opc == AMDGPUISD::ATOMIC_INC || Opc == AMDGPUISD::ATOMIC_DEC))
302     N = glueCopyToM0(N);
303 
304   switch (Opc) {
305   default: break;
306   // We are selecting i64 ADD here instead of custom lower it during
307   // DAG legalization, so we can fold some i64 ADDs used for address
308   // calculation into the LOAD and STORE instructions.
309   case ISD::ADD:
310   case ISD::ADDC:
311   case ISD::ADDE:
312   case ISD::SUB:
313   case ISD::SUBC:
314   case ISD::SUBE: {
315     if (N->getValueType(0) != MVT::i64 ||
316         Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
317       break;
318 
319     SelectADD_SUB_I64(N);
320     return;
321   }
322   case AMDGPUISD::FMUL_W_CHAIN: {
323     SelectFMUL_W_CHAIN(N);
324     return;
325   }
326   case AMDGPUISD::FMA_W_CHAIN: {
327     SelectFMA_W_CHAIN(N);
328     return;
329   }
330 
331   case ISD::SCALAR_TO_VECTOR:
332   case AMDGPUISD::BUILD_VERTICAL_VECTOR:
333   case ISD::BUILD_VECTOR: {
334     unsigned RegClassID;
335     const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo();
336     EVT VT = N->getValueType(0);
337     unsigned NumVectorElts = VT.getVectorNumElements();
338     EVT EltVT = VT.getVectorElementType();
339     assert(EltVT.bitsEq(MVT::i32));
340     if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
341       RegClassID = selectSGPRVectorRegClassID(NumVectorElts);
342     } else {
343       // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
344       // that adds a 128 bits reg copy when going through TwoAddressInstructions
345       // pass. We want to avoid 128 bits copies as much as possible because they
346       // can't be bundled by our scheduler.
347       switch(NumVectorElts) {
348       case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
349       case 4:
350         if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
351           RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
352         else
353           RegClassID = AMDGPU::R600_Reg128RegClassID;
354         break;
355       default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
356       }
357     }
358 
359     SDLoc DL(N);
360     SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
361 
362     if (NumVectorElts == 1) {
363       CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT, N->getOperand(0),
364                            RegClass);
365       return;
366     }
367 
368     assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
369                                   "supported yet");
370     // 16 = Max Num Vector Elements
371     // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
372     // 1 = Vector Register Class
373     SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
374 
375     RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
376     bool IsRegSeq = true;
377     unsigned NOps = N->getNumOperands();
378     for (unsigned i = 0; i < NOps; i++) {
379       // XXX: Why is this here?
380       if (isa<RegisterSDNode>(N->getOperand(i))) {
381         IsRegSeq = false;
382         break;
383       }
384       RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
385       RegSeqArgs[1 + (2 * i) + 1] =
386               CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL,
387                                         MVT::i32);
388     }
389 
390     if (NOps != NumVectorElts) {
391       // Fill in the missing undef elements if this was a scalar_to_vector.
392       assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
393 
394       MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
395                                                      DL, EltVT);
396       for (unsigned i = NOps; i < NumVectorElts; ++i) {
397         RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
398         RegSeqArgs[1 + (2 * i) + 1] =
399           CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32);
400       }
401     }
402 
403     if (!IsRegSeq)
404       break;
405     CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(), RegSeqArgs);
406     return;
407   }
408   case ISD::BUILD_PAIR: {
409     SDValue RC, SubReg0, SubReg1;
410     if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
411       break;
412     }
413     SDLoc DL(N);
414     if (N->getValueType(0) == MVT::i128) {
415       RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32);
416       SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
417       SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
418     } else if (N->getValueType(0) == MVT::i64) {
419       RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32);
420       SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
421       SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
422     } else {
423       llvm_unreachable("Unhandled value type for BUILD_PAIR");
424     }
425     const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
426                             N->getOperand(1), SubReg1 };
427     ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
428                                           N->getValueType(0), Ops));
429     return;
430   }
431 
432   case ISD::Constant:
433   case ISD::ConstantFP: {
434     if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
435         N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
436       break;
437 
438     uint64_t Imm;
439     if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
440       Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
441     else {
442       ConstantSDNode *C = cast<ConstantSDNode>(N);
443       Imm = C->getZExtValue();
444     }
445 
446     SDLoc DL(N);
447     SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
448                                 CurDAG->getConstant(Imm & 0xFFFFFFFF, DL,
449                                                     MVT::i32));
450     SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
451                                 CurDAG->getConstant(Imm >> 32, DL, MVT::i32));
452     const SDValue Ops[] = {
453       CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
454       SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
455       SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
456     };
457 
458     ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
459                                           N->getValueType(0), Ops));
460     return;
461   }
462   case ISD::LOAD:
463   case ISD::STORE: {
464     N = glueCopyToM0(N);
465     break;
466   }
467 
468   case AMDGPUISD::BFE_I32:
469   case AMDGPUISD::BFE_U32: {
470     if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
471       break;
472 
473     // There is a scalar version available, but unlike the vector version which
474     // has a separate operand for the offset and width, the scalar version packs
475     // the width and offset into a single operand. Try to move to the scalar
476     // version if the offsets are constant, so that we can try to keep extended
477     // loads of kernel arguments in SGPRs.
478 
479     // TODO: Technically we could try to pattern match scalar bitshifts of
480     // dynamic values, but it's probably not useful.
481     ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
482     if (!Offset)
483       break;
484 
485     ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
486     if (!Width)
487       break;
488 
489     bool Signed = Opc == AMDGPUISD::BFE_I32;
490 
491     uint32_t OffsetVal = Offset->getZExtValue();
492     uint32_t WidthVal = Width->getZExtValue();
493 
494     ReplaceNode(N, getS_BFE(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32,
495                             SDLoc(N), N->getOperand(0), OffsetVal, WidthVal));
496     return;
497   }
498   case AMDGPUISD::DIV_SCALE: {
499     SelectDIV_SCALE(N);
500     return;
501   }
502   case ISD::CopyToReg: {
503     const SITargetLowering& Lowering =
504       *static_cast<const SITargetLowering*>(getTargetLowering());
505     Lowering.legalizeTargetIndependentNode(N, *CurDAG);
506     break;
507   }
508   case ISD::AND:
509   case ISD::SRL:
510   case ISD::SRA:
511   case ISD::SIGN_EXTEND_INREG:
512     if (N->getValueType(0) != MVT::i32 ||
513         Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
514       break;
515 
516     SelectS_BFE(N);
517     return;
518   case ISD::BRCOND:
519     SelectBRCOND(N);
520     return;
521 
522   case AMDGPUISD::ATOMIC_CMP_SWAP:
523     SelectATOMIC_CMP_SWAP(N);
524     return;
525   }
526 
527   SelectCode(N);
528 }
529 
530 bool AMDGPUDAGToDAGISel::isConstantLoad(const MemSDNode *N, int CbId) const {
531   if (!N->readMem())
532     return false;
533   if (CbId == -1)
534     return N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS;
535 
536   return N->getAddressSpace() == AMDGPUAS::CONSTANT_BUFFER_0 + CbId;
537 }
538 
539 bool AMDGPUDAGToDAGISel::isUniformBr(const SDNode *N) const {
540   const BasicBlock *BB = FuncInfo->MBB->getBasicBlock();
541   const Instruction *Term = BB->getTerminator();
542   return Term->getMetadata("amdgpu.uniform") ||
543          Term->getMetadata("structurizecfg.uniform");
544 }
545 
546 StringRef AMDGPUDAGToDAGISel::getPassName() const {
547   return "AMDGPU DAG->DAG Pattern Instruction Selection";
548 }
549 
550 //===----------------------------------------------------------------------===//
551 // Complex Patterns
552 //===----------------------------------------------------------------------===//
553 
554 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
555                                                          SDValue& IntPtr) {
556   if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
557     IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, SDLoc(Addr),
558                                        true);
559     return true;
560   }
561   return false;
562 }
563 
564 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
565     SDValue& BaseReg, SDValue &Offset) {
566   if (!isa<ConstantSDNode>(Addr)) {
567     BaseReg = Addr;
568     Offset = CurDAG->getIntPtrConstant(0, SDLoc(Addr), true);
569     return true;
570   }
571   return false;
572 }
573 
574 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
575                                            SDValue &Offset) {
576   ConstantSDNode *IMMOffset;
577 
578   if (Addr.getOpcode() == ISD::ADD
579       && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
580       && isInt<16>(IMMOffset->getZExtValue())) {
581 
582       Base = Addr.getOperand(0);
583       Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
584                                          MVT::i32);
585       return true;
586   // If the pointer address is constant, we can move it to the offset field.
587   } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
588              && isInt<16>(IMMOffset->getZExtValue())) {
589     Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
590                                   SDLoc(CurDAG->getEntryNode()),
591                                   AMDGPU::ZERO, MVT::i32);
592     Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
593                                        MVT::i32);
594     return true;
595   }
596 
597   // Default case, no offset
598   Base = Addr;
599   Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
600   return true;
601 }
602 
603 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
604                                             SDValue &Offset) {
605   ConstantSDNode *C;
606   SDLoc DL(Addr);
607 
608   if ((C = dyn_cast<ConstantSDNode>(Addr))) {
609     Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
610     Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
611   } else if ((Addr.getOpcode() == AMDGPUISD::DWORDADDR) &&
612              (C = dyn_cast<ConstantSDNode>(Addr.getOperand(0)))) {
613     Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
614     Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
615   } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
616             (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
617     Base = Addr.getOperand(0);
618     Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
619   } else {
620     Base = Addr;
621     Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
622   }
623 
624   return true;
625 }
626 
627 void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
628   SDLoc DL(N);
629   SDValue LHS = N->getOperand(0);
630   SDValue RHS = N->getOperand(1);
631 
632   unsigned Opcode = N->getOpcode();
633   bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE);
634   bool ProduceCarry =
635       ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC;
636   bool IsAdd =
637       (Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE);
638 
639   SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
640   SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
641 
642   SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
643                                        DL, MVT::i32, LHS, Sub0);
644   SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
645                                        DL, MVT::i32, LHS, Sub1);
646 
647   SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
648                                        DL, MVT::i32, RHS, Sub0);
649   SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
650                                        DL, MVT::i32, RHS, Sub1);
651 
652   SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
653 
654   unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
655   unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
656 
657   SDNode *AddLo;
658   if (!ConsumeCarry) {
659     SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
660     AddLo = CurDAG->getMachineNode(Opc, DL, VTList, Args);
661   } else {
662     SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0), N->getOperand(2) };
663     AddLo = CurDAG->getMachineNode(CarryOpc, DL, VTList, Args);
664   }
665   SDValue AddHiArgs[] = {
666     SDValue(Hi0, 0),
667     SDValue(Hi1, 0),
668     SDValue(AddLo, 1)
669   };
670   SDNode *AddHi = CurDAG->getMachineNode(CarryOpc, DL, VTList, AddHiArgs);
671 
672   SDValue RegSequenceArgs[] = {
673     CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
674     SDValue(AddLo,0),
675     Sub0,
676     SDValue(AddHi,0),
677     Sub1,
678   };
679   SDNode *RegSequence = CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
680                                                MVT::i64, RegSequenceArgs);
681 
682   if (ProduceCarry) {
683     // Replace the carry-use
684     CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(AddHi, 1));
685   }
686 
687   // Replace the remaining uses.
688   CurDAG->ReplaceAllUsesWith(N, RegSequence);
689   CurDAG->RemoveDeadNode(N);
690 }
691 
692 void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
693   SDLoc SL(N);
694   //  src0_modifiers, src0,  src1_modifiers, src1, src2_modifiers, src2, clamp, omod
695   SDValue Ops[10];
696 
697   SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[6], Ops[7]);
698   SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
699   SelectVOP3Mods(N->getOperand(3), Ops[5], Ops[4]);
700   Ops[8] = N->getOperand(0);
701   Ops[9] = N->getOperand(4);
702 
703   CurDAG->SelectNodeTo(N, AMDGPU::V_FMA_F32, N->getVTList(), Ops);
704 }
705 
706 void AMDGPUDAGToDAGISel::SelectFMUL_W_CHAIN(SDNode *N) {
707   SDLoc SL(N);
708   //	src0_modifiers, src0,  src1_modifiers, src1, clamp, omod
709   SDValue Ops[8];
710 
711   SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[4], Ops[5]);
712   SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
713   Ops[6] = N->getOperand(0);
714   Ops[7] = N->getOperand(3);
715 
716   CurDAG->SelectNodeTo(N, AMDGPU::V_MUL_F32_e64, N->getVTList(), Ops);
717 }
718 
719 // We need to handle this here because tablegen doesn't support matching
720 // instructions with multiple outputs.
721 void AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
722   SDLoc SL(N);
723   EVT VT = N->getValueType(0);
724 
725   assert(VT == MVT::f32 || VT == MVT::f64);
726 
727   unsigned Opc
728     = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
729 
730   // src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp,
731   // omod
732   SDValue Ops[8];
733 
734   SelectVOP3Mods0(N->getOperand(0), Ops[1], Ops[0], Ops[6], Ops[7]);
735   SelectVOP3Mods(N->getOperand(1), Ops[3], Ops[2]);
736   SelectVOP3Mods(N->getOperand(2), Ops[5], Ops[4]);
737   CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
738 }
739 
740 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
741                                          unsigned OffsetBits) const {
742   if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
743       (OffsetBits == 8 && !isUInt<8>(Offset)))
744     return false;
745 
746   if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS ||
747       Subtarget->unsafeDSOffsetFoldingEnabled())
748     return true;
749 
750   // On Southern Islands instruction with a negative base value and an offset
751   // don't seem to work.
752   return CurDAG->SignBitIsZero(Base);
753 }
754 
755 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
756                                               SDValue &Offset) const {
757   SDLoc DL(Addr);
758   if (CurDAG->isBaseWithConstantOffset(Addr)) {
759     SDValue N0 = Addr.getOperand(0);
760     SDValue N1 = Addr.getOperand(1);
761     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
762     if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
763       // (add n0, c0)
764       Base = N0;
765       Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
766       return true;
767     }
768   } else if (Addr.getOpcode() == ISD::SUB) {
769     // sub C, x -> add (sub 0, x), C
770     if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
771       int64_t ByteOffset = C->getSExtValue();
772       if (isUInt<16>(ByteOffset)) {
773         SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
774 
775         // XXX - This is kind of hacky. Create a dummy sub node so we can check
776         // the known bits in isDSOffsetLegal. We need to emit the selected node
777         // here, so this is thrown away.
778         SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
779                                       Zero, Addr.getOperand(1));
780 
781         if (isDSOffsetLegal(Sub, ByteOffset, 16)) {
782           MachineSDNode *MachineSub
783             = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
784                                      Zero, Addr.getOperand(1));
785 
786           Base = SDValue(MachineSub, 0);
787           Offset = CurDAG->getTargetConstant(ByteOffset, DL, MVT::i16);
788           return true;
789         }
790       }
791     }
792   } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
793     // If we have a constant address, prefer to put the constant into the
794     // offset. This can save moves to load the constant address since multiple
795     // operations can share the zero base address register, and enables merging
796     // into read2 / write2 instructions.
797 
798     SDLoc DL(Addr);
799 
800     if (isUInt<16>(CAddr->getZExtValue())) {
801       SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
802       MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
803                                  DL, MVT::i32, Zero);
804       Base = SDValue(MovZero, 0);
805       Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16);
806       return true;
807     }
808   }
809 
810   // default case
811   Base = Addr;
812   Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i16);
813   return true;
814 }
815 
816 // TODO: If offset is too big, put low 16-bit into offset.
817 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
818                                                    SDValue &Offset0,
819                                                    SDValue &Offset1) const {
820   SDLoc DL(Addr);
821 
822   if (CurDAG->isBaseWithConstantOffset(Addr)) {
823     SDValue N0 = Addr.getOperand(0);
824     SDValue N1 = Addr.getOperand(1);
825     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
826     unsigned DWordOffset0 = C1->getZExtValue() / 4;
827     unsigned DWordOffset1 = DWordOffset0 + 1;
828     // (add n0, c0)
829     if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
830       Base = N0;
831       Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
832       Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
833       return true;
834     }
835   } else if (Addr.getOpcode() == ISD::SUB) {
836     // sub C, x -> add (sub 0, x), C
837     if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
838       unsigned DWordOffset0 = C->getZExtValue() / 4;
839       unsigned DWordOffset1 = DWordOffset0 + 1;
840 
841       if (isUInt<8>(DWordOffset0)) {
842         SDLoc DL(Addr);
843         SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
844 
845         // XXX - This is kind of hacky. Create a dummy sub node so we can check
846         // the known bits in isDSOffsetLegal. We need to emit the selected node
847         // here, so this is thrown away.
848         SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
849                                       Zero, Addr.getOperand(1));
850 
851         if (isDSOffsetLegal(Sub, DWordOffset1, 8)) {
852           MachineSDNode *MachineSub
853             = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
854                                      Zero, Addr.getOperand(1));
855 
856           Base = SDValue(MachineSub, 0);
857           Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
858           Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
859           return true;
860         }
861       }
862     }
863   } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
864     unsigned DWordOffset0 = CAddr->getZExtValue() / 4;
865     unsigned DWordOffset1 = DWordOffset0 + 1;
866     assert(4 * DWordOffset0 == CAddr->getZExtValue());
867 
868     if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) {
869       SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
870       MachineSDNode *MovZero
871         = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
872                                  DL, MVT::i32, Zero);
873       Base = SDValue(MovZero, 0);
874       Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
875       Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
876       return true;
877     }
878   }
879 
880   // default case
881 
882   // FIXME: This is broken on SI where we still need to check if the base
883   // pointer is positive here.
884   Base = Addr;
885   Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8);
886   Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8);
887   return true;
888 }
889 
890 static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
891   return isUInt<12>(Imm->getZExtValue());
892 }
893 
894 bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
895                                      SDValue &VAddr, SDValue &SOffset,
896                                      SDValue &Offset, SDValue &Offen,
897                                      SDValue &Idxen, SDValue &Addr64,
898                                      SDValue &GLC, SDValue &SLC,
899                                      SDValue &TFE) const {
900   // Subtarget prefers to use flat instruction
901   if (Subtarget->useFlatForGlobal())
902     return false;
903 
904   SDLoc DL(Addr);
905 
906   if (!GLC.getNode())
907     GLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
908   if (!SLC.getNode())
909     SLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
910   TFE = CurDAG->getTargetConstant(0, DL, MVT::i1);
911 
912   Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1);
913   Offen = CurDAG->getTargetConstant(0, DL, MVT::i1);
914   Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1);
915   SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
916 
917   if (CurDAG->isBaseWithConstantOffset(Addr)) {
918     SDValue N0 = Addr.getOperand(0);
919     SDValue N1 = Addr.getOperand(1);
920     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
921 
922     if (N0.getOpcode() == ISD::ADD) {
923       // (add (add N2, N3), C1) -> addr64
924       SDValue N2 = N0.getOperand(0);
925       SDValue N3 = N0.getOperand(1);
926       Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
927       Ptr = N2;
928       VAddr = N3;
929     } else {
930       // (add N0, C1) -> offset
931       VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
932       Ptr = N0;
933     }
934 
935     if (isLegalMUBUFImmOffset(C1)) {
936       Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
937       return true;
938     }
939 
940     if (isUInt<32>(C1->getZExtValue())) {
941       // Illegal offset, store it in soffset.
942       Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
943       SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
944                    CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)),
945                         0);
946       return true;
947     }
948   }
949 
950   if (Addr.getOpcode() == ISD::ADD) {
951     // (add N0, N1) -> addr64
952     SDValue N0 = Addr.getOperand(0);
953     SDValue N1 = Addr.getOperand(1);
954     Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
955     Ptr = N0;
956     VAddr = N1;
957     Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
958     return true;
959   }
960 
961   // default case -> offset
962   VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
963   Ptr = Addr;
964   Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
965 
966   return true;
967 }
968 
969 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
970                                            SDValue &VAddr, SDValue &SOffset,
971                                            SDValue &Offset, SDValue &GLC,
972                                            SDValue &SLC, SDValue &TFE) const {
973   SDValue Ptr, Offen, Idxen, Addr64;
974 
975   // addr64 bit was removed for volcanic islands.
976   if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
977     return false;
978 
979   if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
980               GLC, SLC, TFE))
981     return false;
982 
983   ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
984   if (C->getSExtValue()) {
985     SDLoc DL(Addr);
986 
987     const SITargetLowering& Lowering =
988       *static_cast<const SITargetLowering*>(getTargetLowering());
989 
990     SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
991     return true;
992   }
993 
994   return false;
995 }
996 
997 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
998                                            SDValue &VAddr, SDValue &SOffset,
999                                            SDValue &Offset,
1000                                            SDValue &SLC) const {
1001   SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1);
1002   SDValue GLC, TFE;
1003 
1004   return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE);
1005 }
1006 
1007 SDValue AMDGPUDAGToDAGISel::foldFrameIndex(SDValue N) const {
1008   if (auto FI = dyn_cast<FrameIndexSDNode>(N))
1009     return CurDAG->getTargetFrameIndex(FI->getIndex(), FI->getValueType(0));
1010   return N;
1011 }
1012 
1013 bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
1014                                             SDValue &VAddr, SDValue &SOffset,
1015                                             SDValue &ImmOffset) const {
1016 
1017   SDLoc DL(Addr);
1018   MachineFunction &MF = CurDAG->getMachineFunction();
1019   const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1020 
1021   Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
1022   SOffset = CurDAG->getRegister(Info->getScratchWaveOffsetReg(), MVT::i32);
1023 
1024   // (add n0, c1)
1025   if (CurDAG->isBaseWithConstantOffset(Addr)) {
1026     SDValue N0 = Addr.getOperand(0);
1027     SDValue N1 = Addr.getOperand(1);
1028 
1029     // Offsets in vaddr must be positive.
1030     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1031     if (isLegalMUBUFImmOffset(C1)) {
1032       VAddr = foldFrameIndex(N0);
1033       ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1034       return true;
1035     }
1036   }
1037 
1038   // (node)
1039   VAddr = foldFrameIndex(Addr);
1040   ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1041   return true;
1042 }
1043 
1044 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1045                                            SDValue &SOffset, SDValue &Offset,
1046                                            SDValue &GLC, SDValue &SLC,
1047                                            SDValue &TFE) const {
1048   SDValue Ptr, VAddr, Offen, Idxen, Addr64;
1049   const SIInstrInfo *TII =
1050     static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1051 
1052   if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1053               GLC, SLC, TFE))
1054     return false;
1055 
1056   if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
1057       !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
1058       !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
1059     uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
1060                     APInt::getAllOnesValue(32).getZExtValue(); // Size
1061     SDLoc DL(Addr);
1062 
1063     const SITargetLowering& Lowering =
1064       *static_cast<const SITargetLowering*>(getTargetLowering());
1065 
1066     SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
1067     return true;
1068   }
1069   return false;
1070 }
1071 
1072 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1073                                            SDValue &Soffset, SDValue &Offset
1074                                            ) const {
1075   SDValue GLC, SLC, TFE;
1076 
1077   return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1078 }
1079 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1080                                            SDValue &Soffset, SDValue &Offset,
1081                                            SDValue &SLC) const {
1082   SDValue GLC, TFE;
1083 
1084   return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1085 }
1086 
1087 bool AMDGPUDAGToDAGISel::SelectMUBUFConstant(SDValue Constant,
1088                                              SDValue &SOffset,
1089                                              SDValue &ImmOffset) const {
1090   SDLoc DL(Constant);
1091   uint32_t Imm = cast<ConstantSDNode>(Constant)->getZExtValue();
1092   uint32_t Overflow = 0;
1093 
1094   if (Imm >= 4096) {
1095     if (Imm <= 4095 + 64) {
1096       // Use an SOffset inline constant for 1..64
1097       Overflow = Imm - 4095;
1098       Imm = 4095;
1099     } else {
1100       // Try to keep the same value in SOffset for adjacent loads, so that
1101       // the corresponding register contents can be re-used.
1102       //
1103       // Load values with all low-bits set into SOffset, so that a larger
1104       // range of values can be covered using s_movk_i32
1105       uint32_t High = (Imm + 1) & ~4095;
1106       uint32_t Low = (Imm + 1) & 4095;
1107       Imm = Low;
1108       Overflow = High - 1;
1109     }
1110   }
1111 
1112   // There is a hardware bug in SI and CI which prevents address clamping in
1113   // MUBUF instructions from working correctly with SOffsets. The immediate
1114   // offset is unaffected.
1115   if (Overflow > 0 &&
1116       Subtarget->getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS)
1117     return false;
1118 
1119   ImmOffset = CurDAG->getTargetConstant(Imm, DL, MVT::i16);
1120 
1121   if (Overflow <= 64)
1122     SOffset = CurDAG->getTargetConstant(Overflow, DL, MVT::i32);
1123   else
1124     SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1125                       CurDAG->getTargetConstant(Overflow, DL, MVT::i32)),
1126                       0);
1127 
1128   return true;
1129 }
1130 
1131 bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicOffset(SDValue Offset,
1132                                                     SDValue &SOffset,
1133                                                     SDValue &ImmOffset) const {
1134   SDLoc DL(Offset);
1135 
1136   if (!isa<ConstantSDNode>(Offset))
1137     return false;
1138 
1139   return SelectMUBUFConstant(Offset, SOffset, ImmOffset);
1140 }
1141 
1142 bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicVOffset(SDValue Offset,
1143                                                      SDValue &SOffset,
1144                                                      SDValue &ImmOffset,
1145                                                      SDValue &VOffset) const {
1146   SDLoc DL(Offset);
1147 
1148   // Don't generate an unnecessary voffset for constant offsets.
1149   if (isa<ConstantSDNode>(Offset)) {
1150     SDValue Tmp1, Tmp2;
1151 
1152     // When necessary, use a voffset in <= CI anyway to work around a hardware
1153     // bug.
1154     if (Subtarget->getGeneration() > AMDGPUSubtarget::SEA_ISLANDS ||
1155         SelectMUBUFConstant(Offset, Tmp1, Tmp2))
1156       return false;
1157   }
1158 
1159   if (CurDAG->isBaseWithConstantOffset(Offset)) {
1160     SDValue N0 = Offset.getOperand(0);
1161     SDValue N1 = Offset.getOperand(1);
1162     if (cast<ConstantSDNode>(N1)->getSExtValue() >= 0 &&
1163         SelectMUBUFConstant(N1, SOffset, ImmOffset)) {
1164       VOffset = N0;
1165       return true;
1166     }
1167   }
1168 
1169   SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
1170   ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1171   VOffset = Offset;
1172 
1173   return true;
1174 }
1175 
1176 bool AMDGPUDAGToDAGISel::SelectFlat(SDValue Addr,
1177                                     SDValue &VAddr,
1178                                     SDValue &SLC,
1179                                     SDValue &TFE) const {
1180   VAddr = Addr;
1181   TFE = SLC = CurDAG->getTargetConstant(0, SDLoc(), MVT::i1);
1182   return true;
1183 }
1184 
1185 ///
1186 /// \param EncodedOffset This is the immediate value that will be encoded
1187 ///        directly into the instruction.  On SI/CI the \p EncodedOffset
1188 ///        will be in units of dwords and on VI+ it will be units of bytes.
1189 static bool isLegalSMRDImmOffset(const AMDGPUSubtarget *ST,
1190                                  int64_t EncodedOffset) {
1191   return ST->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS ?
1192      isUInt<8>(EncodedOffset) : isUInt<20>(EncodedOffset);
1193 }
1194 
1195 bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
1196                                           SDValue &Offset, bool &Imm) const {
1197 
1198   // FIXME: Handle non-constant offsets.
1199   ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode);
1200   if (!C)
1201     return false;
1202 
1203   SDLoc SL(ByteOffsetNode);
1204   AMDGPUSubtarget::Generation Gen = Subtarget->getGeneration();
1205   int64_t ByteOffset = C->getSExtValue();
1206   int64_t EncodedOffset = Gen < AMDGPUSubtarget::VOLCANIC_ISLANDS ?
1207       ByteOffset >> 2 : ByteOffset;
1208 
1209   if (isLegalSMRDImmOffset(Subtarget, EncodedOffset)) {
1210     Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1211     Imm = true;
1212     return true;
1213   }
1214 
1215   if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset))
1216     return false;
1217 
1218   if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) {
1219     // 32-bit Immediates are supported on Sea Islands.
1220     Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1221   } else {
1222     SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
1223     Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32,
1224                                             C32Bit), 0);
1225   }
1226   Imm = false;
1227   return true;
1228 }
1229 
1230 bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
1231                                      SDValue &Offset, bool &Imm) const {
1232   SDLoc SL(Addr);
1233   if (CurDAG->isBaseWithConstantOffset(Addr)) {
1234     SDValue N0 = Addr.getOperand(0);
1235     SDValue N1 = Addr.getOperand(1);
1236 
1237     if (SelectSMRDOffset(N1, Offset, Imm)) {
1238       SBase = N0;
1239       return true;
1240     }
1241   }
1242   SBase = Addr;
1243   Offset = CurDAG->getTargetConstant(0, SL, MVT::i32);
1244   Imm = true;
1245   return true;
1246 }
1247 
1248 bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase,
1249                                        SDValue &Offset) const {
1250   bool Imm;
1251   return SelectSMRD(Addr, SBase, Offset, Imm) && Imm;
1252 }
1253 
1254 bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase,
1255                                          SDValue &Offset) const {
1256 
1257   if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1258     return false;
1259 
1260   bool Imm;
1261   if (!SelectSMRD(Addr, SBase, Offset, Imm))
1262     return false;
1263 
1264   return !Imm && isa<ConstantSDNode>(Offset);
1265 }
1266 
1267 bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
1268                                         SDValue &Offset) const {
1269   bool Imm;
1270   return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm &&
1271          !isa<ConstantSDNode>(Offset);
1272 }
1273 
1274 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
1275                                              SDValue &Offset) const {
1276   bool Imm;
1277   return SelectSMRDOffset(Addr, Offset, Imm) && Imm;
1278 }
1279 
1280 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr,
1281                                                SDValue &Offset) const {
1282   if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1283     return false;
1284 
1285   bool Imm;
1286   if (!SelectSMRDOffset(Addr, Offset, Imm))
1287     return false;
1288 
1289   return !Imm && isa<ConstantSDNode>(Offset);
1290 }
1291 
1292 bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
1293                                               SDValue &Offset) const {
1294   bool Imm;
1295   return SelectSMRDOffset(Addr, Offset, Imm) && !Imm &&
1296          !isa<ConstantSDNode>(Offset);
1297 }
1298 
1299 bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
1300                                             SDValue &Base,
1301                                             SDValue &Offset) const {
1302   SDLoc DL(Index);
1303 
1304   if (CurDAG->isBaseWithConstantOffset(Index)) {
1305     SDValue N0 = Index.getOperand(0);
1306     SDValue N1 = Index.getOperand(1);
1307     ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1308 
1309     // (add n0, c0)
1310     Base = N0;
1311     Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32);
1312     return true;
1313   }
1314 
1315   if (isa<ConstantSDNode>(Index))
1316     return false;
1317 
1318   Base = Index;
1319   Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
1320   return true;
1321 }
1322 
1323 SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, const SDLoc &DL,
1324                                      SDValue Val, uint32_t Offset,
1325                                      uint32_t Width) {
1326   // Transformation function, pack the offset and width of a BFE into
1327   // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
1328   // source, bits [5:0] contain the offset and bits [22:16] the width.
1329   uint32_t PackedVal = Offset | (Width << 16);
1330   SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32);
1331 
1332   return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst);
1333 }
1334 
1335 void AMDGPUDAGToDAGISel::SelectS_BFEFromShifts(SDNode *N) {
1336   // "(a << b) srl c)" ---> "BFE_U32 a, (c-b), (32-c)
1337   // "(a << b) sra c)" ---> "BFE_I32 a, (c-b), (32-c)
1338   // Predicate: 0 < b <= c < 32
1339 
1340   const SDValue &Shl = N->getOperand(0);
1341   ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
1342   ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1343 
1344   if (B && C) {
1345     uint32_t BVal = B->getZExtValue();
1346     uint32_t CVal = C->getZExtValue();
1347 
1348     if (0 < BVal && BVal <= CVal && CVal < 32) {
1349       bool Signed = N->getOpcode() == ISD::SRA;
1350       unsigned Opcode = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;
1351 
1352       ReplaceNode(N, getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0), CVal - BVal,
1353                               32 - CVal));
1354       return;
1355     }
1356   }
1357   SelectCode(N);
1358 }
1359 
1360 void AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
1361   switch (N->getOpcode()) {
1362   case ISD::AND:
1363     if (N->getOperand(0).getOpcode() == ISD::SRL) {
1364       // "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
1365       // Predicate: isMask(mask)
1366       const SDValue &Srl = N->getOperand(0);
1367       ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1));
1368       ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
1369 
1370       if (Shift && Mask) {
1371         uint32_t ShiftVal = Shift->getZExtValue();
1372         uint32_t MaskVal = Mask->getZExtValue();
1373 
1374         if (isMask_32(MaskVal)) {
1375           uint32_t WidthVal = countPopulation(MaskVal);
1376 
1377           ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N),
1378                                   Srl.getOperand(0), ShiftVal, WidthVal));
1379           return;
1380         }
1381       }
1382     }
1383     break;
1384   case ISD::SRL:
1385     if (N->getOperand(0).getOpcode() == ISD::AND) {
1386       // "(a & mask) srl b)" ---> "BFE_U32 a, b, popcount(mask >> b)"
1387       // Predicate: isMask(mask >> b)
1388       const SDValue &And = N->getOperand(0);
1389       ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1));
1390       ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1));
1391 
1392       if (Shift && Mask) {
1393         uint32_t ShiftVal = Shift->getZExtValue();
1394         uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal;
1395 
1396         if (isMask_32(MaskVal)) {
1397           uint32_t WidthVal = countPopulation(MaskVal);
1398 
1399           ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N),
1400                                   And.getOperand(0), ShiftVal, WidthVal));
1401           return;
1402         }
1403       }
1404     } else if (N->getOperand(0).getOpcode() == ISD::SHL) {
1405       SelectS_BFEFromShifts(N);
1406       return;
1407     }
1408     break;
1409   case ISD::SRA:
1410     if (N->getOperand(0).getOpcode() == ISD::SHL) {
1411       SelectS_BFEFromShifts(N);
1412       return;
1413     }
1414     break;
1415 
1416   case ISD::SIGN_EXTEND_INREG: {
1417     // sext_inreg (srl x, 16), i8 -> bfe_i32 x, 16, 8
1418     SDValue Src = N->getOperand(0);
1419     if (Src.getOpcode() != ISD::SRL)
1420       break;
1421 
1422     const ConstantSDNode *Amt = dyn_cast<ConstantSDNode>(Src.getOperand(1));
1423     if (!Amt)
1424       break;
1425 
1426     unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
1427     ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_I32, SDLoc(N), Src.getOperand(0),
1428                             Amt->getZExtValue(), Width));
1429     return;
1430   }
1431   }
1432 
1433   SelectCode(N);
1434 }
1435 
1436 bool AMDGPUDAGToDAGISel::isCBranchSCC(const SDNode *N) const {
1437   assert(N->getOpcode() == ISD::BRCOND);
1438   if (!N->hasOneUse())
1439     return false;
1440 
1441   SDValue Cond = N->getOperand(1);
1442   if (Cond.getOpcode() == ISD::CopyToReg)
1443     Cond = Cond.getOperand(2);
1444 
1445   if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse())
1446     return false;
1447 
1448   MVT VT = Cond.getOperand(0).getSimpleValueType();
1449   if (VT == MVT::i32)
1450     return true;
1451 
1452   if (VT == MVT::i64) {
1453     auto ST = static_cast<const SISubtarget *>(Subtarget);
1454 
1455     ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
1456     return (CC == ISD::SETEQ || CC == ISD::SETNE) && ST->hasScalarCompareEq64();
1457   }
1458 
1459   return false;
1460 }
1461 
1462 void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
1463   SDValue Cond = N->getOperand(1);
1464 
1465   if (Cond.isUndef()) {
1466     CurDAG->SelectNodeTo(N, AMDGPU::SI_BR_UNDEF, MVT::Other,
1467                          N->getOperand(2), N->getOperand(0));
1468     return;
1469   }
1470 
1471   if (isCBranchSCC(N)) {
1472     // This brcond will use S_CBRANCH_SCC*, so let tablegen handle it.
1473     SelectCode(N);
1474     return;
1475   }
1476 
1477   SDLoc SL(N);
1478 
1479   SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, AMDGPU::VCC, Cond);
1480   CurDAG->SelectNodeTo(N, AMDGPU::S_CBRANCH_VCCNZ, MVT::Other,
1481                        N->getOperand(2), // Basic Block
1482                        VCC.getValue(0));
1483 }
1484 
1485 // This is here because there isn't a way to use the generated sub0_sub1 as the
1486 // subreg index to EXTRACT_SUBREG in tablegen.
1487 void AMDGPUDAGToDAGISel::SelectATOMIC_CMP_SWAP(SDNode *N) {
1488   MemSDNode *Mem = cast<MemSDNode>(N);
1489   unsigned AS = Mem->getAddressSpace();
1490   if (AS == AMDGPUAS::FLAT_ADDRESS) {
1491     SelectCode(N);
1492     return;
1493   }
1494 
1495   MVT VT = N->getSimpleValueType(0);
1496   bool Is32 = (VT == MVT::i32);
1497   SDLoc SL(N);
1498 
1499   MachineSDNode *CmpSwap = nullptr;
1500   if (Subtarget->hasAddr64()) {
1501     SDValue SRsrc, VAddr, SOffset, Offset, GLC, SLC;
1502 
1503     if (SelectMUBUFAddr64(Mem->getBasePtr(), SRsrc, VAddr, SOffset, Offset, SLC)) {
1504       unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_RTN_ADDR64 :
1505         AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_RTN_ADDR64;
1506       SDValue CmpVal = Mem->getOperand(2);
1507 
1508       // XXX - Do we care about glue operands?
1509 
1510       SDValue Ops[] = {
1511         CmpVal, VAddr, SRsrc, SOffset, Offset, SLC, Mem->getChain()
1512       };
1513 
1514       CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
1515     }
1516   }
1517 
1518   if (!CmpSwap) {
1519     SDValue SRsrc, SOffset, Offset, SLC;
1520     if (SelectMUBUFOffset(Mem->getBasePtr(), SRsrc, SOffset, Offset, SLC)) {
1521       unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET :
1522         AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_RTN_OFFSET;
1523 
1524       SDValue CmpVal = Mem->getOperand(2);
1525       SDValue Ops[] = {
1526         CmpVal, SRsrc, SOffset, Offset, SLC, Mem->getChain()
1527       };
1528 
1529       CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
1530     }
1531   }
1532 
1533   if (!CmpSwap) {
1534     SelectCode(N);
1535     return;
1536   }
1537 
1538   MachineSDNode::mmo_iterator MMOs = MF->allocateMemRefsArray(1);
1539   *MMOs = Mem->getMemOperand();
1540   CmpSwap->setMemRefs(MMOs, MMOs + 1);
1541 
1542   unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1;
1543   SDValue Extract
1544     = CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0));
1545 
1546   ReplaceUses(SDValue(N, 0), Extract);
1547   ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 1));
1548   CurDAG->RemoveDeadNode(N);
1549 }
1550 
1551 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
1552                                         SDValue &SrcMods) const {
1553   unsigned Mods = 0;
1554 
1555   Src = In;
1556 
1557   if (Src.getOpcode() == ISD::FNEG) {
1558     Mods |= SISrcMods::NEG;
1559     Src = Src.getOperand(0);
1560   }
1561 
1562   if (Src.getOpcode() == ISD::FABS) {
1563     Mods |= SISrcMods::ABS;
1564     Src = Src.getOperand(0);
1565   }
1566 
1567   SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
1568 
1569   return true;
1570 }
1571 
1572 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src,
1573                                          SDValue &SrcMods) const {
1574   bool Res = SelectVOP3Mods(In, Src, SrcMods);
1575   return Res && cast<ConstantSDNode>(SrcMods)->isNullValue();
1576 }
1577 
1578 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
1579                                          SDValue &SrcMods, SDValue &Clamp,
1580                                          SDValue &Omod) const {
1581   SDLoc DL(In);
1582   // FIXME: Handle Clamp and Omod
1583   Clamp = CurDAG->getTargetConstant(0, DL, MVT::i32);
1584   Omod = CurDAG->getTargetConstant(0, DL, MVT::i32);
1585 
1586   return SelectVOP3Mods(In, Src, SrcMods);
1587 }
1588 
1589 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods0(SDValue In, SDValue &Src,
1590                                            SDValue &SrcMods, SDValue &Clamp,
1591                                            SDValue &Omod) const {
1592   bool Res = SelectVOP3Mods0(In, Src, SrcMods, Clamp, Omod);
1593 
1594   return Res && cast<ConstantSDNode>(SrcMods)->isNullValue() &&
1595                 cast<ConstantSDNode>(Clamp)->isNullValue() &&
1596                 cast<ConstantSDNode>(Omod)->isNullValue();
1597 }
1598 
1599 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp(SDValue In, SDValue &Src,
1600                                               SDValue &SrcMods,
1601                                               SDValue &Omod) const {
1602   // FIXME: Handle Omod
1603   Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1604 
1605   return SelectVOP3Mods(In, Src, SrcMods);
1606 }
1607 
1608 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src,
1609                                                    SDValue &SrcMods,
1610                                                    SDValue &Clamp,
1611                                                    SDValue &Omod) const {
1612   Clamp = Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1613   return SelectVOP3Mods(In, Src, SrcMods);
1614 }
1615 
1616 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
1617   const AMDGPUTargetLowering& Lowering =
1618     *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
1619   bool IsModified = false;
1620   do {
1621     IsModified = false;
1622     // Go over all selected nodes and try to fold them a bit more
1623     for (SDNode &Node : CurDAG->allnodes()) {
1624       MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(&Node);
1625       if (!MachineNode)
1626         continue;
1627 
1628       SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
1629       if (ResNode != &Node) {
1630         ReplaceUses(&Node, ResNode);
1631         IsModified = true;
1632       }
1633     }
1634     CurDAG->RemoveDeadNodes();
1635   } while (IsModified);
1636 }
1637