1//=- AMDGPUCombine.td - Define AMDGPU Combine Rules ----------*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9include "llvm/Target/GlobalISel/Combine.td"
10
11// TODO: This really belongs after legalization after scalarization.
12// TODO: GICombineRules should accept subtarget predicates
13
14def fmin_fmax_legacy_matchdata : GIDefMatchData<"AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo">;
15
16def fcmp_select_to_fmin_fmax_legacy : GICombineRule<
17  (defs root:$select, fmin_fmax_legacy_matchdata:$matchinfo),
18  (match (wip_match_opcode G_SELECT):$select,
19         [{ return PostLegalizerHelper.matchFMinFMaxLegacy(*${select}, ${matchinfo}); }]),
20  (apply [{ PostLegalizerHelper.applySelectFCmpToFMinToFMaxLegacy(*${select}, ${matchinfo}); }])>;
21
22
23def uchar_to_float : GICombineRule<
24  (defs root:$itofp),
25  (match (wip_match_opcode G_UITOFP, G_SITOFP):$itofp,
26         [{ return PostLegalizerHelper.matchUCharToFloat(*${itofp}); }]),
27  (apply [{ PostLegalizerHelper.applyUCharToFloat(*${itofp}); }])>;
28
29
30def rcp_sqrt_to_rsq : GICombineRule<
31  (defs root:$rcp, build_fn_matchinfo:$matchinfo),
32  (match (wip_match_opcode G_INTRINSIC, G_FSQRT):$rcp,
33         [{ return PostLegalizerHelper.matchRcpSqrtToRsq(*${rcp}, ${matchinfo}); }]),
34  (apply [{ Helper.applyBuildFn(*${rcp}, ${matchinfo}); }])>;
35
36
37def cvt_f32_ubyteN_matchdata : GIDefMatchData<"AMDGPUPostLegalizerCombinerHelper::CvtF32UByteMatchInfo">;
38
39def cvt_f32_ubyteN : GICombineRule<
40  (defs root:$cvt_f32_ubyteN, cvt_f32_ubyteN_matchdata:$matchinfo),
41  (match (wip_match_opcode G_AMDGPU_CVT_F32_UBYTE0,
42                           G_AMDGPU_CVT_F32_UBYTE1,
43                           G_AMDGPU_CVT_F32_UBYTE2,
44                           G_AMDGPU_CVT_F32_UBYTE3):$cvt_f32_ubyteN,
45         [{ return PostLegalizerHelper.matchCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }]),
46  (apply [{ PostLegalizerHelper.applyCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }])>;
47
48def clamp_i64_to_i16_matchdata : GIDefMatchData<"AMDGPUPreLegalizerCombinerHelper::ClampI64ToI16MatchInfo">;
49
50def clamp_i64_to_i16 : GICombineRule<
51  (defs root:$clamp_i64_to_i16, clamp_i64_to_i16_matchdata:$matchinfo),
52  (match (wip_match_opcode G_TRUNC):$clamp_i64_to_i16,
53      [{ return PreLegalizerHelper.matchClampI64ToI16(*${clamp_i64_to_i16}, MRI, *MF, ${matchinfo}); }]),
54  (apply [{ PreLegalizerHelper.applyClampI64ToI16(*${clamp_i64_to_i16}, ${matchinfo}); }])>;
55
56def med3_matchdata : GIDefMatchData<"AMDGPURegBankCombinerHelper::Med3MatchInfo">;
57
58def int_minmax_to_med3 : GICombineRule<
59  (defs root:$min_or_max, med3_matchdata:$matchinfo),
60  (match (wip_match_opcode G_SMAX,
61                           G_SMIN,
62                           G_UMAX,
63                           G_UMIN):$min_or_max,
64         [{ return RegBankHelper.matchIntMinMaxToMed3(*${min_or_max}, ${matchinfo}); }]),
65  (apply [{ RegBankHelper.applyMed3(*${min_or_max}, ${matchinfo}); }])>;
66
67def remove_fcanonicalize_matchinfo : GIDefMatchData<"Register">;
68
69def remove_fcanonicalize : GICombineRule<
70  (defs root:$fcanonicalize, remove_fcanonicalize_matchinfo:$matchinfo),
71  (match (wip_match_opcode G_FCANONICALIZE):$fcanonicalize,
72         [{ return PostLegalizerHelper.matchRemoveFcanonicalize(*${fcanonicalize}, ${matchinfo}); }]),
73  (apply [{ Helper.replaceSingleDefInstWithReg(*${fcanonicalize}, ${matchinfo}); }])>;
74
75def foldable_fneg_matchdata : GIDefMatchData<"MachineInstr *">;
76
77def foldable_fneg : GICombineRule<
78  (defs root:$ffn, foldable_fneg_matchdata:$matchinfo),
79  (match (wip_match_opcode G_FNEG):$ffn,
80         [{ return Helper.matchFoldableFneg(*${ffn}, ${matchinfo}); }]),
81  (apply [{ Helper.applyFoldableFneg(*${ffn}, ${matchinfo}); }])>;
82
83// Combines which should only apply on SI/VI
84def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>;
85
86def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper<
87  "AMDGPUGenPreLegalizerCombinerHelper",
88  [all_combines, clamp_i64_to_i16, foldable_fneg]> {
89  let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule";
90  let StateClass = "AMDGPUPreLegalizerCombinerHelperState";
91  let AdditionalArguments = [];
92}
93
94def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper<
95  "AMDGPUGenPostLegalizerCombinerHelper",
96  [all_combines, gfx6gfx7_combines,
97   uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg,
98   rcp_sqrt_to_rsq]> {
99  let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule";
100  let StateClass = "AMDGPUPostLegalizerCombinerHelperState";
101  let AdditionalArguments = [];
102}
103
104def AMDGPURegBankCombinerHelper : GICombinerHelper<
105  "AMDGPUGenRegBankCombinerHelper", [zext_trunc_fold, int_minmax_to_med3, ptr_add_immed_chain]> {
106  let DisableRuleOption = "amdgpuregbankcombiner-disable-rule";
107  let StateClass = "AMDGPURegBankCombinerHelperState";
108  let AdditionalArguments = [];
109}
110