1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
14 #include "AArch64MachineFunctionInfo.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetObjectFile.h"
18 #include "AArch64TargetTransformInfo.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "TargetInfo/AArch64TargetInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/CSEConfigBase.h"
25 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
26 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
27 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
28 #include "llvm/CodeGen/GlobalISel/Localizer.h"
29 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
30 #include "llvm/CodeGen/MIRParser/MIParser.h"
31 #include "llvm/CodeGen/MachineScheduler.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/TargetPassConfig.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/InitializePasses.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCTargetOptions.h"
39 #include "llvm/Pass.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/TargetRegistry.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Transforms/CFGuard.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include <memory>
48 #include <string>
49 
50 using namespace llvm;
51 
52 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
53                                 cl::desc("Enable the CCMP formation pass"),
54                                 cl::init(true), cl::Hidden);
55 
56 static cl::opt<bool>
57     EnableCondBrTuning("aarch64-enable-cond-br-tune",
58                        cl::desc("Enable the conditional branch tuning pass"),
59                        cl::init(true), cl::Hidden);
60 
61 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
62                                cl::desc("Enable the machine combiner pass"),
63                                cl::init(true), cl::Hidden);
64 
65 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
66                                           cl::desc("Suppress STP for AArch64"),
67                                           cl::init(true), cl::Hidden);
68 
69 static cl::opt<bool> EnableAdvSIMDScalar(
70     "aarch64-enable-simd-scalar",
71     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
72     cl::init(false), cl::Hidden);
73 
74 static cl::opt<bool>
75     EnablePromoteConstant("aarch64-enable-promote-const",
76                           cl::desc("Enable the promote constant pass"),
77                           cl::init(true), cl::Hidden);
78 
79 static cl::opt<bool> EnableCollectLOH(
80     "aarch64-enable-collect-loh",
81     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
82     cl::init(true), cl::Hidden);
83 
84 static cl::opt<bool>
85     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
86                                   cl::desc("Enable the pass that removes dead"
87                                            " definitons and replaces stores to"
88                                            " them with stores to the zero"
89                                            " register"),
90                                   cl::init(true));
91 
92 static cl::opt<bool> EnableRedundantCopyElimination(
93     "aarch64-enable-copyelim",
94     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
95     cl::Hidden);
96 
97 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
98                                         cl::desc("Enable the load/store pair"
99                                                  " optimization pass"),
100                                         cl::init(true), cl::Hidden);
101 
102 static cl::opt<bool> EnableAtomicTidy(
103     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
104     cl::desc("Run SimplifyCFG after expanding atomic operations"
105              " to make use of cmpxchg flow-based information"),
106     cl::init(true));
107 
108 static cl::opt<bool>
109 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
110                         cl::desc("Run early if-conversion"),
111                         cl::init(true));
112 
113 static cl::opt<bool>
114     EnableCondOpt("aarch64-enable-condopt",
115                   cl::desc("Enable the condition optimizer pass"),
116                   cl::init(true), cl::Hidden);
117 
118 static cl::opt<bool>
119 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
120                 cl::desc("Work around Cortex-A53 erratum 835769"),
121                 cl::init(false));
122 
123 static cl::opt<bool>
124     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
125                  cl::desc("Enable optimizations on complex GEPs"),
126                  cl::init(false));
127 
128 static cl::opt<bool>
129     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
130                      cl::desc("Relax out of range conditional branches"));
131 
132 static cl::opt<bool> EnableCompressJumpTables(
133     "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
134     cl::desc("Use smallest entry possible for jump tables"));
135 
136 // FIXME: Unify control over GlobalMerge.
137 static cl::opt<cl::boolOrDefault>
138     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
139                       cl::desc("Enable the global merge pass"));
140 
141 static cl::opt<bool>
142     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
143                            cl::desc("Enable the loop data prefetch pass"),
144                            cl::init(true));
145 
146 static cl::opt<int> EnableGlobalISelAtO(
147     "aarch64-enable-global-isel-at-O", cl::Hidden,
148     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
149     cl::init(0));
150 
151 static cl::opt<bool>
152     EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
153                            cl::desc("Enable SVE intrinsic opts"),
154                            cl::init(true));
155 
156 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
157                                          cl::init(true), cl::Hidden);
158 
159 static cl::opt<bool>
160     EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
161                         cl::desc("Enable the AAcrh64 branch target pass"),
162                         cl::init(true));
163 
164 extern cl::opt<bool> EnableHomogeneousPrologEpilog;
165 
166 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
167   // Register the target.
168   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
169   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
170   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
171   RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
172   RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
173   auto PR = PassRegistry::getPassRegistry();
174   initializeGlobalISel(*PR);
175   initializeAArch64A53Fix835769Pass(*PR);
176   initializeAArch64A57FPLoadBalancingPass(*PR);
177   initializeAArch64AdvSIMDScalarPass(*PR);
178   initializeAArch64BranchTargetsPass(*PR);
179   initializeAArch64CollectLOHPass(*PR);
180   initializeAArch64CompressJumpTablesPass(*PR);
181   initializeAArch64ConditionalComparesPass(*PR);
182   initializeAArch64ConditionOptimizerPass(*PR);
183   initializeAArch64DeadRegisterDefinitionsPass(*PR);
184   initializeAArch64ExpandPseudoPass(*PR);
185   initializeAArch64LoadStoreOptPass(*PR);
186   initializeAArch64SIMDInstrOptPass(*PR);
187   initializeAArch64PreLegalizerCombinerPass(*PR);
188   initializeAArch64PostLegalizerCombinerPass(*PR);
189   initializeAArch64PostLegalizerLoweringPass(*PR);
190   initializeAArch64PostSelectOptimizePass(*PR);
191   initializeAArch64PromoteConstantPass(*PR);
192   initializeAArch64RedundantCopyEliminationPass(*PR);
193   initializeAArch64StorePairSuppressPass(*PR);
194   initializeFalkorHWPFFixPass(*PR);
195   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
196   initializeLDTLSCleanupPass(*PR);
197   initializeSVEIntrinsicOptsPass(*PR);
198   initializeAArch64SpeculationHardeningPass(*PR);
199   initializeAArch64SLSHardeningPass(*PR);
200   initializeAArch64StackTaggingPass(*PR);
201   initializeAArch64StackTaggingPreRAPass(*PR);
202   initializeAArch64LowerHomogeneousPrologEpilogPass(*PR);
203 }
204 
205 //===----------------------------------------------------------------------===//
206 // AArch64 Lowering public interface.
207 //===----------------------------------------------------------------------===//
208 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
209   if (TT.isOSBinFormatMachO())
210     return std::make_unique<AArch64_MachoTargetObjectFile>();
211   if (TT.isOSBinFormatCOFF())
212     return std::make_unique<AArch64_COFFTargetObjectFile>();
213 
214   return std::make_unique<AArch64_ELFTargetObjectFile>();
215 }
216 
217 // Helper function to build a DataLayout string
218 static std::string computeDataLayout(const Triple &TT,
219                                      const MCTargetOptions &Options,
220                                      bool LittleEndian) {
221   if (TT.isOSBinFormatMachO()) {
222     if (TT.getArch() == Triple::aarch64_32)
223       return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
224     return "e-m:o-i64:64-i128:128-n32:64-S128";
225   }
226   if (TT.isOSBinFormatCOFF())
227     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
228   std::string Endian = LittleEndian ? "e" : "E";
229   std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
230   return Endian + "-m:e" + Ptr32 +
231          "-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
232 }
233 
234 static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {
235   if (CPU.empty() && TT.isArm64e())
236     return "apple-a12";
237   return CPU;
238 }
239 
240 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
241                                            Optional<Reloc::Model> RM) {
242   // AArch64 Darwin and Windows are always PIC.
243   if (TT.isOSDarwin() || TT.isOSWindows())
244     return Reloc::PIC_;
245   // On ELF platforms the default static relocation model has a smart enough
246   // linker to cope with referencing external symbols defined in a shared
247   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
248   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
249     return Reloc::Static;
250   return *RM;
251 }
252 
253 static CodeModel::Model
254 getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
255                              bool JIT) {
256   if (CM) {
257     if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
258         *CM != CodeModel::Large) {
259       report_fatal_error(
260           "Only small, tiny and large code models are allowed on AArch64");
261     } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
262       report_fatal_error("tiny code model is only supported on ELF");
263     return *CM;
264   }
265   // The default MCJIT memory managers make no guarantees about where they can
266   // find an executable page; JITed code needs to be able to refer to globals
267   // no matter how far away they are.
268   // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
269   // since with large code model LLVM generating 4 MOV instructions, and
270   // Windows doesn't support relocating these long branch (4 MOVs).
271   if (JIT && !TT.isOSWindows())
272     return CodeModel::Large;
273   return CodeModel::Small;
274 }
275 
276 /// Create an AArch64 architecture model.
277 ///
278 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
279                                            StringRef CPU, StringRef FS,
280                                            const TargetOptions &Options,
281                                            Optional<Reloc::Model> RM,
282                                            Optional<CodeModel::Model> CM,
283                                            CodeGenOpt::Level OL, bool JIT,
284                                            bool LittleEndian)
285     : LLVMTargetMachine(T,
286                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
287                         TT, computeDefaultCPU(TT, CPU), FS, Options,
288                         getEffectiveRelocModel(TT, RM),
289                         getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
290       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
291   initAsmInfo();
292 
293   if (TT.isOSBinFormatMachO()) {
294     this->Options.TrapUnreachable = true;
295     this->Options.NoTrapAfterNoreturn = true;
296   }
297 
298   if (getMCAsmInfo()->usesWindowsCFI()) {
299     // Unwinding can get confused if the last instruction in an
300     // exception-handling region (function, funclet, try block, etc.)
301     // is a call.
302     //
303     // FIXME: We could elide the trap if the next instruction would be in
304     // the same region anyway.
305     this->Options.TrapUnreachable = true;
306   }
307 
308   if (this->Options.TLSSize == 0) // default
309     this->Options.TLSSize = 24;
310   if ((getCodeModel() == CodeModel::Small ||
311        getCodeModel() == CodeModel::Kernel) &&
312       this->Options.TLSSize > 32)
313     // for the small (and kernel) code model, the maximum TLS size is 4GiB
314     this->Options.TLSSize = 32;
315   else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
316     // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
317     this->Options.TLSSize = 24;
318 
319   // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
320   // MachO/CodeModel::Large, which GlobalISel does not support.
321   if (getOptLevel() <= EnableGlobalISelAtO &&
322       TT.getArch() != Triple::aarch64_32 &&
323       TT.getEnvironment() != Triple::GNUILP32 &&
324       !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
325     setGlobalISel(true);
326     setGlobalISelAbort(GlobalISelAbortMode::Disable);
327   }
328 
329   // AArch64 supports the MachineOutliner.
330   setMachineOutliner(true);
331 
332   // AArch64 supports default outlining behaviour.
333   setSupportsDefaultOutlining(true);
334 
335   // AArch64 supports the debug entry values.
336   setSupportsDebugEntryValues(true);
337 }
338 
339 AArch64TargetMachine::~AArch64TargetMachine() = default;
340 
341 const AArch64Subtarget *
342 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
343   Attribute CPUAttr = F.getFnAttribute("target-cpu");
344   Attribute FSAttr = F.getFnAttribute("target-features");
345 
346   std::string CPU =
347       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
348   std::string FS =
349       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
350 
351   auto &I = SubtargetMap[CPU + FS];
352   if (!I) {
353     // This needs to be done before we create a new subtarget since any
354     // creation will depend on the TM and the code generation flags on the
355     // function that reside in TargetOptions.
356     resetTargetOptions(F);
357     I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
358                                             isLittle);
359   }
360   return I.get();
361 }
362 
363 void AArch64leTargetMachine::anchor() { }
364 
365 AArch64leTargetMachine::AArch64leTargetMachine(
366     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
367     const TargetOptions &Options, Optional<Reloc::Model> RM,
368     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
369     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
370 
371 void AArch64beTargetMachine::anchor() { }
372 
373 AArch64beTargetMachine::AArch64beTargetMachine(
374     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
375     const TargetOptions &Options, Optional<Reloc::Model> RM,
376     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
377     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
378 
379 namespace {
380 
381 /// AArch64 Code Generator Pass Configuration Options.
382 class AArch64PassConfig : public TargetPassConfig {
383 public:
384   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
385       : TargetPassConfig(TM, PM) {
386     if (TM.getOptLevel() != CodeGenOpt::None)
387       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
388   }
389 
390   AArch64TargetMachine &getAArch64TargetMachine() const {
391     return getTM<AArch64TargetMachine>();
392   }
393 
394   ScheduleDAGInstrs *
395   createMachineScheduler(MachineSchedContext *C) const override {
396     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
397     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
398     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
399     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
400     if (ST.hasFusion())
401       DAG->addMutation(createAArch64MacroFusionDAGMutation());
402     return DAG;
403   }
404 
405   ScheduleDAGInstrs *
406   createPostMachineScheduler(MachineSchedContext *C) const override {
407     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
408     if (ST.hasFusion()) {
409       // Run the Macro Fusion after RA again since literals are expanded from
410       // pseudos then (v. addPreSched2()).
411       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
412       DAG->addMutation(createAArch64MacroFusionDAGMutation());
413       return DAG;
414     }
415 
416     return nullptr;
417   }
418 
419   void addIRPasses()  override;
420   bool addPreISel() override;
421   bool addInstSelector() override;
422   bool addIRTranslator() override;
423   void addPreLegalizeMachineIR() override;
424   bool addLegalizeMachineIR() override;
425   void addPreRegBankSelect() override;
426   bool addRegBankSelect() override;
427   void addPreGlobalInstructionSelect() override;
428   bool addGlobalInstructionSelect() override;
429   bool addILPOpts() override;
430   void addPreRegAlloc() override;
431   void addPostRegAlloc() override;
432   void addPreSched2() override;
433   void addPreEmitPass() override;
434 
435   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
436 };
437 
438 } // end anonymous namespace
439 
440 TargetTransformInfo
441 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
442   return TargetTransformInfo(AArch64TTIImpl(this, F));
443 }
444 
445 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
446   return new AArch64PassConfig(*this, PM);
447 }
448 
449 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
450   return getStandardCSEConfigForOpt(TM->getOptLevel());
451 }
452 
453 void AArch64PassConfig::addIRPasses() {
454   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
455   // ourselves.
456   addPass(createAtomicExpandPass());
457 
458   // Expand any SVE vector library calls that we can't code generate directly.
459   if (EnableSVEIntrinsicOpts && TM->getOptLevel() == CodeGenOpt::Aggressive)
460     addPass(createSVEIntrinsicOptsPass());
461 
462   // Cmpxchg instructions are often used with a subsequent comparison to
463   // determine whether it succeeded. We can exploit existing control-flow in
464   // ldrex/strex loops to simplify this, but it needs tidying up.
465   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
466     addPass(createCFGSimplificationPass(SimplifyCFGOptions()
467                                             .forwardSwitchCondToPhi(true)
468                                             .convertSwitchToLookupTable(true)
469                                             .needCanonicalLoops(false)
470                                             .hoistCommonInsts(true)
471                                             .sinkCommonInsts(true)));
472 
473   // Run LoopDataPrefetch
474   //
475   // Run this before LSR to remove the multiplies involved in computing the
476   // pointer values N iterations ahead.
477   if (TM->getOptLevel() != CodeGenOpt::None) {
478     if (EnableLoopDataPrefetch)
479       addPass(createLoopDataPrefetchPass());
480     if (EnableFalkorHWPFFix)
481       addPass(createFalkorMarkStridedAccessesPass());
482   }
483 
484   TargetPassConfig::addIRPasses();
485 
486   addPass(createAArch64StackTaggingPass(
487       /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
488 
489   // Match interleaved memory accesses to ldN/stN intrinsics.
490   if (TM->getOptLevel() != CodeGenOpt::None) {
491     addPass(createInterleavedLoadCombinePass());
492     addPass(createInterleavedAccessPass());
493   }
494 
495   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
496     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
497     // and lower a GEP with multiple indices to either arithmetic operations or
498     // multiple GEPs with single index.
499     addPass(createSeparateConstOffsetFromGEPPass(true));
500     // Call EarlyCSE pass to find and remove subexpressions in the lowered
501     // result.
502     addPass(createEarlyCSEPass());
503     // Do loop invariant code motion in case part of the lowered result is
504     // invariant.
505     addPass(createLICMPass());
506   }
507 
508   // Add Control Flow Guard checks.
509   if (TM->getTargetTriple().isOSWindows())
510     addPass(createCFGuardCheckPass());
511 }
512 
513 // Pass Pipeline Configuration
514 bool AArch64PassConfig::addPreISel() {
515   // Run promote constant before global merge, so that the promoted constants
516   // get a chance to be merged
517   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
518     addPass(createAArch64PromoteConstantPass());
519   // FIXME: On AArch64, this depends on the type.
520   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
521   // and the offset has to be a multiple of the related size in bytes.
522   if ((TM->getOptLevel() != CodeGenOpt::None &&
523        EnableGlobalMerge == cl::BOU_UNSET) ||
524       EnableGlobalMerge == cl::BOU_TRUE) {
525     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
526                                (EnableGlobalMerge == cl::BOU_UNSET);
527 
528     // Merging of extern globals is enabled by default on non-Mach-O as we
529     // expect it to be generally either beneficial or harmless. On Mach-O it
530     // is disabled as we emit the .subsections_via_symbols directive which
531     // means that merging extern globals is not safe.
532     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
533 
534     // FIXME: extern global merging is only enabled when we optimise for size
535     // because there are some regressions with it also enabled for performance.
536     if (!OnlyOptimizeForSize)
537       MergeExternalByDefault = false;
538 
539     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
540                                   MergeExternalByDefault));
541   }
542 
543   return false;
544 }
545 
546 bool AArch64PassConfig::addInstSelector() {
547   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
548 
549   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
550   // references to _TLS_MODULE_BASE_ as possible.
551   if (TM->getTargetTriple().isOSBinFormatELF() &&
552       getOptLevel() != CodeGenOpt::None)
553     addPass(createAArch64CleanupLocalDynamicTLSPass());
554 
555   return false;
556 }
557 
558 bool AArch64PassConfig::addIRTranslator() {
559   addPass(new IRTranslator(getOptLevel()));
560   return false;
561 }
562 
563 void AArch64PassConfig::addPreLegalizeMachineIR() {
564   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
565   addPass(createAArch64PreLegalizerCombiner(IsOptNone));
566 }
567 
568 bool AArch64PassConfig::addLegalizeMachineIR() {
569   addPass(new Legalizer());
570   return false;
571 }
572 
573 void AArch64PassConfig::addPreRegBankSelect() {
574   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
575   if (!IsOptNone)
576     addPass(createAArch64PostLegalizerCombiner(IsOptNone));
577   addPass(createAArch64PostLegalizerLowering());
578 }
579 
580 bool AArch64PassConfig::addRegBankSelect() {
581   addPass(new RegBankSelect());
582   return false;
583 }
584 
585 void AArch64PassConfig::addPreGlobalInstructionSelect() {
586   addPass(new Localizer());
587 }
588 
589 bool AArch64PassConfig::addGlobalInstructionSelect() {
590   addPass(new InstructionSelect());
591   if (getOptLevel() != CodeGenOpt::None)
592     addPass(createAArch64PostSelectOptimize());
593   return false;
594 }
595 
596 bool AArch64PassConfig::addILPOpts() {
597   if (EnableCondOpt)
598     addPass(createAArch64ConditionOptimizerPass());
599   if (EnableCCMP)
600     addPass(createAArch64ConditionalCompares());
601   if (EnableMCR)
602     addPass(&MachineCombinerID);
603   if (EnableCondBrTuning)
604     addPass(createAArch64CondBrTuning());
605   if (EnableEarlyIfConversion)
606     addPass(&EarlyIfConverterID);
607   if (EnableStPairSuppress)
608     addPass(createAArch64StorePairSuppressPass());
609   addPass(createAArch64SIMDInstrOptPass());
610   if (TM->getOptLevel() != CodeGenOpt::None)
611     addPass(createAArch64StackTaggingPreRAPass());
612   return true;
613 }
614 
615 void AArch64PassConfig::addPreRegAlloc() {
616   // Change dead register definitions to refer to the zero register.
617   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
618     addPass(createAArch64DeadRegisterDefinitions());
619 
620   // Use AdvSIMD scalar instructions whenever profitable.
621   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
622     addPass(createAArch64AdvSIMDScalar());
623     // The AdvSIMD pass may produce copies that can be rewritten to
624     // be register coalescer friendly.
625     addPass(&PeepholeOptimizerID);
626   }
627 }
628 
629 void AArch64PassConfig::addPostRegAlloc() {
630   // Remove redundant copy instructions.
631   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
632     addPass(createAArch64RedundantCopyEliminationPass());
633 
634   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
635     // Improve performance for some FP/SIMD code for A57.
636     addPass(createAArch64A57FPLoadBalancing());
637 }
638 
639 void AArch64PassConfig::addPreSched2() {
640   // Lower homogeneous frame instructions
641   if (EnableHomogeneousPrologEpilog)
642     addPass(createAArch64LowerHomogeneousPrologEpilogPass());
643   // Expand some pseudo instructions to allow proper scheduling.
644   addPass(createAArch64ExpandPseudoPass());
645   // Use load/store pair instructions when possible.
646   if (TM->getOptLevel() != CodeGenOpt::None) {
647     if (EnableLoadStoreOpt)
648       addPass(createAArch64LoadStoreOptimizationPass());
649   }
650 
651   // The AArch64SpeculationHardeningPass destroys dominator tree and natural
652   // loop info, which is needed for the FalkorHWPFFixPass and also later on.
653   // Therefore, run the AArch64SpeculationHardeningPass before the
654   // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
655   // info.
656   addPass(createAArch64SpeculationHardeningPass());
657 
658   addPass(createAArch64IndirectThunks());
659   addPass(createAArch64SLSHardeningPass());
660 
661   if (TM->getOptLevel() != CodeGenOpt::None) {
662     if (EnableFalkorHWPFFix)
663       addPass(createFalkorHWPFFixPass());
664   }
665 }
666 
667 void AArch64PassConfig::addPreEmitPass() {
668   // Machine Block Placement might have created new opportunities when run
669   // at O3, where the Tail Duplication Threshold is set to 4 instructions.
670   // Run the load/store optimizer once more.
671   if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
672     addPass(createAArch64LoadStoreOptimizationPass());
673 
674   if (EnableA53Fix835769)
675     addPass(createAArch64A53Fix835769());
676 
677   if (EnableBranchTargets)
678     addPass(createAArch64BranchTargetsPass());
679 
680   // Relax conditional branch instructions if they're otherwise out of
681   // range of their destination.
682   if (BranchRelaxation)
683     addPass(&BranchRelaxationPassID);
684 
685   // Identify valid longjmp targets for Windows Control Flow Guard.
686   if (TM->getTargetTriple().isOSWindows())
687     addPass(createCFGuardLongjmpPass());
688 
689   if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
690     addPass(createAArch64CompressJumpTablesPass());
691 
692   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
693       TM->getTargetTriple().isOSBinFormatMachO())
694     addPass(createAArch64CollectLOHPass());
695 
696   // SVE bundles move prefixes with destructive operations.
697   addPass(createUnpackMachineBundles(nullptr));
698 }
699 
700 yaml::MachineFunctionInfo *
701 AArch64TargetMachine::createDefaultFuncInfoYAML() const {
702   return new yaml::AArch64FunctionInfo();
703 }
704 
705 yaml::MachineFunctionInfo *
706 AArch64TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
707   const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
708   return new yaml::AArch64FunctionInfo(*MFI);
709 }
710 
711 bool AArch64TargetMachine::parseMachineFunctionInfo(
712     const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
713     SMDiagnostic &Error, SMRange &SourceRange) const {
714   const auto &YamlMFI =
715       reinterpret_cast<const yaml::AArch64FunctionInfo &>(MFI);
716   MachineFunction &MF = PFS.MF;
717   MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
718   return false;
719 }
720