1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
14 #include "AArch64MacroFusion.h"
15 #include "AArch64Subtarget.h"
16 #include "AArch64TargetObjectFile.h"
17 #include "AArch64TargetTransformInfo.h"
18 #include "MCTargetDesc/AArch64MCTargetDesc.h"
19 #include "TargetInfo/AArch64TargetInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/CSEConfigBase.h"
24 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
25 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
26 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
27 #include "llvm/CodeGen/GlobalISel/Localizer.h"
28 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
29 #include "llvm/CodeGen/MachineScheduler.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/CodeGen/TargetPassConfig.h"
32 #include "llvm/IR/Attributes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/InitializePasses.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCTargetOptions.h"
37 #include "llvm/Pass.h"
38 #include "llvm/Support/CodeGen.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Transforms/CFGuard.h"
44 #include "llvm/Transforms/Scalar.h"
45 #include <memory>
46 #include <string>
47 
48 using namespace llvm;
49 
50 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
51                                 cl::desc("Enable the CCMP formation pass"),
52                                 cl::init(true), cl::Hidden);
53 
54 static cl::opt<bool>
55     EnableCondBrTuning("aarch64-enable-cond-br-tune",
56                        cl::desc("Enable the conditional branch tuning pass"),
57                        cl::init(true), cl::Hidden);
58 
59 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
60                                cl::desc("Enable the machine combiner pass"),
61                                cl::init(true), cl::Hidden);
62 
63 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
64                                           cl::desc("Suppress STP for AArch64"),
65                                           cl::init(true), cl::Hidden);
66 
67 static cl::opt<bool> EnableAdvSIMDScalar(
68     "aarch64-enable-simd-scalar",
69     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
70     cl::init(false), cl::Hidden);
71 
72 static cl::opt<bool>
73     EnablePromoteConstant("aarch64-enable-promote-const",
74                           cl::desc("Enable the promote constant pass"),
75                           cl::init(true), cl::Hidden);
76 
77 static cl::opt<bool> EnableCollectLOH(
78     "aarch64-enable-collect-loh",
79     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
80     cl::init(true), cl::Hidden);
81 
82 static cl::opt<bool>
83     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
84                                   cl::desc("Enable the pass that removes dead"
85                                            " definitons and replaces stores to"
86                                            " them with stores to the zero"
87                                            " register"),
88                                   cl::init(true));
89 
90 static cl::opt<bool> EnableRedundantCopyElimination(
91     "aarch64-enable-copyelim",
92     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
93     cl::Hidden);
94 
95 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
96                                         cl::desc("Enable the load/store pair"
97                                                  " optimization pass"),
98                                         cl::init(true), cl::Hidden);
99 
100 static cl::opt<bool> EnableAtomicTidy(
101     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
102     cl::desc("Run SimplifyCFG after expanding atomic operations"
103              " to make use of cmpxchg flow-based information"),
104     cl::init(true));
105 
106 static cl::opt<bool>
107 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
108                         cl::desc("Run early if-conversion"),
109                         cl::init(true));
110 
111 static cl::opt<bool>
112     EnableCondOpt("aarch64-enable-condopt",
113                   cl::desc("Enable the condition optimizer pass"),
114                   cl::init(true), cl::Hidden);
115 
116 static cl::opt<bool>
117 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
118                 cl::desc("Work around Cortex-A53 erratum 835769"),
119                 cl::init(false));
120 
121 static cl::opt<bool>
122     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
123                  cl::desc("Enable optimizations on complex GEPs"),
124                  cl::init(false));
125 
126 static cl::opt<bool>
127     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
128                      cl::desc("Relax out of range conditional branches"));
129 
130 static cl::opt<bool> EnableCompressJumpTables(
131     "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
132     cl::desc("Use smallest entry possible for jump tables"));
133 
134 // FIXME: Unify control over GlobalMerge.
135 static cl::opt<cl::boolOrDefault>
136     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
137                       cl::desc("Enable the global merge pass"));
138 
139 static cl::opt<bool>
140     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
141                            cl::desc("Enable the loop data prefetch pass"),
142                            cl::init(true));
143 
144 static cl::opt<int> EnableGlobalISelAtO(
145     "aarch64-enable-global-isel-at-O", cl::Hidden,
146     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
147     cl::init(0));
148 
149 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
150                                          cl::init(true), cl::Hidden);
151 
152 static cl::opt<bool>
153     EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
154                         cl::desc("Enable the AAcrh64 branch target pass"),
155                         cl::init(true));
156 
157 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
158   // Register the target.
159   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
160   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
161   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
162   RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
163   RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
164   auto PR = PassRegistry::getPassRegistry();
165   initializeGlobalISel(*PR);
166   initializeAArch64A53Fix835769Pass(*PR);
167   initializeAArch64A57FPLoadBalancingPass(*PR);
168   initializeAArch64AdvSIMDScalarPass(*PR);
169   initializeAArch64BranchTargetsPass(*PR);
170   initializeAArch64CollectLOHPass(*PR);
171   initializeAArch64CompressJumpTablesPass(*PR);
172   initializeAArch64ConditionalComparesPass(*PR);
173   initializeAArch64ConditionOptimizerPass(*PR);
174   initializeAArch64DeadRegisterDefinitionsPass(*PR);
175   initializeAArch64ExpandPseudoPass(*PR);
176   initializeAArch64LoadStoreOptPass(*PR);
177   initializeAArch64SIMDInstrOptPass(*PR);
178   initializeAArch64PreLegalizerCombinerPass(*PR);
179   initializeAArch64PromoteConstantPass(*PR);
180   initializeAArch64RedundantCopyEliminationPass(*PR);
181   initializeAArch64StorePairSuppressPass(*PR);
182   initializeFalkorHWPFFixPass(*PR);
183   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
184   initializeLDTLSCleanupPass(*PR);
185   initializeAArch64SpeculationHardeningPass(*PR);
186   initializeAArch64StackTaggingPass(*PR);
187   initializeAArch64StackTaggingPreRAPass(*PR);
188 }
189 
190 //===----------------------------------------------------------------------===//
191 // AArch64 Lowering public interface.
192 //===----------------------------------------------------------------------===//
193 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
194   if (TT.isOSBinFormatMachO())
195     return std::make_unique<AArch64_MachoTargetObjectFile>();
196   if (TT.isOSBinFormatCOFF())
197     return std::make_unique<AArch64_COFFTargetObjectFile>();
198 
199   return std::make_unique<AArch64_ELFTargetObjectFile>();
200 }
201 
202 // Helper function to build a DataLayout string
203 static std::string computeDataLayout(const Triple &TT,
204                                      const MCTargetOptions &Options,
205                                      bool LittleEndian) {
206   if (Options.getABIName() == "ilp32")
207     return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
208   if (TT.isOSBinFormatMachO()) {
209     if (TT.getArch() == Triple::aarch64_32)
210       return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
211     return "e-m:o-i64:64-i128:128-n32:64-S128";
212   }
213   if (TT.isOSBinFormatCOFF())
214     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
215   if (LittleEndian)
216     return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
217   return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
218 }
219 
220 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
221                                            Optional<Reloc::Model> RM) {
222   // AArch64 Darwin and Windows are always PIC.
223   if (TT.isOSDarwin() || TT.isOSWindows())
224     return Reloc::PIC_;
225   // On ELF platforms the default static relocation model has a smart enough
226   // linker to cope with referencing external symbols defined in a shared
227   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
228   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
229     return Reloc::Static;
230   return *RM;
231 }
232 
233 static CodeModel::Model
234 getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
235                              bool JIT) {
236   if (CM) {
237     if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
238         *CM != CodeModel::Large) {
239       report_fatal_error(
240           "Only small, tiny and large code models are allowed on AArch64");
241     } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
242       report_fatal_error("tiny code model is only supported on ELF");
243     return *CM;
244   }
245   // The default MCJIT memory managers make no guarantees about where they can
246   // find an executable page; JITed code needs to be able to refer to globals
247   // no matter how far away they are.
248   // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
249   // since with large code model LLVM generating 4 MOV instructions, and
250   // Windows doesn't support relocating these long branch (4 MOVs).
251   if (JIT && !TT.isOSWindows())
252     return CodeModel::Large;
253   return CodeModel::Small;
254 }
255 
256 /// Create an AArch64 architecture model.
257 ///
258 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
259                                            StringRef CPU, StringRef FS,
260                                            const TargetOptions &Options,
261                                            Optional<Reloc::Model> RM,
262                                            Optional<CodeModel::Model> CM,
263                                            CodeGenOpt::Level OL, bool JIT,
264                                            bool LittleEndian)
265     : LLVMTargetMachine(T,
266                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
267                         TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
268                         getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
269       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
270   initAsmInfo();
271 
272   if (TT.isOSBinFormatMachO()) {
273     this->Options.TrapUnreachable = true;
274     this->Options.NoTrapAfterNoreturn = true;
275   }
276 
277   if (getMCAsmInfo()->usesWindowsCFI()) {
278     // Unwinding can get confused if the last instruction in an
279     // exception-handling region (function, funclet, try block, etc.)
280     // is a call.
281     //
282     // FIXME: We could elide the trap if the next instruction would be in
283     // the same region anyway.
284     this->Options.TrapUnreachable = true;
285   }
286 
287   if (this->Options.TLSSize == 0) // default
288     this->Options.TLSSize = 24;
289   if ((getCodeModel() == CodeModel::Small ||
290        getCodeModel() == CodeModel::Kernel) &&
291       this->Options.TLSSize > 32)
292     // for the small (and kernel) code model, the maximum TLS size is 4GiB
293     this->Options.TLSSize = 32;
294   else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
295     // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
296     this->Options.TLSSize = 24;
297 
298   // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
299   // MachO/CodeModel::Large, which GlobalISel does not support.
300   if (getOptLevel() <= EnableGlobalISelAtO &&
301       TT.getArch() != Triple::aarch64_32 &&
302       !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
303     setGlobalISel(true);
304     setGlobalISelAbort(GlobalISelAbortMode::Disable);
305   }
306 
307   // AArch64 supports the MachineOutliner.
308   setMachineOutliner(true);
309 
310   // AArch64 supports default outlining behaviour.
311   setSupportsDefaultOutlining(true);
312 
313   // AArch64 supports the debug entry values.
314   setSupportsDebugEntryValues(true);
315 }
316 
317 AArch64TargetMachine::~AArch64TargetMachine() = default;
318 
319 const AArch64Subtarget *
320 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
321   Attribute CPUAttr = F.getFnAttribute("target-cpu");
322   Attribute FSAttr = F.getFnAttribute("target-features");
323 
324   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
325                         ? CPUAttr.getValueAsString().str()
326                         : TargetCPU;
327   std::string FS = !FSAttr.hasAttribute(Attribute::None)
328                        ? FSAttr.getValueAsString().str()
329                        : TargetFS;
330 
331   auto &I = SubtargetMap[CPU + FS];
332   if (!I) {
333     // This needs to be done before we create a new subtarget since any
334     // creation will depend on the TM and the code generation flags on the
335     // function that reside in TargetOptions.
336     resetTargetOptions(F);
337     I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
338                                             isLittle);
339   }
340   return I.get();
341 }
342 
343 void AArch64leTargetMachine::anchor() { }
344 
345 AArch64leTargetMachine::AArch64leTargetMachine(
346     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
347     const TargetOptions &Options, Optional<Reloc::Model> RM,
348     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
349     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
350 
351 void AArch64beTargetMachine::anchor() { }
352 
353 AArch64beTargetMachine::AArch64beTargetMachine(
354     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
355     const TargetOptions &Options, Optional<Reloc::Model> RM,
356     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
357     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
358 
359 namespace {
360 
361 /// AArch64 Code Generator Pass Configuration Options.
362 class AArch64PassConfig : public TargetPassConfig {
363 public:
364   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
365       : TargetPassConfig(TM, PM) {
366     if (TM.getOptLevel() != CodeGenOpt::None)
367       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
368   }
369 
370   AArch64TargetMachine &getAArch64TargetMachine() const {
371     return getTM<AArch64TargetMachine>();
372   }
373 
374   ScheduleDAGInstrs *
375   createMachineScheduler(MachineSchedContext *C) const override {
376     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
377     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
378     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
379     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
380     if (ST.hasFusion())
381       DAG->addMutation(createAArch64MacroFusionDAGMutation());
382     return DAG;
383   }
384 
385   ScheduleDAGInstrs *
386   createPostMachineScheduler(MachineSchedContext *C) const override {
387     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
388     if (ST.hasFusion()) {
389       // Run the Macro Fusion after RA again since literals are expanded from
390       // pseudos then (v. addPreSched2()).
391       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
392       DAG->addMutation(createAArch64MacroFusionDAGMutation());
393       return DAG;
394     }
395 
396     return nullptr;
397   }
398 
399   void addIRPasses()  override;
400   bool addPreISel() override;
401   bool addInstSelector() override;
402   bool addIRTranslator() override;
403   void addPreLegalizeMachineIR() override;
404   bool addLegalizeMachineIR() override;
405   bool addRegBankSelect() override;
406   void addPreGlobalInstructionSelect() override;
407   bool addGlobalInstructionSelect() override;
408   bool addILPOpts() override;
409   void addPreRegAlloc() override;
410   void addPostRegAlloc() override;
411   void addPreSched2() override;
412   void addPreEmitPass() override;
413 
414   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
415 };
416 
417 } // end anonymous namespace
418 
419 TargetTransformInfo
420 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
421   return TargetTransformInfo(AArch64TTIImpl(this, F));
422 }
423 
424 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
425   return new AArch64PassConfig(*this, PM);
426 }
427 
428 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
429   return getStandardCSEConfigForOpt(TM->getOptLevel());
430 }
431 
432 void AArch64PassConfig::addIRPasses() {
433   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
434   // ourselves.
435   addPass(createAtomicExpandPass());
436 
437   // Cmpxchg instructions are often used with a subsequent comparison to
438   // determine whether it succeeded. We can exploit existing control-flow in
439   // ldrex/strex loops to simplify this, but it needs tidying up.
440   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
441     addPass(createCFGSimplificationPass(1, true, true, false, true));
442 
443   // Run LoopDataPrefetch
444   //
445   // Run this before LSR to remove the multiplies involved in computing the
446   // pointer values N iterations ahead.
447   if (TM->getOptLevel() != CodeGenOpt::None) {
448     if (EnableLoopDataPrefetch)
449       addPass(createLoopDataPrefetchPass());
450     if (EnableFalkorHWPFFix)
451       addPass(createFalkorMarkStridedAccessesPass());
452   }
453 
454   TargetPassConfig::addIRPasses();
455 
456   // Match interleaved memory accesses to ldN/stN intrinsics.
457   if (TM->getOptLevel() != CodeGenOpt::None) {
458     addPass(createInterleavedLoadCombinePass());
459     addPass(createInterleavedAccessPass());
460   }
461 
462   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
463     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
464     // and lower a GEP with multiple indices to either arithmetic operations or
465     // multiple GEPs with single index.
466     addPass(createSeparateConstOffsetFromGEPPass(true));
467     // Call EarlyCSE pass to find and remove subexpressions in the lowered
468     // result.
469     addPass(createEarlyCSEPass());
470     // Do loop invariant code motion in case part of the lowered result is
471     // invariant.
472     addPass(createLICMPass());
473   }
474 
475   addPass(createAArch64StackTaggingPass(/* MergeInit = */ TM->getOptLevel() !=
476                                         CodeGenOpt::None));
477 
478   // Add Control Flow Guard checks.
479   if (TM->getTargetTriple().isOSWindows())
480     addPass(createCFGuardCheckPass());
481 }
482 
483 // Pass Pipeline Configuration
484 bool AArch64PassConfig::addPreISel() {
485   // Run promote constant before global merge, so that the promoted constants
486   // get a chance to be merged
487   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
488     addPass(createAArch64PromoteConstantPass());
489   // FIXME: On AArch64, this depends on the type.
490   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
491   // and the offset has to be a multiple of the related size in bytes.
492   if ((TM->getOptLevel() != CodeGenOpt::None &&
493        EnableGlobalMerge == cl::BOU_UNSET) ||
494       EnableGlobalMerge == cl::BOU_TRUE) {
495     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
496                                (EnableGlobalMerge == cl::BOU_UNSET);
497 
498     // Merging of extern globals is enabled by default on non-Mach-O as we
499     // expect it to be generally either beneficial or harmless. On Mach-O it
500     // is disabled as we emit the .subsections_via_symbols directive which
501     // means that merging extern globals is not safe.
502     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
503 
504     // FIXME: extern global merging is only enabled when we optimise for size
505     // because there are some regressions with it also enabled for performance.
506     if (!OnlyOptimizeForSize)
507       MergeExternalByDefault = false;
508 
509     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
510                                   MergeExternalByDefault));
511   }
512 
513   return false;
514 }
515 
516 bool AArch64PassConfig::addInstSelector() {
517   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
518 
519   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
520   // references to _TLS_MODULE_BASE_ as possible.
521   if (TM->getTargetTriple().isOSBinFormatELF() &&
522       getOptLevel() != CodeGenOpt::None)
523     addPass(createAArch64CleanupLocalDynamicTLSPass());
524 
525   return false;
526 }
527 
528 bool AArch64PassConfig::addIRTranslator() {
529   addPass(new IRTranslator());
530   return false;
531 }
532 
533 void AArch64PassConfig::addPreLegalizeMachineIR() {
534   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
535   addPass(createAArch64PreLegalizeCombiner(IsOptNone));
536 }
537 
538 bool AArch64PassConfig::addLegalizeMachineIR() {
539   addPass(new Legalizer());
540   return false;
541 }
542 
543 bool AArch64PassConfig::addRegBankSelect() {
544   addPass(new RegBankSelect());
545   return false;
546 }
547 
548 void AArch64PassConfig::addPreGlobalInstructionSelect() {
549   addPass(new Localizer());
550 }
551 
552 bool AArch64PassConfig::addGlobalInstructionSelect() {
553   addPass(new InstructionSelect());
554   return false;
555 }
556 
557 bool AArch64PassConfig::addILPOpts() {
558   if (EnableCondOpt)
559     addPass(createAArch64ConditionOptimizerPass());
560   if (EnableCCMP)
561     addPass(createAArch64ConditionalCompares());
562   if (EnableMCR)
563     addPass(&MachineCombinerID);
564   if (EnableCondBrTuning)
565     addPass(createAArch64CondBrTuning());
566   if (EnableEarlyIfConversion)
567     addPass(&EarlyIfConverterID);
568   if (EnableStPairSuppress)
569     addPass(createAArch64StorePairSuppressPass());
570   addPass(createAArch64SIMDInstrOptPass());
571   if (TM->getOptLevel() != CodeGenOpt::None)
572     addPass(createAArch64StackTaggingPreRAPass());
573   return true;
574 }
575 
576 void AArch64PassConfig::addPreRegAlloc() {
577   // Change dead register definitions to refer to the zero register.
578   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
579     addPass(createAArch64DeadRegisterDefinitions());
580 
581   // Use AdvSIMD scalar instructions whenever profitable.
582   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
583     addPass(createAArch64AdvSIMDScalar());
584     // The AdvSIMD pass may produce copies that can be rewritten to
585     // be register coalescer friendly.
586     addPass(&PeepholeOptimizerID);
587   }
588 }
589 
590 void AArch64PassConfig::addPostRegAlloc() {
591   // Remove redundant copy instructions.
592   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
593     addPass(createAArch64RedundantCopyEliminationPass());
594 
595   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
596     // Improve performance for some FP/SIMD code for A57.
597     addPass(createAArch64A57FPLoadBalancing());
598 }
599 
600 void AArch64PassConfig::addPreSched2() {
601   // Expand some pseudo instructions to allow proper scheduling.
602   addPass(createAArch64ExpandPseudoPass());
603   // Use load/store pair instructions when possible.
604   if (TM->getOptLevel() != CodeGenOpt::None) {
605     if (EnableLoadStoreOpt)
606       addPass(createAArch64LoadStoreOptimizationPass());
607   }
608 
609   // The AArch64SpeculationHardeningPass destroys dominator tree and natural
610   // loop info, which is needed for the FalkorHWPFFixPass and also later on.
611   // Therefore, run the AArch64SpeculationHardeningPass before the
612   // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
613   // info.
614   addPass(createAArch64SpeculationHardeningPass());
615 
616   if (TM->getOptLevel() != CodeGenOpt::None) {
617     if (EnableFalkorHWPFFix)
618       addPass(createFalkorHWPFFixPass());
619   }
620 }
621 
622 void AArch64PassConfig::addPreEmitPass() {
623   // Machine Block Placement might have created new opportunities when run
624   // at O3, where the Tail Duplication Threshold is set to 4 instructions.
625   // Run the load/store optimizer once more.
626   if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
627     addPass(createAArch64LoadStoreOptimizationPass());
628 
629   if (EnableA53Fix835769)
630     addPass(createAArch64A53Fix835769());
631 
632   if (EnableBranchTargets)
633     addPass(createAArch64BranchTargetsPass());
634 
635   // Relax conditional branch instructions if they're otherwise out of
636   // range of their destination.
637   if (BranchRelaxation)
638     addPass(&BranchRelaxationPassID);
639 
640   // Identify valid longjmp targets for Windows Control Flow Guard.
641   if (TM->getTargetTriple().isOSWindows())
642     addPass(createCFGuardLongjmpPass());
643 
644   if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
645     addPass(createAArch64CompressJumpTablesPass());
646 
647   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
648       TM->getTargetTriple().isOSBinFormatMachO())
649     addPass(createAArch64CollectLOHPass());
650 
651   // SVE bundles move prefixes with destructive operations.
652   addPass(createUnpackMachineBundles(nullptr));
653 }
654