1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
14 #include "AArch64MachineFunctionInfo.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetObjectFile.h"
18 #include "AArch64TargetTransformInfo.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "TargetInfo/AArch64TargetInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/CSEConfigBase.h"
25 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
26 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
27 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
28 #include "llvm/CodeGen/GlobalISel/Localizer.h"
29 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
30 #include "llvm/CodeGen/MIRParser/MIParser.h"
31 #include "llvm/CodeGen/MachineScheduler.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/TargetPassConfig.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/InitializePasses.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCTargetOptions.h"
39 #include "llvm/Pass.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/TargetRegistry.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Transforms/CFGuard.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include <memory>
48 #include <string>
49 
50 using namespace llvm;
51 
52 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
53                                 cl::desc("Enable the CCMP formation pass"),
54                                 cl::init(true), cl::Hidden);
55 
56 static cl::opt<bool>
57     EnableCondBrTuning("aarch64-enable-cond-br-tune",
58                        cl::desc("Enable the conditional branch tuning pass"),
59                        cl::init(true), cl::Hidden);
60 
61 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
62                                cl::desc("Enable the machine combiner pass"),
63                                cl::init(true), cl::Hidden);
64 
65 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
66                                           cl::desc("Suppress STP for AArch64"),
67                                           cl::init(true), cl::Hidden);
68 
69 static cl::opt<bool> EnableAdvSIMDScalar(
70     "aarch64-enable-simd-scalar",
71     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
72     cl::init(false), cl::Hidden);
73 
74 static cl::opt<bool>
75     EnablePromoteConstant("aarch64-enable-promote-const",
76                           cl::desc("Enable the promote constant pass"),
77                           cl::init(true), cl::Hidden);
78 
79 static cl::opt<bool> EnableCollectLOH(
80     "aarch64-enable-collect-loh",
81     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
82     cl::init(true), cl::Hidden);
83 
84 static cl::opt<bool>
85     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
86                                   cl::desc("Enable the pass that removes dead"
87                                            " definitons and replaces stores to"
88                                            " them with stores to the zero"
89                                            " register"),
90                                   cl::init(true));
91 
92 static cl::opt<bool> EnableRedundantCopyElimination(
93     "aarch64-enable-copyelim",
94     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
95     cl::Hidden);
96 
97 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
98                                         cl::desc("Enable the load/store pair"
99                                                  " optimization pass"),
100                                         cl::init(true), cl::Hidden);
101 
102 static cl::opt<bool> EnableAtomicTidy(
103     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
104     cl::desc("Run SimplifyCFG after expanding atomic operations"
105              " to make use of cmpxchg flow-based information"),
106     cl::init(true));
107 
108 static cl::opt<bool>
109 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
110                         cl::desc("Run early if-conversion"),
111                         cl::init(true));
112 
113 static cl::opt<bool>
114     EnableCondOpt("aarch64-enable-condopt",
115                   cl::desc("Enable the condition optimizer pass"),
116                   cl::init(true), cl::Hidden);
117 
118 static cl::opt<bool>
119 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
120                 cl::desc("Work around Cortex-A53 erratum 835769"),
121                 cl::init(false));
122 
123 static cl::opt<bool>
124     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
125                  cl::desc("Enable optimizations on complex GEPs"),
126                  cl::init(false));
127 
128 static cl::opt<bool>
129     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
130                      cl::desc("Relax out of range conditional branches"));
131 
132 static cl::opt<bool> EnableCompressJumpTables(
133     "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
134     cl::desc("Use smallest entry possible for jump tables"));
135 
136 // FIXME: Unify control over GlobalMerge.
137 static cl::opt<cl::boolOrDefault>
138     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
139                       cl::desc("Enable the global merge pass"));
140 
141 static cl::opt<bool>
142     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
143                            cl::desc("Enable the loop data prefetch pass"),
144                            cl::init(true));
145 
146 static cl::opt<int> EnableGlobalISelAtO(
147     "aarch64-enable-global-isel-at-O", cl::Hidden,
148     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
149     cl::init(0));
150 
151 static cl::opt<bool> EnableSVEIntrinsicOpts(
152     "aarch64-sve-intrinsic-opts", cl::Hidden,
153     cl::desc("Enable SVE intrinsic opts"),
154     cl::init(true));
155 
156 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
157                                          cl::init(true), cl::Hidden);
158 
159 static cl::opt<bool>
160     EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
161                         cl::desc("Enable the AAcrh64 branch target pass"),
162                         cl::init(true));
163 
164 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
165   // Register the target.
166   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
167   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
168   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
169   RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
170   RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
171   auto PR = PassRegistry::getPassRegistry();
172   initializeGlobalISel(*PR);
173   initializeAArch64A53Fix835769Pass(*PR);
174   initializeAArch64A57FPLoadBalancingPass(*PR);
175   initializeAArch64AdvSIMDScalarPass(*PR);
176   initializeAArch64BranchTargetsPass(*PR);
177   initializeAArch64CollectLOHPass(*PR);
178   initializeAArch64CompressJumpTablesPass(*PR);
179   initializeAArch64ConditionalComparesPass(*PR);
180   initializeAArch64ConditionOptimizerPass(*PR);
181   initializeAArch64DeadRegisterDefinitionsPass(*PR);
182   initializeAArch64ExpandPseudoPass(*PR);
183   initializeAArch64LoadStoreOptPass(*PR);
184   initializeAArch64SIMDInstrOptPass(*PR);
185   initializeAArch64PreLegalizerCombinerPass(*PR);
186   initializeAArch64PostLegalizerCombinerPass(*PR);
187   initializeAArch64PromoteConstantPass(*PR);
188   initializeAArch64RedundantCopyEliminationPass(*PR);
189   initializeAArch64StorePairSuppressPass(*PR);
190   initializeFalkorHWPFFixPass(*PR);
191   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
192   initializeLDTLSCleanupPass(*PR);
193   initializeSVEIntrinsicOptsPass(*PR);
194   initializeAArch64SpeculationHardeningPass(*PR);
195   initializeAArch64StackTaggingPass(*PR);
196   initializeAArch64StackTaggingPreRAPass(*PR);
197 }
198 
199 //===----------------------------------------------------------------------===//
200 // AArch64 Lowering public interface.
201 //===----------------------------------------------------------------------===//
202 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
203   if (TT.isOSBinFormatMachO())
204     return std::make_unique<AArch64_MachoTargetObjectFile>();
205   if (TT.isOSBinFormatCOFF())
206     return std::make_unique<AArch64_COFFTargetObjectFile>();
207 
208   return std::make_unique<AArch64_ELFTargetObjectFile>();
209 }
210 
211 // Helper function to build a DataLayout string
212 static std::string computeDataLayout(const Triple &TT,
213                                      const MCTargetOptions &Options,
214                                      bool LittleEndian) {
215   if (Options.getABIName() == "ilp32")
216     return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
217   if (TT.isOSBinFormatMachO()) {
218     if (TT.getArch() == Triple::aarch64_32)
219       return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
220     return "e-m:o-i64:64-i128:128-n32:64-S128";
221   }
222   if (TT.isOSBinFormatCOFF())
223     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
224   if (LittleEndian)
225     return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
226   return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
227 }
228 
229 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
230                                            Optional<Reloc::Model> RM) {
231   // AArch64 Darwin and Windows are always PIC.
232   if (TT.isOSDarwin() || TT.isOSWindows())
233     return Reloc::PIC_;
234   // On ELF platforms the default static relocation model has a smart enough
235   // linker to cope with referencing external symbols defined in a shared
236   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
237   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
238     return Reloc::Static;
239   return *RM;
240 }
241 
242 static CodeModel::Model
243 getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
244                              bool JIT) {
245   if (CM) {
246     if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
247         *CM != CodeModel::Large) {
248       report_fatal_error(
249           "Only small, tiny and large code models are allowed on AArch64");
250     } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
251       report_fatal_error("tiny code model is only supported on ELF");
252     return *CM;
253   }
254   // The default MCJIT memory managers make no guarantees about where they can
255   // find an executable page; JITed code needs to be able to refer to globals
256   // no matter how far away they are.
257   // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
258   // since with large code model LLVM generating 4 MOV instructions, and
259   // Windows doesn't support relocating these long branch (4 MOVs).
260   if (JIT && !TT.isOSWindows())
261     return CodeModel::Large;
262   return CodeModel::Small;
263 }
264 
265 /// Create an AArch64 architecture model.
266 ///
267 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
268                                            StringRef CPU, StringRef FS,
269                                            const TargetOptions &Options,
270                                            Optional<Reloc::Model> RM,
271                                            Optional<CodeModel::Model> CM,
272                                            CodeGenOpt::Level OL, bool JIT,
273                                            bool LittleEndian)
274     : LLVMTargetMachine(T,
275                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
276                         TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
277                         getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
278       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
279   initAsmInfo();
280 
281   if (TT.isOSBinFormatMachO()) {
282     this->Options.TrapUnreachable = true;
283     this->Options.NoTrapAfterNoreturn = true;
284   }
285 
286   if (getMCAsmInfo()->usesWindowsCFI()) {
287     // Unwinding can get confused if the last instruction in an
288     // exception-handling region (function, funclet, try block, etc.)
289     // is a call.
290     //
291     // FIXME: We could elide the trap if the next instruction would be in
292     // the same region anyway.
293     this->Options.TrapUnreachable = true;
294   }
295 
296   if (this->Options.TLSSize == 0) // default
297     this->Options.TLSSize = 24;
298   if ((getCodeModel() == CodeModel::Small ||
299        getCodeModel() == CodeModel::Kernel) &&
300       this->Options.TLSSize > 32)
301     // for the small (and kernel) code model, the maximum TLS size is 4GiB
302     this->Options.TLSSize = 32;
303   else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
304     // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
305     this->Options.TLSSize = 24;
306 
307   // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
308   // MachO/CodeModel::Large, which GlobalISel does not support.
309   if (getOptLevel() <= EnableGlobalISelAtO &&
310       TT.getArch() != Triple::aarch64_32 &&
311       !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
312     setGlobalISel(true);
313     setGlobalISelAbort(GlobalISelAbortMode::Disable);
314   }
315 
316   // AArch64 supports the MachineOutliner.
317   setMachineOutliner(true);
318 
319   // AArch64 supports default outlining behaviour.
320   setSupportsDefaultOutlining(true);
321 
322   // AArch64 supports the debug entry values.
323   setSupportsDebugEntryValues(true);
324 }
325 
326 AArch64TargetMachine::~AArch64TargetMachine() = default;
327 
328 const AArch64Subtarget *
329 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
330   Attribute CPUAttr = F.getFnAttribute("target-cpu");
331   Attribute FSAttr = F.getFnAttribute("target-features");
332 
333   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
334                         ? CPUAttr.getValueAsString().str()
335                         : TargetCPU;
336   std::string FS = !FSAttr.hasAttribute(Attribute::None)
337                        ? FSAttr.getValueAsString().str()
338                        : TargetFS;
339 
340   auto &I = SubtargetMap[CPU + FS];
341   if (!I) {
342     // This needs to be done before we create a new subtarget since any
343     // creation will depend on the TM and the code generation flags on the
344     // function that reside in TargetOptions.
345     resetTargetOptions(F);
346     I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
347                                             isLittle);
348   }
349   return I.get();
350 }
351 
352 void AArch64leTargetMachine::anchor() { }
353 
354 AArch64leTargetMachine::AArch64leTargetMachine(
355     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
356     const TargetOptions &Options, Optional<Reloc::Model> RM,
357     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
358     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
359 
360 void AArch64beTargetMachine::anchor() { }
361 
362 AArch64beTargetMachine::AArch64beTargetMachine(
363     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
364     const TargetOptions &Options, Optional<Reloc::Model> RM,
365     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
366     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
367 
368 namespace {
369 
370 /// AArch64 Code Generator Pass Configuration Options.
371 class AArch64PassConfig : public TargetPassConfig {
372 public:
373   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
374       : TargetPassConfig(TM, PM) {
375     if (TM.getOptLevel() != CodeGenOpt::None)
376       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
377   }
378 
379   AArch64TargetMachine &getAArch64TargetMachine() const {
380     return getTM<AArch64TargetMachine>();
381   }
382 
383   ScheduleDAGInstrs *
384   createMachineScheduler(MachineSchedContext *C) const override {
385     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
386     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
387     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
388     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
389     if (ST.hasFusion())
390       DAG->addMutation(createAArch64MacroFusionDAGMutation());
391     return DAG;
392   }
393 
394   ScheduleDAGInstrs *
395   createPostMachineScheduler(MachineSchedContext *C) const override {
396     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
397     if (ST.hasFusion()) {
398       // Run the Macro Fusion after RA again since literals are expanded from
399       // pseudos then (v. addPreSched2()).
400       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
401       DAG->addMutation(createAArch64MacroFusionDAGMutation());
402       return DAG;
403     }
404 
405     return nullptr;
406   }
407 
408   void addIRPasses()  override;
409   bool addPreISel() override;
410   bool addInstSelector() override;
411   bool addIRTranslator() override;
412   void addPreLegalizeMachineIR() override;
413   bool addLegalizeMachineIR() override;
414   void addPreRegBankSelect() override;
415   bool addRegBankSelect() override;
416   void addPreGlobalInstructionSelect() override;
417   bool addGlobalInstructionSelect() override;
418   bool addILPOpts() override;
419   void addPreRegAlloc() override;
420   void addPostRegAlloc() override;
421   void addPreSched2() override;
422   void addPreEmitPass() override;
423 
424   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
425 };
426 
427 } // end anonymous namespace
428 
429 TargetTransformInfo
430 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
431   return TargetTransformInfo(AArch64TTIImpl(this, F));
432 }
433 
434 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
435   return new AArch64PassConfig(*this, PM);
436 }
437 
438 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
439   return getStandardCSEConfigForOpt(TM->getOptLevel());
440 }
441 
442 void AArch64PassConfig::addIRPasses() {
443   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
444   // ourselves.
445   addPass(createAtomicExpandPass());
446 
447   // Expand any SVE vector library calls that we can't code generate directly.
448   if (EnableSVEIntrinsicOpts && TM->getOptLevel() == CodeGenOpt::Aggressive)
449     addPass(createSVEIntrinsicOptsPass());
450 
451   // Cmpxchg instructions are often used with a subsequent comparison to
452   // determine whether it succeeded. We can exploit existing control-flow in
453   // ldrex/strex loops to simplify this, but it needs tidying up.
454   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
455     addPass(createCFGSimplificationPass(1, true, true, false, true));
456 
457   // Run LoopDataPrefetch
458   //
459   // Run this before LSR to remove the multiplies involved in computing the
460   // pointer values N iterations ahead.
461   if (TM->getOptLevel() != CodeGenOpt::None) {
462     if (EnableLoopDataPrefetch)
463       addPass(createLoopDataPrefetchPass());
464     if (EnableFalkorHWPFFix)
465       addPass(createFalkorMarkStridedAccessesPass());
466   }
467 
468   TargetPassConfig::addIRPasses();
469 
470   addPass(createAArch64StackTaggingPass(
471       /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
472 
473   // Match interleaved memory accesses to ldN/stN intrinsics.
474   if (TM->getOptLevel() != CodeGenOpt::None) {
475     addPass(createInterleavedLoadCombinePass());
476     addPass(createInterleavedAccessPass());
477   }
478 
479   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
480     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
481     // and lower a GEP with multiple indices to either arithmetic operations or
482     // multiple GEPs with single index.
483     addPass(createSeparateConstOffsetFromGEPPass(true));
484     // Call EarlyCSE pass to find and remove subexpressions in the lowered
485     // result.
486     addPass(createEarlyCSEPass());
487     // Do loop invariant code motion in case part of the lowered result is
488     // invariant.
489     addPass(createLICMPass());
490   }
491 
492   // Add Control Flow Guard checks.
493   if (TM->getTargetTriple().isOSWindows())
494     addPass(createCFGuardCheckPass());
495 }
496 
497 // Pass Pipeline Configuration
498 bool AArch64PassConfig::addPreISel() {
499   // Run promote constant before global merge, so that the promoted constants
500   // get a chance to be merged
501   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
502     addPass(createAArch64PromoteConstantPass());
503   // FIXME: On AArch64, this depends on the type.
504   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
505   // and the offset has to be a multiple of the related size in bytes.
506   if ((TM->getOptLevel() != CodeGenOpt::None &&
507        EnableGlobalMerge == cl::BOU_UNSET) ||
508       EnableGlobalMerge == cl::BOU_TRUE) {
509     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
510                                (EnableGlobalMerge == cl::BOU_UNSET);
511 
512     // Merging of extern globals is enabled by default on non-Mach-O as we
513     // expect it to be generally either beneficial or harmless. On Mach-O it
514     // is disabled as we emit the .subsections_via_symbols directive which
515     // means that merging extern globals is not safe.
516     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
517 
518     // FIXME: extern global merging is only enabled when we optimise for size
519     // because there are some regressions with it also enabled for performance.
520     if (!OnlyOptimizeForSize)
521       MergeExternalByDefault = false;
522 
523     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
524                                   MergeExternalByDefault));
525   }
526 
527   return false;
528 }
529 
530 bool AArch64PassConfig::addInstSelector() {
531   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
532 
533   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
534   // references to _TLS_MODULE_BASE_ as possible.
535   if (TM->getTargetTriple().isOSBinFormatELF() &&
536       getOptLevel() != CodeGenOpt::None)
537     addPass(createAArch64CleanupLocalDynamicTLSPass());
538 
539   return false;
540 }
541 
542 bool AArch64PassConfig::addIRTranslator() {
543   addPass(new IRTranslator());
544   return false;
545 }
546 
547 void AArch64PassConfig::addPreLegalizeMachineIR() {
548   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
549   addPass(createAArch64PreLegalizeCombiner(IsOptNone));
550 }
551 
552 bool AArch64PassConfig::addLegalizeMachineIR() {
553   addPass(new Legalizer());
554   return false;
555 }
556 
557 void AArch64PassConfig::addPreRegBankSelect() {
558   // For now we don't add this to the pipeline for -O0. We could do in future
559   // if we split the combines into separate O0/opt groupings.
560   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
561   if (!IsOptNone)
562     addPass(createAArch64PostLegalizeCombiner(IsOptNone));
563 }
564 
565 bool AArch64PassConfig::addRegBankSelect() {
566   addPass(new RegBankSelect());
567   return false;
568 }
569 
570 void AArch64PassConfig::addPreGlobalInstructionSelect() {
571   addPass(new Localizer());
572 }
573 
574 bool AArch64PassConfig::addGlobalInstructionSelect() {
575   addPass(new InstructionSelect());
576   return false;
577 }
578 
579 bool AArch64PassConfig::addILPOpts() {
580   if (EnableCondOpt)
581     addPass(createAArch64ConditionOptimizerPass());
582   if (EnableCCMP)
583     addPass(createAArch64ConditionalCompares());
584   if (EnableMCR)
585     addPass(&MachineCombinerID);
586   if (EnableCondBrTuning)
587     addPass(createAArch64CondBrTuning());
588   if (EnableEarlyIfConversion)
589     addPass(&EarlyIfConverterID);
590   if (EnableStPairSuppress)
591     addPass(createAArch64StorePairSuppressPass());
592   addPass(createAArch64SIMDInstrOptPass());
593   if (TM->getOptLevel() != CodeGenOpt::None)
594     addPass(createAArch64StackTaggingPreRAPass());
595   return true;
596 }
597 
598 void AArch64PassConfig::addPreRegAlloc() {
599   // Change dead register definitions to refer to the zero register.
600   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
601     addPass(createAArch64DeadRegisterDefinitions());
602 
603   // Use AdvSIMD scalar instructions whenever profitable.
604   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
605     addPass(createAArch64AdvSIMDScalar());
606     // The AdvSIMD pass may produce copies that can be rewritten to
607     // be register coalescer friendly.
608     addPass(&PeepholeOptimizerID);
609   }
610 }
611 
612 void AArch64PassConfig::addPostRegAlloc() {
613   // Remove redundant copy instructions.
614   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
615     addPass(createAArch64RedundantCopyEliminationPass());
616 
617   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
618     // Improve performance for some FP/SIMD code for A57.
619     addPass(createAArch64A57FPLoadBalancing());
620 }
621 
622 void AArch64PassConfig::addPreSched2() {
623   // Expand some pseudo instructions to allow proper scheduling.
624   addPass(createAArch64ExpandPseudoPass());
625   // Use load/store pair instructions when possible.
626   if (TM->getOptLevel() != CodeGenOpt::None) {
627     if (EnableLoadStoreOpt)
628       addPass(createAArch64LoadStoreOptimizationPass());
629   }
630 
631   // The AArch64SpeculationHardeningPass destroys dominator tree and natural
632   // loop info, which is needed for the FalkorHWPFFixPass and also later on.
633   // Therefore, run the AArch64SpeculationHardeningPass before the
634   // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
635   // info.
636   addPass(createAArch64SpeculationHardeningPass());
637 
638   if (TM->getOptLevel() != CodeGenOpt::None) {
639     if (EnableFalkorHWPFFix)
640       addPass(createFalkorHWPFFixPass());
641   }
642 }
643 
644 void AArch64PassConfig::addPreEmitPass() {
645   // Machine Block Placement might have created new opportunities when run
646   // at O3, where the Tail Duplication Threshold is set to 4 instructions.
647   // Run the load/store optimizer once more.
648   if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
649     addPass(createAArch64LoadStoreOptimizationPass());
650 
651   if (EnableA53Fix835769)
652     addPass(createAArch64A53Fix835769());
653 
654   if (EnableBranchTargets)
655     addPass(createAArch64BranchTargetsPass());
656 
657   // Relax conditional branch instructions if they're otherwise out of
658   // range of their destination.
659   if (BranchRelaxation)
660     addPass(&BranchRelaxationPassID);
661 
662   // Identify valid longjmp targets for Windows Control Flow Guard.
663   if (TM->getTargetTriple().isOSWindows())
664     addPass(createCFGuardLongjmpPass());
665 
666   if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
667     addPass(createAArch64CompressJumpTablesPass());
668 
669   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
670       TM->getTargetTriple().isOSBinFormatMachO())
671     addPass(createAArch64CollectLOHPass());
672 
673   // SVE bundles move prefixes with destructive operations.
674   addPass(createUnpackMachineBundles(nullptr));
675 }
676 
677 yaml::MachineFunctionInfo *
678 AArch64TargetMachine::createDefaultFuncInfoYAML() const {
679   return new yaml::AArch64FunctionInfo();
680 }
681 
682 yaml::MachineFunctionInfo *
683 AArch64TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
684   const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
685   return new yaml::AArch64FunctionInfo(*MFI);
686 }
687 
688 bool AArch64TargetMachine::parseMachineFunctionInfo(
689     const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
690     SMDiagnostic &Error, SMRange &SourceRange) const {
691   const auto &YamlMFI =
692       reinterpret_cast<const yaml::AArch64FunctionInfo &>(MFI);
693   MachineFunction &MF = PFS.MF;
694   MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
695   return false;
696 }
697