1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
14 #include "AArch64MacroFusion.h"
15 #include "AArch64Subtarget.h"
16 #include "AArch64TargetObjectFile.h"
17 #include "AArch64TargetTransformInfo.h"
18 #include "MCTargetDesc/AArch64MCTargetDesc.h"
19 #include "TargetInfo/AArch64TargetInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/CSEConfigBase.h"
24 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
25 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
26 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
27 #include "llvm/CodeGen/GlobalISel/Localizer.h"
28 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
29 #include "llvm/CodeGen/MachineScheduler.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/CodeGen/TargetPassConfig.h"
32 #include "llvm/IR/Attributes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCTargetOptions.h"
36 #include "llvm/Pass.h"
37 #include "llvm/Support/CodeGen.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/TargetRegistry.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Transforms/Scalar.h"
43 #include <memory>
44 #include <string>
45 
46 using namespace llvm;
47 
48 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
49                                 cl::desc("Enable the CCMP formation pass"),
50                                 cl::init(true), cl::Hidden);
51 
52 static cl::opt<bool>
53     EnableCondBrTuning("aarch64-enable-cond-br-tune",
54                        cl::desc("Enable the conditional branch tuning pass"),
55                        cl::init(true), cl::Hidden);
56 
57 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
58                                cl::desc("Enable the machine combiner pass"),
59                                cl::init(true), cl::Hidden);
60 
61 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
62                                           cl::desc("Suppress STP for AArch64"),
63                                           cl::init(true), cl::Hidden);
64 
65 static cl::opt<bool> EnableAdvSIMDScalar(
66     "aarch64-enable-simd-scalar",
67     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
68     cl::init(false), cl::Hidden);
69 
70 static cl::opt<bool>
71     EnablePromoteConstant("aarch64-enable-promote-const",
72                           cl::desc("Enable the promote constant pass"),
73                           cl::init(true), cl::Hidden);
74 
75 static cl::opt<bool> EnableCollectLOH(
76     "aarch64-enable-collect-loh",
77     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
78     cl::init(true), cl::Hidden);
79 
80 static cl::opt<bool>
81     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
82                                   cl::desc("Enable the pass that removes dead"
83                                            " definitons and replaces stores to"
84                                            " them with stores to the zero"
85                                            " register"),
86                                   cl::init(true));
87 
88 static cl::opt<bool> EnableRedundantCopyElimination(
89     "aarch64-enable-copyelim",
90     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
91     cl::Hidden);
92 
93 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
94                                         cl::desc("Enable the load/store pair"
95                                                  " optimization pass"),
96                                         cl::init(true), cl::Hidden);
97 
98 static cl::opt<bool> EnableAtomicTidy(
99     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
100     cl::desc("Run SimplifyCFG after expanding atomic operations"
101              " to make use of cmpxchg flow-based information"),
102     cl::init(true));
103 
104 static cl::opt<bool>
105 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
106                         cl::desc("Run early if-conversion"),
107                         cl::init(true));
108 
109 static cl::opt<bool>
110     EnableCondOpt("aarch64-enable-condopt",
111                   cl::desc("Enable the condition optimizer pass"),
112                   cl::init(true), cl::Hidden);
113 
114 static cl::opt<bool>
115 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
116                 cl::desc("Work around Cortex-A53 erratum 835769"),
117                 cl::init(false));
118 
119 static cl::opt<bool>
120     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
121                  cl::desc("Enable optimizations on complex GEPs"),
122                  cl::init(false));
123 
124 static cl::opt<bool>
125     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
126                      cl::desc("Relax out of range conditional branches"));
127 
128 static cl::opt<bool> EnableCompressJumpTables(
129     "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
130     cl::desc("Use smallest entry possible for jump tables"));
131 
132 // FIXME: Unify control over GlobalMerge.
133 static cl::opt<cl::boolOrDefault>
134     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
135                       cl::desc("Enable the global merge pass"));
136 
137 static cl::opt<bool>
138     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
139                            cl::desc("Enable the loop data prefetch pass"),
140                            cl::init(true));
141 
142 static cl::opt<int> EnableGlobalISelAtO(
143     "aarch64-enable-global-isel-at-O", cl::Hidden,
144     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
145     cl::init(0));
146 
147 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
148                                          cl::init(true), cl::Hidden);
149 
150 static cl::opt<bool>
151     EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
152                         cl::desc("Enable the AAcrh64 branch target pass"),
153                         cl::init(true));
154 
155 extern "C" void LLVMInitializeAArch64Target() {
156   // Register the target.
157   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
158   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
159   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
160   auto PR = PassRegistry::getPassRegistry();
161   initializeGlobalISel(*PR);
162   initializeAArch64A53Fix835769Pass(*PR);
163   initializeAArch64A57FPLoadBalancingPass(*PR);
164   initializeAArch64AdvSIMDScalarPass(*PR);
165   initializeAArch64BranchTargetsPass(*PR);
166   initializeAArch64CollectLOHPass(*PR);
167   initializeAArch64CompressJumpTablesPass(*PR);
168   initializeAArch64ConditionalComparesPass(*PR);
169   initializeAArch64ConditionOptimizerPass(*PR);
170   initializeAArch64DeadRegisterDefinitionsPass(*PR);
171   initializeAArch64ExpandPseudoPass(*PR);
172   initializeAArch64LoadStoreOptPass(*PR);
173   initializeAArch64SIMDInstrOptPass(*PR);
174   initializeAArch64PreLegalizerCombinerPass(*PR);
175   initializeAArch64PromoteConstantPass(*PR);
176   initializeAArch64RedundantCopyEliminationPass(*PR);
177   initializeAArch64StorePairSuppressPass(*PR);
178   initializeFalkorHWPFFixPass(*PR);
179   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
180   initializeLDTLSCleanupPass(*PR);
181   initializeAArch64SpeculationHardeningPass(*PR);
182 }
183 
184 //===----------------------------------------------------------------------===//
185 // AArch64 Lowering public interface.
186 //===----------------------------------------------------------------------===//
187 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
188   if (TT.isOSBinFormatMachO())
189     return llvm::make_unique<AArch64_MachoTargetObjectFile>();
190   if (TT.isOSBinFormatCOFF())
191     return llvm::make_unique<AArch64_COFFTargetObjectFile>();
192 
193   return llvm::make_unique<AArch64_ELFTargetObjectFile>();
194 }
195 
196 // Helper function to build a DataLayout string
197 static std::string computeDataLayout(const Triple &TT,
198                                      const MCTargetOptions &Options,
199                                      bool LittleEndian) {
200   if (Options.getABIName() == "ilp32")
201     return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
202   if (TT.isOSBinFormatMachO())
203     return "e-m:o-i64:64-i128:128-n32:64-S128";
204   if (TT.isOSBinFormatCOFF())
205     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
206   if (LittleEndian)
207     return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
208   return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
209 }
210 
211 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
212                                            Optional<Reloc::Model> RM) {
213   // AArch64 Darwin and Windows are always PIC.
214   if (TT.isOSDarwin() || TT.isOSWindows())
215     return Reloc::PIC_;
216   // On ELF platforms the default static relocation model has a smart enough
217   // linker to cope with referencing external symbols defined in a shared
218   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
219   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
220     return Reloc::Static;
221   return *RM;
222 }
223 
224 static CodeModel::Model
225 getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
226                              bool JIT) {
227   if (CM) {
228     if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
229         *CM != CodeModel::Large) {
230       if (!TT.isOSFuchsia())
231         report_fatal_error(
232             "Only small, tiny and large code models are allowed on AArch64");
233       else if (*CM != CodeModel::Kernel)
234         report_fatal_error("Only small, tiny, kernel, and large code models "
235                            "are allowed on AArch64");
236     } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
237       report_fatal_error("tiny code model is only supported on ELF");
238     return *CM;
239   }
240   // The default MCJIT memory managers make no guarantees about where they can
241   // find an executable page; JITed code needs to be able to refer to globals
242   // no matter how far away they are.
243   if (JIT)
244     return CodeModel::Large;
245   return CodeModel::Small;
246 }
247 
248 /// Create an AArch64 architecture model.
249 ///
250 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
251                                            StringRef CPU, StringRef FS,
252                                            const TargetOptions &Options,
253                                            Optional<Reloc::Model> RM,
254                                            Optional<CodeModel::Model> CM,
255                                            CodeGenOpt::Level OL, bool JIT,
256                                            bool LittleEndian)
257     : LLVMTargetMachine(T,
258                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
259                         TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
260                         getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
261       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
262   initAsmInfo();
263 
264   if (TT.isOSBinFormatMachO()) {
265     this->Options.TrapUnreachable = true;
266     this->Options.NoTrapAfterNoreturn = true;
267   }
268 
269   if (getMCAsmInfo()->usesWindowsCFI()) {
270     // Unwinding can get confused if the last instruction in an
271     // exception-handling region (function, funclet, try block, etc.)
272     // is a call.
273     //
274     // FIXME: We could elide the trap if the next instruction would be in
275     // the same region anyway.
276     this->Options.TrapUnreachable = true;
277   }
278 
279   // Enable GlobalISel at or below EnableGlobalISelAt0.
280   if (getOptLevel() <= EnableGlobalISelAtO) {
281     setGlobalISel(true);
282     setGlobalISelAbort(GlobalISelAbortMode::Disable);
283   }
284 
285   // AArch64 supports the MachineOutliner.
286   setMachineOutliner(true);
287 
288   // AArch64 supports default outlining behaviour.
289   setSupportsDefaultOutlining(true);
290 }
291 
292 AArch64TargetMachine::~AArch64TargetMachine() = default;
293 
294 const AArch64Subtarget *
295 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
296   Attribute CPUAttr = F.getFnAttribute("target-cpu");
297   Attribute FSAttr = F.getFnAttribute("target-features");
298 
299   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
300                         ? CPUAttr.getValueAsString().str()
301                         : TargetCPU;
302   std::string FS = !FSAttr.hasAttribute(Attribute::None)
303                        ? FSAttr.getValueAsString().str()
304                        : TargetFS;
305 
306   auto &I = SubtargetMap[CPU + FS];
307   if (!I) {
308     // This needs to be done before we create a new subtarget since any
309     // creation will depend on the TM and the code generation flags on the
310     // function that reside in TargetOptions.
311     resetTargetOptions(F);
312     I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
313                                             isLittle);
314   }
315   return I.get();
316 }
317 
318 void AArch64leTargetMachine::anchor() { }
319 
320 AArch64leTargetMachine::AArch64leTargetMachine(
321     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
322     const TargetOptions &Options, Optional<Reloc::Model> RM,
323     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
324     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
325 
326 void AArch64beTargetMachine::anchor() { }
327 
328 AArch64beTargetMachine::AArch64beTargetMachine(
329     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
330     const TargetOptions &Options, Optional<Reloc::Model> RM,
331     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
332     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
333 
334 namespace {
335 
336 /// AArch64 Code Generator Pass Configuration Options.
337 class AArch64PassConfig : public TargetPassConfig {
338 public:
339   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
340       : TargetPassConfig(TM, PM) {
341     if (TM.getOptLevel() != CodeGenOpt::None)
342       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
343   }
344 
345   AArch64TargetMachine &getAArch64TargetMachine() const {
346     return getTM<AArch64TargetMachine>();
347   }
348 
349   ScheduleDAGInstrs *
350   createMachineScheduler(MachineSchedContext *C) const override {
351     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
352     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
353     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
354     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
355     if (ST.hasFusion())
356       DAG->addMutation(createAArch64MacroFusionDAGMutation());
357     return DAG;
358   }
359 
360   ScheduleDAGInstrs *
361   createPostMachineScheduler(MachineSchedContext *C) const override {
362     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
363     if (ST.hasFusion()) {
364       // Run the Macro Fusion after RA again since literals are expanded from
365       // pseudos then (v. addPreSched2()).
366       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
367       DAG->addMutation(createAArch64MacroFusionDAGMutation());
368       return DAG;
369     }
370 
371     return nullptr;
372   }
373 
374   void addIRPasses()  override;
375   bool addPreISel() override;
376   bool addInstSelector() override;
377   bool addIRTranslator() override;
378   void addPreLegalizeMachineIR() override;
379   bool addLegalizeMachineIR() override;
380   bool addRegBankSelect() override;
381   void addPreGlobalInstructionSelect() override;
382   bool addGlobalInstructionSelect() override;
383   bool addILPOpts() override;
384   void addPreRegAlloc() override;
385   void addPostRegAlloc() override;
386   void addPreSched2() override;
387   void addPreEmitPass() override;
388 
389   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
390 };
391 
392 } // end anonymous namespace
393 
394 TargetTransformInfo
395 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
396   return TargetTransformInfo(AArch64TTIImpl(this, F));
397 }
398 
399 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
400   return new AArch64PassConfig(*this, PM);
401 }
402 
403 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
404   return getStandardCSEConfigForOpt(TM->getOptLevel());
405 }
406 
407 void AArch64PassConfig::addIRPasses() {
408   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
409   // ourselves.
410   addPass(createAtomicExpandPass());
411 
412   // Cmpxchg instructions are often used with a subsequent comparison to
413   // determine whether it succeeded. We can exploit existing control-flow in
414   // ldrex/strex loops to simplify this, but it needs tidying up.
415   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
416     addPass(createCFGSimplificationPass(1, true, true, false, true));
417 
418   // Run LoopDataPrefetch
419   //
420   // Run this before LSR to remove the multiplies involved in computing the
421   // pointer values N iterations ahead.
422   if (TM->getOptLevel() != CodeGenOpt::None) {
423     if (EnableLoopDataPrefetch)
424       addPass(createLoopDataPrefetchPass());
425     if (EnableFalkorHWPFFix)
426       addPass(createFalkorMarkStridedAccessesPass());
427   }
428 
429   TargetPassConfig::addIRPasses();
430 
431   // Match interleaved memory accesses to ldN/stN intrinsics.
432   if (TM->getOptLevel() != CodeGenOpt::None) {
433     addPass(createInterleavedLoadCombinePass());
434     addPass(createInterleavedAccessPass());
435   }
436 
437   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
438     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
439     // and lower a GEP with multiple indices to either arithmetic operations or
440     // multiple GEPs with single index.
441     addPass(createSeparateConstOffsetFromGEPPass(true));
442     // Call EarlyCSE pass to find and remove subexpressions in the lowered
443     // result.
444     addPass(createEarlyCSEPass());
445     // Do loop invariant code motion in case part of the lowered result is
446     // invariant.
447     addPass(createLICMPass());
448   }
449 }
450 
451 // Pass Pipeline Configuration
452 bool AArch64PassConfig::addPreISel() {
453   // Run promote constant before global merge, so that the promoted constants
454   // get a chance to be merged
455   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
456     addPass(createAArch64PromoteConstantPass());
457   // FIXME: On AArch64, this depends on the type.
458   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
459   // and the offset has to be a multiple of the related size in bytes.
460   if ((TM->getOptLevel() != CodeGenOpt::None &&
461        EnableGlobalMerge == cl::BOU_UNSET) ||
462       EnableGlobalMerge == cl::BOU_TRUE) {
463     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
464                                (EnableGlobalMerge == cl::BOU_UNSET);
465     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
466   }
467 
468   return false;
469 }
470 
471 bool AArch64PassConfig::addInstSelector() {
472   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
473 
474   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
475   // references to _TLS_MODULE_BASE_ as possible.
476   if (TM->getTargetTriple().isOSBinFormatELF() &&
477       getOptLevel() != CodeGenOpt::None)
478     addPass(createAArch64CleanupLocalDynamicTLSPass());
479 
480   return false;
481 }
482 
483 bool AArch64PassConfig::addIRTranslator() {
484   addPass(new IRTranslator());
485   return false;
486 }
487 
488 void AArch64PassConfig::addPreLegalizeMachineIR() {
489   addPass(createAArch64PreLegalizeCombiner());
490 }
491 
492 bool AArch64PassConfig::addLegalizeMachineIR() {
493   addPass(new Legalizer());
494   return false;
495 }
496 
497 bool AArch64PassConfig::addRegBankSelect() {
498   addPass(new RegBankSelect());
499   return false;
500 }
501 
502 void AArch64PassConfig::addPreGlobalInstructionSelect() {
503   // Workaround the deficiency of the fast register allocator.
504   if (TM->getOptLevel() == CodeGenOpt::None)
505     addPass(new Localizer());
506 }
507 
508 bool AArch64PassConfig::addGlobalInstructionSelect() {
509   addPass(new InstructionSelect());
510   return false;
511 }
512 
513 bool AArch64PassConfig::addILPOpts() {
514   if (EnableCondOpt)
515     addPass(createAArch64ConditionOptimizerPass());
516   if (EnableCCMP)
517     addPass(createAArch64ConditionalCompares());
518   if (EnableMCR)
519     addPass(&MachineCombinerID);
520   if (EnableCondBrTuning)
521     addPass(createAArch64CondBrTuning());
522   if (EnableEarlyIfConversion)
523     addPass(&EarlyIfConverterID);
524   if (EnableStPairSuppress)
525     addPass(createAArch64StorePairSuppressPass());
526   addPass(createAArch64SIMDInstrOptPass());
527   return true;
528 }
529 
530 void AArch64PassConfig::addPreRegAlloc() {
531   // Change dead register definitions to refer to the zero register.
532   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
533     addPass(createAArch64DeadRegisterDefinitions());
534 
535   // Use AdvSIMD scalar instructions whenever profitable.
536   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
537     addPass(createAArch64AdvSIMDScalar());
538     // The AdvSIMD pass may produce copies that can be rewritten to
539     // be register coaleascer friendly.
540     addPass(&PeepholeOptimizerID);
541   }
542 }
543 
544 void AArch64PassConfig::addPostRegAlloc() {
545   // Remove redundant copy instructions.
546   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
547     addPass(createAArch64RedundantCopyEliminationPass());
548 
549   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
550     // Improve performance for some FP/SIMD code for A57.
551     addPass(createAArch64A57FPLoadBalancing());
552 }
553 
554 void AArch64PassConfig::addPreSched2() {
555   // Expand some pseudo instructions to allow proper scheduling.
556   addPass(createAArch64ExpandPseudoPass());
557   // Use load/store pair instructions when possible.
558   if (TM->getOptLevel() != CodeGenOpt::None) {
559     if (EnableLoadStoreOpt)
560       addPass(createAArch64LoadStoreOptimizationPass());
561   }
562 
563   // The AArch64SpeculationHardeningPass destroys dominator tree and natural
564   // loop info, which is needed for the FalkorHWPFFixPass and also later on.
565   // Therefore, run the AArch64SpeculationHardeningPass before the
566   // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
567   // info.
568   addPass(createAArch64SpeculationHardeningPass());
569 
570   if (TM->getOptLevel() != CodeGenOpt::None) {
571     if (EnableFalkorHWPFFix)
572       addPass(createFalkorHWPFFixPass());
573   }
574 }
575 
576 void AArch64PassConfig::addPreEmitPass() {
577   // Machine Block Placement might have created new opportunities when run
578   // at O3, where the Tail Duplication Threshold is set to 4 instructions.
579   // Run the load/store optimizer once more.
580   if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
581     addPass(createAArch64LoadStoreOptimizationPass());
582 
583   if (EnableA53Fix835769)
584     addPass(createAArch64A53Fix835769());
585   // Relax conditional branch instructions if they're otherwise out of
586   // range of their destination.
587   if (BranchRelaxation)
588     addPass(&BranchRelaxationPassID);
589 
590   if (EnableBranchTargets)
591     addPass(createAArch64BranchTargetsPass());
592 
593   if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
594     addPass(createAArch64CompressJumpTablesPass());
595 
596   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
597       TM->getTargetTriple().isOSBinFormatMachO())
598     addPass(createAArch64CollectLOHPass());
599 }
600