1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64TargetMachine.h"
14 #include "AArch64.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetObjectFile.h"
18 #include "AArch64TargetTransformInfo.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
25 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
26 #include "llvm/CodeGen/GlobalISel/Localizer.h"
27 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
28 #include "llvm/CodeGen/MachineScheduler.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/CodeGen/TargetLoweringObjectFile.h"
31 #include "llvm/CodeGen/TargetPassConfig.h"
32 #include "llvm/IR/Attributes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/MC/MCTargetOptions.h"
35 #include "llvm/Pass.h"
36 #include "llvm/Support/CodeGen.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/Transforms/Scalar.h"
41 #include <memory>
42 #include <string>
43 
44 using namespace llvm;
45 
46 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
47                                 cl::desc("Enable the CCMP formation pass"),
48                                 cl::init(true), cl::Hidden);
49 
50 static cl::opt<bool>
51     EnableCondBrTuning("aarch64-enable-cond-br-tune",
52                        cl::desc("Enable the conditional branch tuning pass"),
53                        cl::init(true), cl::Hidden);
54 
55 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
56                                cl::desc("Enable the machine combiner pass"),
57                                cl::init(true), cl::Hidden);
58 
59 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
60                                           cl::desc("Suppress STP for AArch64"),
61                                           cl::init(true), cl::Hidden);
62 
63 static cl::opt<bool> EnableAdvSIMDScalar(
64     "aarch64-enable-simd-scalar",
65     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
66     cl::init(false), cl::Hidden);
67 
68 static cl::opt<bool>
69     EnablePromoteConstant("aarch64-enable-promote-const",
70                           cl::desc("Enable the promote constant pass"),
71                           cl::init(true), cl::Hidden);
72 
73 static cl::opt<bool> EnableCollectLOH(
74     "aarch64-enable-collect-loh",
75     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
76     cl::init(true), cl::Hidden);
77 
78 static cl::opt<bool>
79     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
80                                   cl::desc("Enable the pass that removes dead"
81                                            " definitons and replaces stores to"
82                                            " them with stores to the zero"
83                                            " register"),
84                                   cl::init(true));
85 
86 static cl::opt<bool> EnableRedundantCopyElimination(
87     "aarch64-enable-copyelim",
88     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
89     cl::Hidden);
90 
91 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
92                                         cl::desc("Enable the load/store pair"
93                                                  " optimization pass"),
94                                         cl::init(true), cl::Hidden);
95 
96 static cl::opt<bool> EnableAtomicTidy(
97     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
98     cl::desc("Run SimplifyCFG after expanding atomic operations"
99              " to make use of cmpxchg flow-based information"),
100     cl::init(true));
101 
102 static cl::opt<bool>
103 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
104                         cl::desc("Run early if-conversion"),
105                         cl::init(true));
106 
107 static cl::opt<bool>
108     EnableCondOpt("aarch64-enable-condopt",
109                   cl::desc("Enable the condition optimizer pass"),
110                   cl::init(true), cl::Hidden);
111 
112 static cl::opt<bool>
113 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
114                 cl::desc("Work around Cortex-A53 erratum 835769"),
115                 cl::init(false));
116 
117 static cl::opt<bool>
118     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
119                  cl::desc("Enable optimizations on complex GEPs"),
120                  cl::init(false));
121 
122 static cl::opt<bool>
123     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
124                      cl::desc("Relax out of range conditional branches"));
125 
126 // FIXME: Unify control over GlobalMerge.
127 static cl::opt<cl::boolOrDefault>
128     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
129                       cl::desc("Enable the global merge pass"));
130 
131 static cl::opt<bool>
132     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
133                            cl::desc("Enable the loop data prefetch pass"),
134                            cl::init(true));
135 
136 static cl::opt<int> EnableGlobalISelAtO(
137     "aarch64-enable-global-isel-at-O", cl::Hidden,
138     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
139     cl::init(0));
140 
141 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
142                                          cl::init(true), cl::Hidden);
143 
144 extern "C" void LLVMInitializeAArch64Target() {
145   // Register the target.
146   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
147   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
148   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
149   auto PR = PassRegistry::getPassRegistry();
150   initializeGlobalISel(*PR);
151   initializeAArch64A53Fix835769Pass(*PR);
152   initializeAArch64A57FPLoadBalancingPass(*PR);
153   initializeAArch64AdvSIMDScalarPass(*PR);
154   initializeAArch64CollectLOHPass(*PR);
155   initializeAArch64ConditionalComparesPass(*PR);
156   initializeAArch64ConditionOptimizerPass(*PR);
157   initializeAArch64DeadRegisterDefinitionsPass(*PR);
158   initializeAArch64ExpandPseudoPass(*PR);
159   initializeAArch64LoadStoreOptPass(*PR);
160   initializeAArch64SIMDInstrOptPass(*PR);
161   initializeAArch64PromoteConstantPass(*PR);
162   initializeAArch64RedundantCopyEliminationPass(*PR);
163   initializeAArch64StorePairSuppressPass(*PR);
164   initializeFalkorHWPFFixPass(*PR);
165   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
166   initializeLDTLSCleanupPass(*PR);
167 }
168 
169 //===----------------------------------------------------------------------===//
170 // AArch64 Lowering public interface.
171 //===----------------------------------------------------------------------===//
172 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
173   if (TT.isOSBinFormatMachO())
174     return llvm::make_unique<AArch64_MachoTargetObjectFile>();
175   if (TT.isOSBinFormatCOFF())
176     return llvm::make_unique<AArch64_COFFTargetObjectFile>();
177 
178   return llvm::make_unique<AArch64_ELFTargetObjectFile>();
179 }
180 
181 // Helper function to build a DataLayout string
182 static std::string computeDataLayout(const Triple &TT,
183                                      const MCTargetOptions &Options,
184                                      bool LittleEndian) {
185   if (Options.getABIName() == "ilp32")
186     return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
187   if (TT.isOSBinFormatMachO())
188     return "e-m:o-i64:64-i128:128-n32:64-S128";
189   if (TT.isOSBinFormatCOFF())
190     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
191   if (LittleEndian)
192     return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
193   return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
194 }
195 
196 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
197                                            Optional<Reloc::Model> RM) {
198   // AArch64 Darwin is always PIC.
199   if (TT.isOSDarwin())
200     return Reloc::PIC_;
201   // On ELF platforms the default static relocation model has a smart enough
202   // linker to cope with referencing external symbols defined in a shared
203   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
204   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
205     return Reloc::Static;
206   return *RM;
207 }
208 
209 static CodeModel::Model getEffectiveCodeModel(const Triple &TT,
210                                               Optional<CodeModel::Model> CM,
211                                               bool JIT) {
212   if (CM) {
213     if (*CM != CodeModel::Small && *CM != CodeModel::Large) {
214       if (!TT.isOSFuchsia())
215         report_fatal_error(
216             "Only small and large code models are allowed on AArch64");
217       else if (CM != CodeModel::Kernel)
218         report_fatal_error(
219             "Only small, kernel, and large code models are allowed on AArch64");
220     }
221     return *CM;
222   }
223   // The default MCJIT memory managers make no guarantees about where they can
224   // find an executable page; JITed code needs to be able to refer to globals
225   // no matter how far away they are.
226   if (JIT)
227     return CodeModel::Large;
228   return CodeModel::Small;
229 }
230 
231 /// Create an AArch64 architecture model.
232 ///
233 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
234                                            StringRef CPU, StringRef FS,
235                                            const TargetOptions &Options,
236                                            Optional<Reloc::Model> RM,
237                                            Optional<CodeModel::Model> CM,
238                                            CodeGenOpt::Level OL, bool JIT,
239                                            bool LittleEndian)
240     : LLVMTargetMachine(T,
241                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
242                         TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
243                         getEffectiveCodeModel(TT, CM, JIT), OL),
244       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
245   initAsmInfo();
246 }
247 
248 AArch64TargetMachine::~AArch64TargetMachine() = default;
249 
250 const AArch64Subtarget *
251 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
252   Attribute CPUAttr = F.getFnAttribute("target-cpu");
253   Attribute FSAttr = F.getFnAttribute("target-features");
254 
255   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
256                         ? CPUAttr.getValueAsString().str()
257                         : TargetCPU;
258   std::string FS = !FSAttr.hasAttribute(Attribute::None)
259                        ? FSAttr.getValueAsString().str()
260                        : TargetFS;
261 
262   auto &I = SubtargetMap[CPU + FS];
263   if (!I) {
264     // This needs to be done before we create a new subtarget since any
265     // creation will depend on the TM and the code generation flags on the
266     // function that reside in TargetOptions.
267     resetTargetOptions(F);
268     I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
269                                             isLittle);
270   }
271   return I.get();
272 }
273 
274 void AArch64leTargetMachine::anchor() { }
275 
276 AArch64leTargetMachine::AArch64leTargetMachine(
277     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
278     const TargetOptions &Options, Optional<Reloc::Model> RM,
279     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
280     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
281 
282 void AArch64beTargetMachine::anchor() { }
283 
284 AArch64beTargetMachine::AArch64beTargetMachine(
285     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
286     const TargetOptions &Options, Optional<Reloc::Model> RM,
287     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
288     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
289 
290 namespace {
291 
292 /// AArch64 Code Generator Pass Configuration Options.
293 class AArch64PassConfig : public TargetPassConfig {
294 public:
295   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
296       : TargetPassConfig(TM, PM) {
297     if (TM.getOptLevel() != CodeGenOpt::None)
298       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
299   }
300 
301   AArch64TargetMachine &getAArch64TargetMachine() const {
302     return getTM<AArch64TargetMachine>();
303   }
304 
305   ScheduleDAGInstrs *
306   createMachineScheduler(MachineSchedContext *C) const override {
307     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
308     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
309     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
310     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
311     if (ST.hasFusion())
312       DAG->addMutation(createAArch64MacroFusionDAGMutation());
313     return DAG;
314   }
315 
316   ScheduleDAGInstrs *
317   createPostMachineScheduler(MachineSchedContext *C) const override {
318     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
319     if (ST.hasFusion()) {
320       // Run the Macro Fusion after RA again since literals are expanded from
321       // pseudos then (v. addPreSched2()).
322       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
323       DAG->addMutation(createAArch64MacroFusionDAGMutation());
324       return DAG;
325     }
326 
327     return nullptr;
328   }
329 
330   void addIRPasses()  override;
331   bool addPreISel() override;
332   bool addInstSelector() override;
333   bool addIRTranslator() override;
334   bool addLegalizeMachineIR() override;
335   bool addRegBankSelect() override;
336   void addPreGlobalInstructionSelect() override;
337   bool addGlobalInstructionSelect() override;
338   bool addILPOpts() override;
339   void addPreRegAlloc() override;
340   void addPostRegAlloc() override;
341   void addPreSched2() override;
342   void addPreEmitPass() override;
343 
344   bool isGlobalISelEnabled() const override;
345 };
346 
347 } // end anonymous namespace
348 
349 TargetTransformInfo
350 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
351   return TargetTransformInfo(AArch64TTIImpl(this, F));
352 }
353 
354 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
355   return new AArch64PassConfig(*this, PM);
356 }
357 
358 void AArch64PassConfig::addIRPasses() {
359   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
360   // ourselves.
361   addPass(createAtomicExpandPass());
362 
363   // Cmpxchg instructions are often used with a subsequent comparison to
364   // determine whether it succeeded. We can exploit existing control-flow in
365   // ldrex/strex loops to simplify this, but it needs tidying up.
366   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
367     addPass(createCFGSimplificationPass(1, true, true, false, true));
368 
369   // Run LoopDataPrefetch
370   //
371   // Run this before LSR to remove the multiplies involved in computing the
372   // pointer values N iterations ahead.
373   if (TM->getOptLevel() != CodeGenOpt::None) {
374     if (EnableLoopDataPrefetch)
375       addPass(createLoopDataPrefetchPass());
376     if (EnableFalkorHWPFFix)
377       addPass(createFalkorMarkStridedAccessesPass());
378   }
379 
380   TargetPassConfig::addIRPasses();
381 
382   // Match interleaved memory accesses to ldN/stN intrinsics.
383   if (TM->getOptLevel() != CodeGenOpt::None)
384     addPass(createInterleavedAccessPass());
385 
386   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
387     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
388     // and lower a GEP with multiple indices to either arithmetic operations or
389     // multiple GEPs with single index.
390     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
391     // Call EarlyCSE pass to find and remove subexpressions in the lowered
392     // result.
393     addPass(createEarlyCSEPass());
394     // Do loop invariant code motion in case part of the lowered result is
395     // invariant.
396     addPass(createLICMPass());
397   }
398 }
399 
400 // Pass Pipeline Configuration
401 bool AArch64PassConfig::addPreISel() {
402   // Run promote constant before global merge, so that the promoted constants
403   // get a chance to be merged
404   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
405     addPass(createAArch64PromoteConstantPass());
406   // FIXME: On AArch64, this depends on the type.
407   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
408   // and the offset has to be a multiple of the related size in bytes.
409   if ((TM->getOptLevel() != CodeGenOpt::None &&
410        EnableGlobalMerge == cl::BOU_UNSET) ||
411       EnableGlobalMerge == cl::BOU_TRUE) {
412     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
413                                (EnableGlobalMerge == cl::BOU_UNSET);
414     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
415   }
416 
417   return false;
418 }
419 
420 bool AArch64PassConfig::addInstSelector() {
421   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
422 
423   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
424   // references to _TLS_MODULE_BASE_ as possible.
425   if (TM->getTargetTriple().isOSBinFormatELF() &&
426       getOptLevel() != CodeGenOpt::None)
427     addPass(createAArch64CleanupLocalDynamicTLSPass());
428 
429   return false;
430 }
431 
432 bool AArch64PassConfig::addIRTranslator() {
433   addPass(new IRTranslator());
434   return false;
435 }
436 
437 bool AArch64PassConfig::addLegalizeMachineIR() {
438   addPass(new Legalizer());
439   return false;
440 }
441 
442 bool AArch64PassConfig::addRegBankSelect() {
443   addPass(new RegBankSelect());
444   return false;
445 }
446 
447 void AArch64PassConfig::addPreGlobalInstructionSelect() {
448   // Workaround the deficiency of the fast register allocator.
449   if (TM->getOptLevel() == CodeGenOpt::None)
450     addPass(new Localizer());
451 }
452 
453 bool AArch64PassConfig::addGlobalInstructionSelect() {
454   addPass(new InstructionSelect());
455   return false;
456 }
457 
458 bool AArch64PassConfig::isGlobalISelEnabled() const {
459   return TM->getOptLevel() <= EnableGlobalISelAtO;
460 }
461 
462 bool AArch64PassConfig::addILPOpts() {
463   if (EnableCondOpt)
464     addPass(createAArch64ConditionOptimizerPass());
465   if (EnableCCMP)
466     addPass(createAArch64ConditionalCompares());
467   if (EnableMCR)
468     addPass(&MachineCombinerID);
469   if (EnableCondBrTuning)
470     addPass(createAArch64CondBrTuning());
471   if (EnableEarlyIfConversion)
472     addPass(&EarlyIfConverterID);
473   if (EnableStPairSuppress)
474     addPass(createAArch64StorePairSuppressPass());
475   addPass(createAArch64SIMDInstrOptPass());
476   return true;
477 }
478 
479 void AArch64PassConfig::addPreRegAlloc() {
480   // Change dead register definitions to refer to the zero register.
481   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
482     addPass(createAArch64DeadRegisterDefinitions());
483 
484   // Use AdvSIMD scalar instructions whenever profitable.
485   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
486     addPass(createAArch64AdvSIMDScalar());
487     // The AdvSIMD pass may produce copies that can be rewritten to
488     // be register coaleascer friendly.
489     addPass(&PeepholeOptimizerID);
490   }
491 }
492 
493 void AArch64PassConfig::addPostRegAlloc() {
494   // Remove redundant copy instructions.
495   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
496     addPass(createAArch64RedundantCopyEliminationPass());
497 
498   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
499     // Improve performance for some FP/SIMD code for A57.
500     addPass(createAArch64A57FPLoadBalancing());
501 }
502 
503 void AArch64PassConfig::addPreSched2() {
504   // Expand some pseudo instructions to allow proper scheduling.
505   addPass(createAArch64ExpandPseudoPass());
506   // Use load/store pair instructions when possible.
507   if (TM->getOptLevel() != CodeGenOpt::None) {
508     if (EnableLoadStoreOpt)
509       addPass(createAArch64LoadStoreOptimizationPass());
510     if (EnableFalkorHWPFFix)
511       addPass(createFalkorHWPFFixPass());
512   }
513 }
514 
515 void AArch64PassConfig::addPreEmitPass() {
516   if (EnableA53Fix835769)
517     addPass(createAArch64A53Fix835769());
518   // Relax conditional branch instructions if they're otherwise out of
519   // range of their destination.
520   if (BranchRelaxation)
521     addPass(&BranchRelaxationPassID);
522 
523   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
524       TM->getTargetTriple().isOSBinFormatMachO())
525     addPass(createAArch64CollectLOHPass());
526 }
527