1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64TargetMachine.h"
14 #include "AArch64.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetObjectFile.h"
18 #include "AArch64TargetTransformInfo.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
25 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
26 #include "llvm/CodeGen/GlobalISel/Localizer.h"
27 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
28 #include "llvm/CodeGen/MachineScheduler.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/CodeGen/TargetPassConfig.h"
31 #include "llvm/IR/Attributes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/MC/MCTargetOptions.h"
34 #include "llvm/Pass.h"
35 #include "llvm/Support/CodeGen.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Target/TargetLoweringObjectFile.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/Transforms/Scalar.h"
41 #include <memory>
42 #include <string>
43 
44 using namespace llvm;
45 
46 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
47                                 cl::desc("Enable the CCMP formation pass"),
48                                 cl::init(true), cl::Hidden);
49 
50 static cl::opt<bool>
51     EnableCondBrTuning("aarch64-enable-cond-br-tune",
52                        cl::desc("Enable the conditional branch tuning pass"),
53                        cl::init(true), cl::Hidden);
54 
55 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
56                                cl::desc("Enable the machine combiner pass"),
57                                cl::init(true), cl::Hidden);
58 
59 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
60                                           cl::desc("Suppress STP for AArch64"),
61                                           cl::init(true), cl::Hidden);
62 
63 static cl::opt<bool> EnableAdvSIMDScalar(
64     "aarch64-enable-simd-scalar",
65     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
66     cl::init(false), cl::Hidden);
67 
68 static cl::opt<bool>
69     EnablePromoteConstant("aarch64-enable-promote-const",
70                           cl::desc("Enable the promote constant pass"),
71                           cl::init(true), cl::Hidden);
72 
73 static cl::opt<bool> EnableCollectLOH(
74     "aarch64-enable-collect-loh",
75     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
76     cl::init(true), cl::Hidden);
77 
78 static cl::opt<bool>
79     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
80                                   cl::desc("Enable the pass that removes dead"
81                                            " definitons and replaces stores to"
82                                            " them with stores to the zero"
83                                            " register"),
84                                   cl::init(true));
85 
86 static cl::opt<bool> EnableRedundantCopyElimination(
87     "aarch64-enable-copyelim",
88     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
89     cl::Hidden);
90 
91 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
92                                         cl::desc("Enable the load/store pair"
93                                                  " optimization pass"),
94                                         cl::init(true), cl::Hidden);
95 
96 static cl::opt<bool> EnableAtomicTidy(
97     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
98     cl::desc("Run SimplifyCFG after expanding atomic operations"
99              " to make use of cmpxchg flow-based information"),
100     cl::init(true));
101 
102 static cl::opt<bool>
103 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
104                         cl::desc("Run early if-conversion"),
105                         cl::init(true));
106 
107 static cl::opt<bool>
108     EnableCondOpt("aarch64-enable-condopt",
109                   cl::desc("Enable the condition optimizer pass"),
110                   cl::init(true), cl::Hidden);
111 
112 static cl::opt<bool>
113 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
114                 cl::desc("Work around Cortex-A53 erratum 835769"),
115                 cl::init(false));
116 
117 static cl::opt<bool>
118     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
119                  cl::desc("Enable optimizations on complex GEPs"),
120                  cl::init(false));
121 
122 static cl::opt<bool>
123     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
124                      cl::desc("Relax out of range conditional branches"));
125 
126 static cl::opt<bool> EnableCompressJumpTables(
127     "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
128     cl::desc("Use smallest entry possible for jump tables"));
129 
130 // FIXME: Unify control over GlobalMerge.
131 static cl::opt<cl::boolOrDefault>
132     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
133                       cl::desc("Enable the global merge pass"));
134 
135 static cl::opt<bool>
136     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
137                            cl::desc("Enable the loop data prefetch pass"),
138                            cl::init(true));
139 
140 static cl::opt<int> EnableGlobalISelAtO(
141     "aarch64-enable-global-isel-at-O", cl::Hidden,
142     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
143     cl::init(0));
144 
145 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
146                                          cl::init(true), cl::Hidden);
147 
148 static cl::opt<bool>
149     EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
150                         cl::desc("Enable the AAcrh64 branch target pass"),
151                         cl::init(true));
152 
153 extern "C" void LLVMInitializeAArch64Target() {
154   // Register the target.
155   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
156   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
157   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
158   auto PR = PassRegistry::getPassRegistry();
159   initializeGlobalISel(*PR);
160   initializeAArch64A53Fix835769Pass(*PR);
161   initializeAArch64A57FPLoadBalancingPass(*PR);
162   initializeAArch64AdvSIMDScalarPass(*PR);
163   initializeAArch64BranchTargetsPass(*PR);
164   initializeAArch64CollectLOHPass(*PR);
165   initializeAArch64CompressJumpTablesPass(*PR);
166   initializeAArch64ConditionalComparesPass(*PR);
167   initializeAArch64ConditionOptimizerPass(*PR);
168   initializeAArch64DeadRegisterDefinitionsPass(*PR);
169   initializeAArch64ExpandPseudoPass(*PR);
170   initializeAArch64LoadStoreOptPass(*PR);
171   initializeAArch64SIMDInstrOptPass(*PR);
172   initializeAArch64PreLegalizerCombinerPass(*PR);
173   initializeAArch64PromoteConstantPass(*PR);
174   initializeAArch64RedundantCopyEliminationPass(*PR);
175   initializeAArch64StorePairSuppressPass(*PR);
176   initializeFalkorHWPFFixPass(*PR);
177   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
178   initializeLDTLSCleanupPass(*PR);
179 }
180 
181 //===----------------------------------------------------------------------===//
182 // AArch64 Lowering public interface.
183 //===----------------------------------------------------------------------===//
184 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
185   if (TT.isOSBinFormatMachO())
186     return llvm::make_unique<AArch64_MachoTargetObjectFile>();
187   if (TT.isOSBinFormatCOFF())
188     return llvm::make_unique<AArch64_COFFTargetObjectFile>();
189 
190   return llvm::make_unique<AArch64_ELFTargetObjectFile>();
191 }
192 
193 // Helper function to build a DataLayout string
194 static std::string computeDataLayout(const Triple &TT,
195                                      const MCTargetOptions &Options,
196                                      bool LittleEndian) {
197   if (Options.getABIName() == "ilp32")
198     return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
199   if (TT.isOSBinFormatMachO())
200     return "e-m:o-i64:64-i128:128-n32:64-S128";
201   if (TT.isOSBinFormatCOFF())
202     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
203   if (LittleEndian)
204     return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
205   return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
206 }
207 
208 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
209                                            Optional<Reloc::Model> RM) {
210   // AArch64 Darwin is always PIC.
211   if (TT.isOSDarwin())
212     return Reloc::PIC_;
213   // On ELF platforms the default static relocation model has a smart enough
214   // linker to cope with referencing external symbols defined in a shared
215   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
216   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
217     return Reloc::Static;
218   return *RM;
219 }
220 
221 static CodeModel::Model getEffectiveCodeModel(const Triple &TT,
222                                               Optional<CodeModel::Model> CM,
223                                               bool JIT) {
224   if (CM) {
225     if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
226         *CM != CodeModel::Large) {
227       if (!TT.isOSFuchsia())
228         report_fatal_error(
229             "Only small, tiny and large code models are allowed on AArch64");
230       else if (*CM != CodeModel::Kernel)
231         report_fatal_error("Only small, tiny, kernel, and large code models "
232                            "are allowed on AArch64");
233     } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
234       report_fatal_error("tiny code model is only supported on ELF");
235     return *CM;
236   }
237   // The default MCJIT memory managers make no guarantees about where they can
238   // find an executable page; JITed code needs to be able to refer to globals
239   // no matter how far away they are.
240   if (JIT)
241     return CodeModel::Large;
242   return CodeModel::Small;
243 }
244 
245 /// Create an AArch64 architecture model.
246 ///
247 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
248                                            StringRef CPU, StringRef FS,
249                                            const TargetOptions &Options,
250                                            Optional<Reloc::Model> RM,
251                                            Optional<CodeModel::Model> CM,
252                                            CodeGenOpt::Level OL, bool JIT,
253                                            bool LittleEndian)
254     : LLVMTargetMachine(T,
255                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
256                         TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
257                         getEffectiveCodeModel(TT, CM, JIT), OL),
258       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
259   initAsmInfo();
260 
261   if (TT.isOSBinFormatMachO()) {
262     this->Options.TrapUnreachable = true;
263     this->Options.NoTrapAfterNoreturn = true;
264   }
265 
266   // Enable GlobalISel at or below EnableGlobalISelAt0.
267   if (getOptLevel() <= EnableGlobalISelAtO)
268     setGlobalISel(true);
269 
270   // AArch64 supports the MachineOutliner.
271   setMachineOutliner(true);
272 
273   // AArch64 supports default outlining behaviour.
274   setSupportsDefaultOutlining(true);
275 }
276 
277 AArch64TargetMachine::~AArch64TargetMachine() = default;
278 
279 const AArch64Subtarget *
280 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
281   Attribute CPUAttr = F.getFnAttribute("target-cpu");
282   Attribute FSAttr = F.getFnAttribute("target-features");
283 
284   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
285                         ? CPUAttr.getValueAsString().str()
286                         : TargetCPU;
287   std::string FS = !FSAttr.hasAttribute(Attribute::None)
288                        ? FSAttr.getValueAsString().str()
289                        : TargetFS;
290 
291   auto &I = SubtargetMap[CPU + FS];
292   if (!I) {
293     // This needs to be done before we create a new subtarget since any
294     // creation will depend on the TM and the code generation flags on the
295     // function that reside in TargetOptions.
296     resetTargetOptions(F);
297     I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
298                                             isLittle);
299   }
300   return I.get();
301 }
302 
303 void AArch64leTargetMachine::anchor() { }
304 
305 AArch64leTargetMachine::AArch64leTargetMachine(
306     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
307     const TargetOptions &Options, Optional<Reloc::Model> RM,
308     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
309     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
310 
311 void AArch64beTargetMachine::anchor() { }
312 
313 AArch64beTargetMachine::AArch64beTargetMachine(
314     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
315     const TargetOptions &Options, Optional<Reloc::Model> RM,
316     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
317     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
318 
319 namespace {
320 
321 /// AArch64 Code Generator Pass Configuration Options.
322 class AArch64PassConfig : public TargetPassConfig {
323 public:
324   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
325       : TargetPassConfig(TM, PM) {
326     if (TM.getOptLevel() != CodeGenOpt::None)
327       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
328   }
329 
330   AArch64TargetMachine &getAArch64TargetMachine() const {
331     return getTM<AArch64TargetMachine>();
332   }
333 
334   ScheduleDAGInstrs *
335   createMachineScheduler(MachineSchedContext *C) const override {
336     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
337     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
338     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
339     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
340     if (ST.hasFusion())
341       DAG->addMutation(createAArch64MacroFusionDAGMutation());
342     return DAG;
343   }
344 
345   ScheduleDAGInstrs *
346   createPostMachineScheduler(MachineSchedContext *C) const override {
347     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
348     if (ST.hasFusion()) {
349       // Run the Macro Fusion after RA again since literals are expanded from
350       // pseudos then (v. addPreSched2()).
351       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
352       DAG->addMutation(createAArch64MacroFusionDAGMutation());
353       return DAG;
354     }
355 
356     return nullptr;
357   }
358 
359   void addIRPasses()  override;
360   bool addPreISel() override;
361   bool addInstSelector() override;
362   bool addIRTranslator() override;
363   void addPreLegalizeMachineIR() override;
364   bool addLegalizeMachineIR() override;
365   bool addRegBankSelect() override;
366   void addPreGlobalInstructionSelect() override;
367   bool addGlobalInstructionSelect() override;
368   bool addILPOpts() override;
369   void addPreRegAlloc() override;
370   void addPostRegAlloc() override;
371   void addPreSched2() override;
372   void addPreEmitPass() override;
373 };
374 
375 } // end anonymous namespace
376 
377 TargetTransformInfo
378 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
379   return TargetTransformInfo(AArch64TTIImpl(this, F));
380 }
381 
382 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
383   return new AArch64PassConfig(*this, PM);
384 }
385 
386 void AArch64PassConfig::addIRPasses() {
387   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
388   // ourselves.
389   addPass(createAtomicExpandPass());
390 
391   // Cmpxchg instructions are often used with a subsequent comparison to
392   // determine whether it succeeded. We can exploit existing control-flow in
393   // ldrex/strex loops to simplify this, but it needs tidying up.
394   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
395     addPass(createCFGSimplificationPass(1, true, true, false, true));
396 
397   // Run LoopDataPrefetch
398   //
399   // Run this before LSR to remove the multiplies involved in computing the
400   // pointer values N iterations ahead.
401   if (TM->getOptLevel() != CodeGenOpt::None) {
402     if (EnableLoopDataPrefetch)
403       addPass(createLoopDataPrefetchPass());
404     if (EnableFalkorHWPFFix)
405       addPass(createFalkorMarkStridedAccessesPass());
406   }
407 
408   TargetPassConfig::addIRPasses();
409 
410   // Match interleaved memory accesses to ldN/stN intrinsics.
411   if (TM->getOptLevel() != CodeGenOpt::None)
412     addPass(createInterleavedAccessPass());
413 
414   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
415     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
416     // and lower a GEP with multiple indices to either arithmetic operations or
417     // multiple GEPs with single index.
418     addPass(createSeparateConstOffsetFromGEPPass(true));
419     // Call EarlyCSE pass to find and remove subexpressions in the lowered
420     // result.
421     addPass(createEarlyCSEPass());
422     // Do loop invariant code motion in case part of the lowered result is
423     // invariant.
424     addPass(createLICMPass());
425   }
426 }
427 
428 // Pass Pipeline Configuration
429 bool AArch64PassConfig::addPreISel() {
430   // Run promote constant before global merge, so that the promoted constants
431   // get a chance to be merged
432   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
433     addPass(createAArch64PromoteConstantPass());
434   // FIXME: On AArch64, this depends on the type.
435   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
436   // and the offset has to be a multiple of the related size in bytes.
437   if ((TM->getOptLevel() != CodeGenOpt::None &&
438        EnableGlobalMerge == cl::BOU_UNSET) ||
439       EnableGlobalMerge == cl::BOU_TRUE) {
440     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
441                                (EnableGlobalMerge == cl::BOU_UNSET);
442     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
443   }
444 
445   return false;
446 }
447 
448 bool AArch64PassConfig::addInstSelector() {
449   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
450 
451   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
452   // references to _TLS_MODULE_BASE_ as possible.
453   if (TM->getTargetTriple().isOSBinFormatELF() &&
454       getOptLevel() != CodeGenOpt::None)
455     addPass(createAArch64CleanupLocalDynamicTLSPass());
456 
457   return false;
458 }
459 
460 bool AArch64PassConfig::addIRTranslator() {
461   addPass(new IRTranslator());
462   return false;
463 }
464 
465 void AArch64PassConfig::addPreLegalizeMachineIR() {
466   addPass(createAArch64PreLegalizeCombiner());
467 }
468 
469 bool AArch64PassConfig::addLegalizeMachineIR() {
470   addPass(new Legalizer());
471   return false;
472 }
473 
474 bool AArch64PassConfig::addRegBankSelect() {
475   addPass(new RegBankSelect());
476   return false;
477 }
478 
479 void AArch64PassConfig::addPreGlobalInstructionSelect() {
480   // Workaround the deficiency of the fast register allocator.
481   if (TM->getOptLevel() == CodeGenOpt::None)
482     addPass(new Localizer());
483 }
484 
485 bool AArch64PassConfig::addGlobalInstructionSelect() {
486   addPass(new InstructionSelect());
487   return false;
488 }
489 
490 bool AArch64PassConfig::addILPOpts() {
491   if (EnableCondOpt)
492     addPass(createAArch64ConditionOptimizerPass());
493   if (EnableCCMP)
494     addPass(createAArch64ConditionalCompares());
495   if (EnableMCR)
496     addPass(&MachineCombinerID);
497   if (EnableCondBrTuning)
498     addPass(createAArch64CondBrTuning());
499   if (EnableEarlyIfConversion)
500     addPass(&EarlyIfConverterID);
501   if (EnableStPairSuppress)
502     addPass(createAArch64StorePairSuppressPass());
503   addPass(createAArch64SIMDInstrOptPass());
504   return true;
505 }
506 
507 void AArch64PassConfig::addPreRegAlloc() {
508   // Change dead register definitions to refer to the zero register.
509   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
510     addPass(createAArch64DeadRegisterDefinitions());
511 
512   // Use AdvSIMD scalar instructions whenever profitable.
513   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
514     addPass(createAArch64AdvSIMDScalar());
515     // The AdvSIMD pass may produce copies that can be rewritten to
516     // be register coaleascer friendly.
517     addPass(&PeepholeOptimizerID);
518   }
519 }
520 
521 void AArch64PassConfig::addPostRegAlloc() {
522   // Remove redundant copy instructions.
523   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
524     addPass(createAArch64RedundantCopyEliminationPass());
525 
526   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
527     // Improve performance for some FP/SIMD code for A57.
528     addPass(createAArch64A57FPLoadBalancing());
529 }
530 
531 void AArch64PassConfig::addPreSched2() {
532   // Expand some pseudo instructions to allow proper scheduling.
533   addPass(createAArch64ExpandPseudoPass());
534   // Use load/store pair instructions when possible.
535   if (TM->getOptLevel() != CodeGenOpt::None) {
536     if (EnableLoadStoreOpt)
537       addPass(createAArch64LoadStoreOptimizationPass());
538     if (EnableFalkorHWPFFix)
539       addPass(createFalkorHWPFFixPass());
540   }
541 }
542 
543 void AArch64PassConfig::addPreEmitPass() {
544   if (EnableA53Fix835769)
545     addPass(createAArch64A53Fix835769());
546   // Relax conditional branch instructions if they're otherwise out of
547   // range of their destination.
548   if (BranchRelaxation)
549     addPass(&BranchRelaxationPassID);
550 
551   if (EnableBranchTargets)
552     addPass(createAArch64BranchTargetsPass());
553 
554   if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
555     addPass(createAArch64CompressJumpTablesPass());
556 
557   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
558       TM->getTargetTriple().isOSBinFormatMachO())
559     addPass(createAArch64CollectLOHPass());
560 }
561