1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64.h"
14 #include "AArch64TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/TargetRegistry.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Transforms/Scalar.h"
21 using namespace llvm;
22 
23 static cl::opt<bool>
24 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
25            cl::init(true), cl::Hidden);
26 
27 static cl::opt<bool>
28 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
29                      cl::init(true), cl::Hidden);
30 
31 static cl::opt<bool>
32 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
33                     " integer instructions"), cl::init(false), cl::Hidden);
34 
35 static cl::opt<bool>
36 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
37                       "constant pass"), cl::init(true), cl::Hidden);
38 
39 static cl::opt<bool>
40 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
41                  " linker optimization hints (LOH)"), cl::init(true),
42                  cl::Hidden);
43 
44 static cl::opt<bool>
45 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
46                               cl::desc("Enable the pass that removes dead"
47                                        " definitons and replaces stores to"
48                                        " them with stores to the zero"
49                                        " register"),
50                               cl::init(true));
51 
52 static cl::opt<bool>
53 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
54                    " optimization pass"), cl::init(true), cl::Hidden);
55 
56 extern "C" void LLVMInitializeAArch64Target() {
57   // Register the target.
58   RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
59   RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
60 
61   RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64leTarget);
62   RegisterTargetMachine<AArch64beTargetMachine> W(TheARM64beTarget);
63 }
64 
65 /// TargetMachine ctor - Create an AArch64 architecture model.
66 ///
67 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
68                                            StringRef CPU, StringRef FS,
69                                            const TargetOptions &Options,
70                                            Reloc::Model RM, CodeModel::Model CM,
71                                            CodeGenOpt::Level OL,
72                                            bool LittleEndian)
73     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
74       Subtarget(TT, CPU, FS, LittleEndian),
75       // This nested ternary is horrible, but DL needs to be properly
76       // initialized
77       // before TLInfo is constructed.
78       DL(Subtarget.isTargetMachO()
79              ? "e-m:o-i64:64-i128:128-n32:64-S128"
80              : (LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128"
81                              : "E-m:e-i64:64-i128:128-n32:64-S128")),
82       InstrInfo(Subtarget), TLInfo(*this), FrameLowering(*this, Subtarget),
83       TSInfo(*this) {
84   initAsmInfo();
85 }
86 
87 void AArch64leTargetMachine::anchor() { }
88 
89 AArch64leTargetMachine::
90 AArch64leTargetMachine(const Target &T, StringRef TT,
91                        StringRef CPU, StringRef FS, const TargetOptions &Options,
92                        Reloc::Model RM, CodeModel::Model CM,
93                        CodeGenOpt::Level OL)
94   : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
95 
96 void AArch64beTargetMachine::anchor() { }
97 
98 AArch64beTargetMachine::
99 AArch64beTargetMachine(const Target &T, StringRef TT,
100                        StringRef CPU, StringRef FS, const TargetOptions &Options,
101                        Reloc::Model RM, CodeModel::Model CM,
102                        CodeGenOpt::Level OL)
103   : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
104 
105 namespace {
106 /// AArch64 Code Generator Pass Configuration Options.
107 class AArch64PassConfig : public TargetPassConfig {
108 public:
109   AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
110       : TargetPassConfig(TM, PM) {}
111 
112   AArch64TargetMachine &getAArch64TargetMachine() const {
113     return getTM<AArch64TargetMachine>();
114   }
115 
116   bool addPreISel() override;
117   bool addInstSelector() override;
118   bool addILPOpts() override;
119   bool addPreRegAlloc() override;
120   bool addPostRegAlloc() override;
121   bool addPreSched2() override;
122   bool addPreEmitPass() override;
123 };
124 } // namespace
125 
126 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
127   // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
128   // allows the AArch64 pass to delegate to the target independent layer when
129   // appropriate.
130   PM.add(createBasicTargetTransformInfoPass(this));
131   PM.add(createAArch64TargetTransformInfoPass(this));
132 }
133 
134 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
135   return new AArch64PassConfig(this, PM);
136 }
137 
138 // Pass Pipeline Configuration
139 bool AArch64PassConfig::addPreISel() {
140   // Run promote constant before global merge, so that the promoted constants
141   // get a chance to be merged
142   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
143     addPass(createAArch64PromoteConstantPass());
144   if (TM->getOptLevel() != CodeGenOpt::None)
145     addPass(createGlobalMergePass(TM));
146   if (TM->getOptLevel() != CodeGenOpt::None)
147     addPass(createAArch64AddressTypePromotionPass());
148 
149   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
150   // ourselves.
151   addPass(createAtomicExpandLoadLinkedPass(TM));
152 
153   return false;
154 }
155 
156 bool AArch64PassConfig::addInstSelector() {
157   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
158 
159   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
160   // references to _TLS_MODULE_BASE_ as possible.
161   if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
162       getOptLevel() != CodeGenOpt::None)
163     addPass(createAArch64CleanupLocalDynamicTLSPass());
164 
165   return false;
166 }
167 
168 bool AArch64PassConfig::addILPOpts() {
169   if (EnableCCMP)
170     addPass(createAArch64ConditionalCompares());
171   addPass(&EarlyIfConverterID);
172   if (EnableStPairSuppress)
173     addPass(createAArch64StorePairSuppressPass());
174   return true;
175 }
176 
177 bool AArch64PassConfig::addPreRegAlloc() {
178   // Use AdvSIMD scalar instructions whenever profitable.
179   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar)
180     addPass(createAArch64AdvSIMDScalar());
181   return true;
182 }
183 
184 bool AArch64PassConfig::addPostRegAlloc() {
185   // Change dead register definitions to refer to the zero register.
186   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
187     addPass(createAArch64DeadRegisterDefinitions());
188   return true;
189 }
190 
191 bool AArch64PassConfig::addPreSched2() {
192   // Expand some pseudo instructions to allow proper scheduling.
193   addPass(createAArch64ExpandPseudoPass());
194   // Use load/store pair instructions when possible.
195   if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
196     addPass(createAArch64LoadStoreOptimizationPass());
197   return true;
198 }
199 
200 bool AArch64PassConfig::addPreEmitPass() {
201   // Relax conditional branch instructions if they're otherwise out of
202   // range of their destination.
203   addPass(createAArch64BranchRelaxation());
204   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
205       TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
206     addPass(createAArch64CollectLOHPass());
207   return true;
208 }
209