1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64.h"
14 #include "AArch64TargetMachine.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/CodeGen/RegAllocRegistry.h"
17 #include "llvm/IR/Function.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/TargetRegistry.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Transforms/Scalar.h"
23 using namespace llvm;
24 
25 static cl::opt<bool>
26 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
27            cl::init(true), cl::Hidden);
28 
29 static cl::opt<bool> EnableMCR("aarch64-mcr",
30                                cl::desc("Enable the machine combiner pass"),
31                                cl::init(true), cl::Hidden);
32 
33 static cl::opt<bool>
34 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
35                      cl::init(true), cl::Hidden);
36 
37 static cl::opt<bool>
38 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
39                     " integer instructions"), cl::init(false), cl::Hidden);
40 
41 static cl::opt<bool>
42 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
43                       "constant pass"), cl::init(true), cl::Hidden);
44 
45 static cl::opt<bool>
46 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
47                  " linker optimization hints (LOH)"), cl::init(true),
48                  cl::Hidden);
49 
50 static cl::opt<bool>
51 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
52                               cl::desc("Enable the pass that removes dead"
53                                        " definitons and replaces stores to"
54                                        " them with stores to the zero"
55                                        " register"),
56                               cl::init(true));
57 
58 static cl::opt<bool>
59 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
60                    " optimization pass"), cl::init(true), cl::Hidden);
61 
62 static cl::opt<bool>
63 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
64                  cl::desc("Run SimplifyCFG after expanding atomic operations"
65                           " to make use of cmpxchg flow-based information"),
66                  cl::init(true));
67 
68 static cl::opt<bool>
69 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
70                         cl::desc("Run early if-conversion"),
71                         cl::init(true));
72 
73 static cl::opt<bool>
74 EnableCondOpt("aarch64-condopt",
75               cl::desc("Enable the condition optimizer pass"),
76               cl::init(true), cl::Hidden);
77 
78 static cl::opt<bool>
79 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
80                 cl::desc("Work around Cortex-A53 erratum 835769"),
81                 cl::init(false));
82 
83 extern "C" void LLVMInitializeAArch64Target() {
84   // Register the target.
85   RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
86   RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
87   RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
88 }
89 
90 /// TargetMachine ctor - Create an AArch64 architecture model.
91 ///
92 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
93                                            StringRef CPU, StringRef FS,
94                                            const TargetOptions &Options,
95                                            Reloc::Model RM, CodeModel::Model CM,
96                                            CodeGenOpt::Level OL,
97                                            bool LittleEndian)
98     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
99       Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian) {
100   initAsmInfo();
101 }
102 
103 const AArch64Subtarget *
104 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
105   AttributeSet FnAttrs = F.getAttributes();
106   Attribute CPUAttr =
107       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
108   Attribute FSAttr =
109       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
110 
111   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
112                         ? CPUAttr.getValueAsString().str()
113                         : TargetCPU;
114   std::string FS = !FSAttr.hasAttribute(Attribute::None)
115                        ? FSAttr.getValueAsString().str()
116                        : TargetFS;
117 
118   auto &I = SubtargetMap[CPU + FS];
119   if (!I) {
120     // This needs to be done before we create a new subtarget since any
121     // creation will depend on the TM and the code generation flags on the
122     // function that reside in TargetOptions.
123     resetTargetOptions(F);
124     I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle);
125   }
126   return I.get();
127 }
128 
129 void AArch64leTargetMachine::anchor() { }
130 
131 AArch64leTargetMachine::
132 AArch64leTargetMachine(const Target &T, StringRef TT,
133                        StringRef CPU, StringRef FS, const TargetOptions &Options,
134                        Reloc::Model RM, CodeModel::Model CM,
135                        CodeGenOpt::Level OL)
136   : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
137 
138 void AArch64beTargetMachine::anchor() { }
139 
140 AArch64beTargetMachine::
141 AArch64beTargetMachine(const Target &T, StringRef TT,
142                        StringRef CPU, StringRef FS, const TargetOptions &Options,
143                        Reloc::Model RM, CodeModel::Model CM,
144                        CodeGenOpt::Level OL)
145   : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
146 
147 namespace {
148 /// AArch64 Code Generator Pass Configuration Options.
149 class AArch64PassConfig : public TargetPassConfig {
150 public:
151   AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
152       : TargetPassConfig(TM, PM) {
153     if (TM->getOptLevel() != CodeGenOpt::None)
154       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
155   }
156 
157   AArch64TargetMachine &getAArch64TargetMachine() const {
158     return getTM<AArch64TargetMachine>();
159   }
160 
161   void addIRPasses()  override;
162   bool addPreISel() override;
163   bool addInstSelector() override;
164   bool addILPOpts() override;
165   bool addPreRegAlloc() override;
166   bool addPostRegAlloc() override;
167   bool addPreSched2() override;
168   bool addPreEmitPass() override;
169 };
170 } // namespace
171 
172 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
173   // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
174   // allows the AArch64 pass to delegate to the target independent layer when
175   // appropriate.
176   PM.add(createBasicTargetTransformInfoPass(this));
177   PM.add(createAArch64TargetTransformInfoPass(this));
178 }
179 
180 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
181   return new AArch64PassConfig(this, PM);
182 }
183 
184 void AArch64PassConfig::addIRPasses() {
185   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
186   // ourselves.
187   addPass(createAtomicExpandPass(TM));
188 
189   // Cmpxchg instructions are often used with a subsequent comparison to
190   // determine whether it succeeded. We can exploit existing control-flow in
191   // ldrex/strex loops to simplify this, but it needs tidying up.
192   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
193     addPass(createCFGSimplificationPass());
194 
195   TargetPassConfig::addIRPasses();
196 }
197 
198 // Pass Pipeline Configuration
199 bool AArch64PassConfig::addPreISel() {
200   // Run promote constant before global merge, so that the promoted constants
201   // get a chance to be merged
202   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
203     addPass(createAArch64PromoteConstantPass());
204   if (TM->getOptLevel() != CodeGenOpt::None)
205     addPass(createGlobalMergePass(TM));
206   if (TM->getOptLevel() != CodeGenOpt::None)
207     addPass(createAArch64AddressTypePromotionPass());
208 
209   return false;
210 }
211 
212 bool AArch64PassConfig::addInstSelector() {
213   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
214 
215   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
216   // references to _TLS_MODULE_BASE_ as possible.
217   if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
218       getOptLevel() != CodeGenOpt::None)
219     addPass(createAArch64CleanupLocalDynamicTLSPass());
220 
221   return false;
222 }
223 
224 bool AArch64PassConfig::addILPOpts() {
225   if (EnableCondOpt)
226     addPass(createAArch64ConditionOptimizerPass());
227   if (EnableCCMP)
228     addPass(createAArch64ConditionalCompares());
229   if (EnableMCR)
230     addPass(&MachineCombinerID);
231   if (EnableEarlyIfConversion)
232     addPass(&EarlyIfConverterID);
233   if (EnableStPairSuppress)
234     addPass(createAArch64StorePairSuppressPass());
235   return true;
236 }
237 
238 bool AArch64PassConfig::addPreRegAlloc() {
239   // Use AdvSIMD scalar instructions whenever profitable.
240   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
241     addPass(createAArch64AdvSIMDScalar());
242     // The AdvSIMD pass may produce copies that can be rewritten to
243     // be register coaleascer friendly.
244     addPass(&PeepholeOptimizerID);
245   }
246   return true;
247 }
248 
249 bool AArch64PassConfig::addPostRegAlloc() {
250   // Change dead register definitions to refer to the zero register.
251   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
252     addPass(createAArch64DeadRegisterDefinitions());
253   if (TM->getOptLevel() != CodeGenOpt::None &&
254       (TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
255        TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
256       usingDefaultRegAlloc())
257     // Improve performance for some FP/SIMD code for A57.
258     addPass(createAArch64A57FPLoadBalancing());
259   return true;
260 }
261 
262 bool AArch64PassConfig::addPreSched2() {
263   // Expand some pseudo instructions to allow proper scheduling.
264   addPass(createAArch64ExpandPseudoPass());
265   // Use load/store pair instructions when possible.
266   if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
267     addPass(createAArch64LoadStoreOptimizationPass());
268   return true;
269 }
270 
271 bool AArch64PassConfig::addPreEmitPass() {
272   if (EnableA53Fix835769)
273     addPass(createAArch64A53Fix835769());
274   // Relax conditional branch instructions if they're otherwise out of
275   // range of their destination.
276   addPass(createAArch64BranchRelaxation());
277   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
278       TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
279     addPass(createAArch64CollectLOHPass());
280   return true;
281 }
282