1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64TargetMachine.h"
14 #include "AArch64.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetObjectFile.h"
18 #include "AArch64TargetTransformInfo.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
25 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
26 #include "llvm/CodeGen/GlobalISel/Localizer.h"
27 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
28 #include "llvm/CodeGen/MachineScheduler.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/CodeGen/TargetPassConfig.h"
31 #include "llvm/IR/Attributes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCTargetOptions.h"
35 #include "llvm/Pass.h"
36 #include "llvm/Support/CodeGen.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Transforms/Scalar.h"
42 #include <memory>
43 #include <string>
44 
45 using namespace llvm;
46 
47 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
48                                 cl::desc("Enable the CCMP formation pass"),
49                                 cl::init(true), cl::Hidden);
50 
51 static cl::opt<bool>
52     EnableCondBrTuning("aarch64-enable-cond-br-tune",
53                        cl::desc("Enable the conditional branch tuning pass"),
54                        cl::init(true), cl::Hidden);
55 
56 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
57                                cl::desc("Enable the machine combiner pass"),
58                                cl::init(true), cl::Hidden);
59 
60 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
61                                           cl::desc("Suppress STP for AArch64"),
62                                           cl::init(true), cl::Hidden);
63 
64 static cl::opt<bool> EnableAdvSIMDScalar(
65     "aarch64-enable-simd-scalar",
66     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
67     cl::init(false), cl::Hidden);
68 
69 static cl::opt<bool>
70     EnablePromoteConstant("aarch64-enable-promote-const",
71                           cl::desc("Enable the promote constant pass"),
72                           cl::init(true), cl::Hidden);
73 
74 static cl::opt<bool> EnableCollectLOH(
75     "aarch64-enable-collect-loh",
76     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
77     cl::init(true), cl::Hidden);
78 
79 static cl::opt<bool>
80     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
81                                   cl::desc("Enable the pass that removes dead"
82                                            " definitons and replaces stores to"
83                                            " them with stores to the zero"
84                                            " register"),
85                                   cl::init(true));
86 
87 static cl::opt<bool> EnableRedundantCopyElimination(
88     "aarch64-enable-copyelim",
89     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
90     cl::Hidden);
91 
92 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
93                                         cl::desc("Enable the load/store pair"
94                                                  " optimization pass"),
95                                         cl::init(true), cl::Hidden);
96 
97 static cl::opt<bool> EnableAtomicTidy(
98     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
99     cl::desc("Run SimplifyCFG after expanding atomic operations"
100              " to make use of cmpxchg flow-based information"),
101     cl::init(true));
102 
103 static cl::opt<bool>
104 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
105                         cl::desc("Run early if-conversion"),
106                         cl::init(true));
107 
108 static cl::opt<bool>
109     EnableCondOpt("aarch64-enable-condopt",
110                   cl::desc("Enable the condition optimizer pass"),
111                   cl::init(true), cl::Hidden);
112 
113 static cl::opt<bool>
114 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
115                 cl::desc("Work around Cortex-A53 erratum 835769"),
116                 cl::init(false));
117 
118 static cl::opt<bool>
119     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
120                  cl::desc("Enable optimizations on complex GEPs"),
121                  cl::init(false));
122 
123 static cl::opt<bool>
124     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
125                      cl::desc("Relax out of range conditional branches"));
126 
127 static cl::opt<bool> EnableCompressJumpTables(
128     "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
129     cl::desc("Use smallest entry possible for jump tables"));
130 
131 // FIXME: Unify control over GlobalMerge.
132 static cl::opt<cl::boolOrDefault>
133     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
134                       cl::desc("Enable the global merge pass"));
135 
136 static cl::opt<bool>
137     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
138                            cl::desc("Enable the loop data prefetch pass"),
139                            cl::init(true));
140 
141 static cl::opt<int> EnableGlobalISelAtO(
142     "aarch64-enable-global-isel-at-O", cl::Hidden,
143     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
144     cl::init(0));
145 
146 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
147                                          cl::init(true), cl::Hidden);
148 
149 static cl::opt<bool>
150     EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
151                         cl::desc("Enable the AAcrh64 branch target pass"),
152                         cl::init(true));
153 
154 extern "C" void LLVMInitializeAArch64Target() {
155   // Register the target.
156   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
157   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
158   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
159   auto PR = PassRegistry::getPassRegistry();
160   initializeGlobalISel(*PR);
161   initializeAArch64A53Fix835769Pass(*PR);
162   initializeAArch64A57FPLoadBalancingPass(*PR);
163   initializeAArch64AdvSIMDScalarPass(*PR);
164   initializeAArch64BranchTargetsPass(*PR);
165   initializeAArch64CollectLOHPass(*PR);
166   initializeAArch64CompressJumpTablesPass(*PR);
167   initializeAArch64ConditionalComparesPass(*PR);
168   initializeAArch64ConditionOptimizerPass(*PR);
169   initializeAArch64DeadRegisterDefinitionsPass(*PR);
170   initializeAArch64ExpandPseudoPass(*PR);
171   initializeAArch64LoadStoreOptPass(*PR);
172   initializeAArch64SIMDInstrOptPass(*PR);
173   initializeAArch64PreLegalizerCombinerPass(*PR);
174   initializeAArch64PromoteConstantPass(*PR);
175   initializeAArch64RedundantCopyEliminationPass(*PR);
176   initializeAArch64StorePairSuppressPass(*PR);
177   initializeFalkorHWPFFixPass(*PR);
178   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
179   initializeLDTLSCleanupPass(*PR);
180 }
181 
182 //===----------------------------------------------------------------------===//
183 // AArch64 Lowering public interface.
184 //===----------------------------------------------------------------------===//
185 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
186   if (TT.isOSBinFormatMachO())
187     return llvm::make_unique<AArch64_MachoTargetObjectFile>();
188   if (TT.isOSBinFormatCOFF())
189     return llvm::make_unique<AArch64_COFFTargetObjectFile>();
190 
191   return llvm::make_unique<AArch64_ELFTargetObjectFile>();
192 }
193 
194 // Helper function to build a DataLayout string
195 static std::string computeDataLayout(const Triple &TT,
196                                      const MCTargetOptions &Options,
197                                      bool LittleEndian) {
198   if (Options.getABIName() == "ilp32")
199     return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
200   if (TT.isOSBinFormatMachO())
201     return "e-m:o-i64:64-i128:128-n32:64-S128";
202   if (TT.isOSBinFormatCOFF())
203     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
204   if (LittleEndian)
205     return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
206   return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
207 }
208 
209 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
210                                            Optional<Reloc::Model> RM) {
211   // AArch64 Darwin is always PIC.
212   if (TT.isOSDarwin())
213     return Reloc::PIC_;
214   // On ELF platforms the default static relocation model has a smart enough
215   // linker to cope with referencing external symbols defined in a shared
216   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
217   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
218     return Reloc::Static;
219   return *RM;
220 }
221 
222 static CodeModel::Model getEffectiveCodeModel(const Triple &TT,
223                                               Optional<CodeModel::Model> CM,
224                                               bool JIT) {
225   if (CM) {
226     if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
227         *CM != CodeModel::Large) {
228       if (!TT.isOSFuchsia())
229         report_fatal_error(
230             "Only small, tiny and large code models are allowed on AArch64");
231       else if (*CM != CodeModel::Kernel)
232         report_fatal_error("Only small, tiny, kernel, and large code models "
233                            "are allowed on AArch64");
234     } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
235       report_fatal_error("tiny code model is only supported on ELF");
236     return *CM;
237   }
238   // The default MCJIT memory managers make no guarantees about where they can
239   // find an executable page; JITed code needs to be able to refer to globals
240   // no matter how far away they are.
241   if (JIT)
242     return CodeModel::Large;
243   return CodeModel::Small;
244 }
245 
246 /// Create an AArch64 architecture model.
247 ///
248 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
249                                            StringRef CPU, StringRef FS,
250                                            const TargetOptions &Options,
251                                            Optional<Reloc::Model> RM,
252                                            Optional<CodeModel::Model> CM,
253                                            CodeGenOpt::Level OL, bool JIT,
254                                            bool LittleEndian)
255     : LLVMTargetMachine(T,
256                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
257                         TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
258                         getEffectiveCodeModel(TT, CM, JIT), OL),
259       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
260   initAsmInfo();
261 
262   if (TT.isOSBinFormatMachO()) {
263     this->Options.TrapUnreachable = true;
264     this->Options.NoTrapAfterNoreturn = true;
265   }
266 
267   if (getMCAsmInfo()->usesWindowsCFI()) {
268     // Unwinding can get confused if the last instruction in an
269     // exception-handling region (function, funclet, try block, etc.)
270     // is a call.
271     //
272     // FIXME: We could elide the trap if the next instruction would be in
273     // the same region anyway.
274     this->Options.TrapUnreachable = true;
275   }
276 
277   // Enable GlobalISel at or below EnableGlobalISelAt0.
278   if (getOptLevel() <= EnableGlobalISelAtO)
279     setGlobalISel(true);
280 
281   // AArch64 supports the MachineOutliner.
282   setMachineOutliner(true);
283 
284   // AArch64 supports default outlining behaviour.
285   setSupportsDefaultOutlining(true);
286 }
287 
288 AArch64TargetMachine::~AArch64TargetMachine() = default;
289 
290 const AArch64Subtarget *
291 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
292   Attribute CPUAttr = F.getFnAttribute("target-cpu");
293   Attribute FSAttr = F.getFnAttribute("target-features");
294 
295   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
296                         ? CPUAttr.getValueAsString().str()
297                         : TargetCPU;
298   std::string FS = !FSAttr.hasAttribute(Attribute::None)
299                        ? FSAttr.getValueAsString().str()
300                        : TargetFS;
301 
302   auto &I = SubtargetMap[CPU + FS];
303   if (!I) {
304     // This needs to be done before we create a new subtarget since any
305     // creation will depend on the TM and the code generation flags on the
306     // function that reside in TargetOptions.
307     resetTargetOptions(F);
308     I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
309                                             isLittle);
310   }
311   return I.get();
312 }
313 
314 void AArch64leTargetMachine::anchor() { }
315 
316 AArch64leTargetMachine::AArch64leTargetMachine(
317     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
318     const TargetOptions &Options, Optional<Reloc::Model> RM,
319     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
320     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
321 
322 void AArch64beTargetMachine::anchor() { }
323 
324 AArch64beTargetMachine::AArch64beTargetMachine(
325     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
326     const TargetOptions &Options, Optional<Reloc::Model> RM,
327     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
328     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
329 
330 namespace {
331 
332 /// AArch64 Code Generator Pass Configuration Options.
333 class AArch64PassConfig : public TargetPassConfig {
334 public:
335   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
336       : TargetPassConfig(TM, PM) {
337     if (TM.getOptLevel() != CodeGenOpt::None)
338       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
339   }
340 
341   AArch64TargetMachine &getAArch64TargetMachine() const {
342     return getTM<AArch64TargetMachine>();
343   }
344 
345   ScheduleDAGInstrs *
346   createMachineScheduler(MachineSchedContext *C) const override {
347     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
348     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
349     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
350     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
351     if (ST.hasFusion())
352       DAG->addMutation(createAArch64MacroFusionDAGMutation());
353     return DAG;
354   }
355 
356   ScheduleDAGInstrs *
357   createPostMachineScheduler(MachineSchedContext *C) const override {
358     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
359     if (ST.hasFusion()) {
360       // Run the Macro Fusion after RA again since literals are expanded from
361       // pseudos then (v. addPreSched2()).
362       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
363       DAG->addMutation(createAArch64MacroFusionDAGMutation());
364       return DAG;
365     }
366 
367     return nullptr;
368   }
369 
370   void addIRPasses()  override;
371   bool addPreISel() override;
372   bool addInstSelector() override;
373   bool addIRTranslator() override;
374   void addPreLegalizeMachineIR() override;
375   bool addLegalizeMachineIR() override;
376   bool addRegBankSelect() override;
377   void addPreGlobalInstructionSelect() override;
378   bool addGlobalInstructionSelect() override;
379   bool addILPOpts() override;
380   void addPreRegAlloc() override;
381   void addPostRegAlloc() override;
382   void addPreSched2() override;
383   void addPreEmitPass() override;
384 };
385 
386 } // end anonymous namespace
387 
388 TargetTransformInfo
389 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
390   return TargetTransformInfo(AArch64TTIImpl(this, F));
391 }
392 
393 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
394   return new AArch64PassConfig(*this, PM);
395 }
396 
397 void AArch64PassConfig::addIRPasses() {
398   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
399   // ourselves.
400   addPass(createAtomicExpandPass());
401 
402   // Cmpxchg instructions are often used with a subsequent comparison to
403   // determine whether it succeeded. We can exploit existing control-flow in
404   // ldrex/strex loops to simplify this, but it needs tidying up.
405   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
406     addPass(createCFGSimplificationPass(1, true, true, false, true));
407 
408   // Run LoopDataPrefetch
409   //
410   // Run this before LSR to remove the multiplies involved in computing the
411   // pointer values N iterations ahead.
412   if (TM->getOptLevel() != CodeGenOpt::None) {
413     if (EnableLoopDataPrefetch)
414       addPass(createLoopDataPrefetchPass());
415     if (EnableFalkorHWPFFix)
416       addPass(createFalkorMarkStridedAccessesPass());
417   }
418 
419   TargetPassConfig::addIRPasses();
420 
421   // Match interleaved memory accesses to ldN/stN intrinsics.
422   if (TM->getOptLevel() != CodeGenOpt::None) {
423     addPass(createInterleavedLoadCombinePass());
424     addPass(createInterleavedAccessPass());
425   }
426 
427   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
428     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
429     // and lower a GEP with multiple indices to either arithmetic operations or
430     // multiple GEPs with single index.
431     addPass(createSeparateConstOffsetFromGEPPass(true));
432     // Call EarlyCSE pass to find and remove subexpressions in the lowered
433     // result.
434     addPass(createEarlyCSEPass());
435     // Do loop invariant code motion in case part of the lowered result is
436     // invariant.
437     addPass(createLICMPass());
438   }
439 }
440 
441 // Pass Pipeline Configuration
442 bool AArch64PassConfig::addPreISel() {
443   // Run promote constant before global merge, so that the promoted constants
444   // get a chance to be merged
445   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
446     addPass(createAArch64PromoteConstantPass());
447   // FIXME: On AArch64, this depends on the type.
448   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
449   // and the offset has to be a multiple of the related size in bytes.
450   if ((TM->getOptLevel() != CodeGenOpt::None &&
451        EnableGlobalMerge == cl::BOU_UNSET) ||
452       EnableGlobalMerge == cl::BOU_TRUE) {
453     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
454                                (EnableGlobalMerge == cl::BOU_UNSET);
455     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
456   }
457 
458   return false;
459 }
460 
461 bool AArch64PassConfig::addInstSelector() {
462   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
463 
464   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
465   // references to _TLS_MODULE_BASE_ as possible.
466   if (TM->getTargetTriple().isOSBinFormatELF() &&
467       getOptLevel() != CodeGenOpt::None)
468     addPass(createAArch64CleanupLocalDynamicTLSPass());
469 
470   return false;
471 }
472 
473 bool AArch64PassConfig::addIRTranslator() {
474   addPass(new IRTranslator());
475   return false;
476 }
477 
478 void AArch64PassConfig::addPreLegalizeMachineIR() {
479   addPass(createAArch64PreLegalizeCombiner());
480 }
481 
482 bool AArch64PassConfig::addLegalizeMachineIR() {
483   addPass(new Legalizer());
484   return false;
485 }
486 
487 bool AArch64PassConfig::addRegBankSelect() {
488   addPass(new RegBankSelect());
489   return false;
490 }
491 
492 void AArch64PassConfig::addPreGlobalInstructionSelect() {
493   // Workaround the deficiency of the fast register allocator.
494   if (TM->getOptLevel() == CodeGenOpt::None)
495     addPass(new Localizer());
496 }
497 
498 bool AArch64PassConfig::addGlobalInstructionSelect() {
499   addPass(new InstructionSelect());
500   return false;
501 }
502 
503 bool AArch64PassConfig::addILPOpts() {
504   if (EnableCondOpt)
505     addPass(createAArch64ConditionOptimizerPass());
506   if (EnableCCMP)
507     addPass(createAArch64ConditionalCompares());
508   if (EnableMCR)
509     addPass(&MachineCombinerID);
510   if (EnableCondBrTuning)
511     addPass(createAArch64CondBrTuning());
512   if (EnableEarlyIfConversion)
513     addPass(&EarlyIfConverterID);
514   if (EnableStPairSuppress)
515     addPass(createAArch64StorePairSuppressPass());
516   addPass(createAArch64SIMDInstrOptPass());
517   return true;
518 }
519 
520 void AArch64PassConfig::addPreRegAlloc() {
521   // Change dead register definitions to refer to the zero register.
522   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
523     addPass(createAArch64DeadRegisterDefinitions());
524 
525   // Use AdvSIMD scalar instructions whenever profitable.
526   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
527     addPass(createAArch64AdvSIMDScalar());
528     // The AdvSIMD pass may produce copies that can be rewritten to
529     // be register coaleascer friendly.
530     addPass(&PeepholeOptimizerID);
531   }
532 }
533 
534 void AArch64PassConfig::addPostRegAlloc() {
535   // Remove redundant copy instructions.
536   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
537     addPass(createAArch64RedundantCopyEliminationPass());
538 
539   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
540     // Improve performance for some FP/SIMD code for A57.
541     addPass(createAArch64A57FPLoadBalancing());
542 }
543 
544 void AArch64PassConfig::addPreSched2() {
545   // Expand some pseudo instructions to allow proper scheduling.
546   addPass(createAArch64ExpandPseudoPass());
547   // Use load/store pair instructions when possible.
548   if (TM->getOptLevel() != CodeGenOpt::None) {
549     if (EnableLoadStoreOpt)
550       addPass(createAArch64LoadStoreOptimizationPass());
551     if (EnableFalkorHWPFFix)
552       addPass(createFalkorHWPFFixPass());
553   }
554 }
555 
556 void AArch64PassConfig::addPreEmitPass() {
557   if (EnableA53Fix835769)
558     addPass(createAArch64A53Fix835769());
559   // Relax conditional branch instructions if they're otherwise out of
560   // range of their destination.
561   if (BranchRelaxation)
562     addPass(&BranchRelaxationPassID);
563 
564   if (EnableBranchTargets)
565     addPass(createAArch64BranchTargetsPass());
566 
567   if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
568     addPass(createAArch64CompressJumpTablesPass());
569 
570   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
571       TM->getTargetTriple().isOSBinFormatMachO())
572     addPass(createAArch64CollectLOHPass());
573 }
574