1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
14 #include "AArch64MachineFunctionInfo.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetObjectFile.h"
18 #include "AArch64TargetTransformInfo.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "TargetInfo/AArch64TargetInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/CSEConfigBase.h"
25 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
26 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
27 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
28 #include "llvm/CodeGen/GlobalISel/Localizer.h"
29 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
30 #include "llvm/CodeGen/MIRParser/MIParser.h"
31 #include "llvm/CodeGen/MachineScheduler.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/TargetPassConfig.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/InitializePasses.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCTargetOptions.h"
39 #include "llvm/Pass.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/TargetRegistry.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Transforms/CFGuard.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include <memory>
48 #include <string>
49 
50 using namespace llvm;
51 
52 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
53                                 cl::desc("Enable the CCMP formation pass"),
54                                 cl::init(true), cl::Hidden);
55 
56 static cl::opt<bool>
57     EnableCondBrTuning("aarch64-enable-cond-br-tune",
58                        cl::desc("Enable the conditional branch tuning pass"),
59                        cl::init(true), cl::Hidden);
60 
61 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
62                                cl::desc("Enable the machine combiner pass"),
63                                cl::init(true), cl::Hidden);
64 
65 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
66                                           cl::desc("Suppress STP for AArch64"),
67                                           cl::init(true), cl::Hidden);
68 
69 static cl::opt<bool> EnableAdvSIMDScalar(
70     "aarch64-enable-simd-scalar",
71     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
72     cl::init(false), cl::Hidden);
73 
74 static cl::opt<bool>
75     EnablePromoteConstant("aarch64-enable-promote-const",
76                           cl::desc("Enable the promote constant pass"),
77                           cl::init(true), cl::Hidden);
78 
79 static cl::opt<bool> EnableCollectLOH(
80     "aarch64-enable-collect-loh",
81     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
82     cl::init(true), cl::Hidden);
83 
84 static cl::opt<bool>
85     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
86                                   cl::desc("Enable the pass that removes dead"
87                                            " definitons and replaces stores to"
88                                            " them with stores to the zero"
89                                            " register"),
90                                   cl::init(true));
91 
92 static cl::opt<bool> EnableRedundantCopyElimination(
93     "aarch64-enable-copyelim",
94     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
95     cl::Hidden);
96 
97 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
98                                         cl::desc("Enable the load/store pair"
99                                                  " optimization pass"),
100                                         cl::init(true), cl::Hidden);
101 
102 static cl::opt<bool> EnableAtomicTidy(
103     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
104     cl::desc("Run SimplifyCFG after expanding atomic operations"
105              " to make use of cmpxchg flow-based information"),
106     cl::init(true));
107 
108 static cl::opt<bool>
109 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
110                         cl::desc("Run early if-conversion"),
111                         cl::init(true));
112 
113 static cl::opt<bool>
114     EnableCondOpt("aarch64-enable-condopt",
115                   cl::desc("Enable the condition optimizer pass"),
116                   cl::init(true), cl::Hidden);
117 
118 static cl::opt<bool>
119 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
120                 cl::desc("Work around Cortex-A53 erratum 835769"),
121                 cl::init(false));
122 
123 static cl::opt<bool>
124     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
125                  cl::desc("Enable optimizations on complex GEPs"),
126                  cl::init(false));
127 
128 static cl::opt<bool>
129     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
130                      cl::desc("Relax out of range conditional branches"));
131 
132 static cl::opt<bool> EnableCompressJumpTables(
133     "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
134     cl::desc("Use smallest entry possible for jump tables"));
135 
136 // FIXME: Unify control over GlobalMerge.
137 static cl::opt<cl::boolOrDefault>
138     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
139                       cl::desc("Enable the global merge pass"));
140 
141 static cl::opt<bool>
142     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
143                            cl::desc("Enable the loop data prefetch pass"),
144                            cl::init(true));
145 
146 static cl::opt<int> EnableGlobalISelAtO(
147     "aarch64-enable-global-isel-at-O", cl::Hidden,
148     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
149     cl::init(0));
150 
151 static cl::opt<bool> EnableSVEIntrinsicOpts(
152     "aarch64-sve-intrinsic-opts", cl::Hidden,
153     cl::desc("Enable SVE intrinsic opts"),
154     cl::init(true));
155 
156 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
157                                          cl::init(true), cl::Hidden);
158 
159 static cl::opt<bool>
160     EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
161                         cl::desc("Enable the AAcrh64 branch target pass"),
162                         cl::init(true));
163 
164 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
165   // Register the target.
166   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
167   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
168   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
169   RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
170   RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
171   auto PR = PassRegistry::getPassRegistry();
172   initializeGlobalISel(*PR);
173   initializeAArch64A53Fix835769Pass(*PR);
174   initializeAArch64A57FPLoadBalancingPass(*PR);
175   initializeAArch64AdvSIMDScalarPass(*PR);
176   initializeAArch64BranchTargetsPass(*PR);
177   initializeAArch64CollectLOHPass(*PR);
178   initializeAArch64CompressJumpTablesPass(*PR);
179   initializeAArch64ConditionalComparesPass(*PR);
180   initializeAArch64ConditionOptimizerPass(*PR);
181   initializeAArch64DeadRegisterDefinitionsPass(*PR);
182   initializeAArch64ExpandPseudoPass(*PR);
183   initializeAArch64LoadStoreOptPass(*PR);
184   initializeAArch64SIMDInstrOptPass(*PR);
185   initializeAArch64PreLegalizerCombinerPass(*PR);
186   initializeAArch64PromoteConstantPass(*PR);
187   initializeAArch64RedundantCopyEliminationPass(*PR);
188   initializeAArch64StorePairSuppressPass(*PR);
189   initializeFalkorHWPFFixPass(*PR);
190   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
191   initializeLDTLSCleanupPass(*PR);
192   initializeSVEIntrinsicOptsPass(*PR);
193   initializeAArch64SpeculationHardeningPass(*PR);
194   initializeAArch64StackTaggingPass(*PR);
195   initializeAArch64StackTaggingPreRAPass(*PR);
196 }
197 
198 //===----------------------------------------------------------------------===//
199 // AArch64 Lowering public interface.
200 //===----------------------------------------------------------------------===//
201 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
202   if (TT.isOSBinFormatMachO())
203     return std::make_unique<AArch64_MachoTargetObjectFile>();
204   if (TT.isOSBinFormatCOFF())
205     return std::make_unique<AArch64_COFFTargetObjectFile>();
206 
207   return std::make_unique<AArch64_ELFTargetObjectFile>();
208 }
209 
210 // Helper function to build a DataLayout string
211 static std::string computeDataLayout(const Triple &TT,
212                                      const MCTargetOptions &Options,
213                                      bool LittleEndian) {
214   if (Options.getABIName() == "ilp32")
215     return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
216   if (TT.isOSBinFormatMachO()) {
217     if (TT.getArch() == Triple::aarch64_32)
218       return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
219     return "e-m:o-i64:64-i128:128-n32:64-S128";
220   }
221   if (TT.isOSBinFormatCOFF())
222     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
223   if (LittleEndian)
224     return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
225   return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
226 }
227 
228 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
229                                            Optional<Reloc::Model> RM) {
230   // AArch64 Darwin and Windows are always PIC.
231   if (TT.isOSDarwin() || TT.isOSWindows())
232     return Reloc::PIC_;
233   // On ELF platforms the default static relocation model has a smart enough
234   // linker to cope with referencing external symbols defined in a shared
235   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
236   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
237     return Reloc::Static;
238   return *RM;
239 }
240 
241 static CodeModel::Model
242 getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
243                              bool JIT) {
244   if (CM) {
245     if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
246         *CM != CodeModel::Large) {
247       report_fatal_error(
248           "Only small, tiny and large code models are allowed on AArch64");
249     } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
250       report_fatal_error("tiny code model is only supported on ELF");
251     return *CM;
252   }
253   // The default MCJIT memory managers make no guarantees about where they can
254   // find an executable page; JITed code needs to be able to refer to globals
255   // no matter how far away they are.
256   // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
257   // since with large code model LLVM generating 4 MOV instructions, and
258   // Windows doesn't support relocating these long branch (4 MOVs).
259   if (JIT && !TT.isOSWindows())
260     return CodeModel::Large;
261   return CodeModel::Small;
262 }
263 
264 /// Create an AArch64 architecture model.
265 ///
266 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
267                                            StringRef CPU, StringRef FS,
268                                            const TargetOptions &Options,
269                                            Optional<Reloc::Model> RM,
270                                            Optional<CodeModel::Model> CM,
271                                            CodeGenOpt::Level OL, bool JIT,
272                                            bool LittleEndian)
273     : LLVMTargetMachine(T,
274                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
275                         TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
276                         getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
277       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
278   initAsmInfo();
279 
280   if (TT.isOSBinFormatMachO()) {
281     this->Options.TrapUnreachable = true;
282     this->Options.NoTrapAfterNoreturn = true;
283   }
284 
285   if (getMCAsmInfo()->usesWindowsCFI()) {
286     // Unwinding can get confused if the last instruction in an
287     // exception-handling region (function, funclet, try block, etc.)
288     // is a call.
289     //
290     // FIXME: We could elide the trap if the next instruction would be in
291     // the same region anyway.
292     this->Options.TrapUnreachable = true;
293   }
294 
295   if (this->Options.TLSSize == 0) // default
296     this->Options.TLSSize = 24;
297   if ((getCodeModel() == CodeModel::Small ||
298        getCodeModel() == CodeModel::Kernel) &&
299       this->Options.TLSSize > 32)
300     // for the small (and kernel) code model, the maximum TLS size is 4GiB
301     this->Options.TLSSize = 32;
302   else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
303     // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
304     this->Options.TLSSize = 24;
305 
306   // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
307   // MachO/CodeModel::Large, which GlobalISel does not support.
308   if (getOptLevel() <= EnableGlobalISelAtO &&
309       TT.getArch() != Triple::aarch64_32 &&
310       !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
311     setGlobalISel(true);
312     setGlobalISelAbort(GlobalISelAbortMode::Disable);
313   }
314 
315   // AArch64 supports the MachineOutliner.
316   setMachineOutliner(true);
317 
318   // AArch64 supports default outlining behaviour.
319   setSupportsDefaultOutlining(true);
320 
321   // AArch64 supports the debug entry values.
322   setSupportsDebugEntryValues(true);
323 }
324 
325 AArch64TargetMachine::~AArch64TargetMachine() = default;
326 
327 const AArch64Subtarget *
328 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
329   Attribute CPUAttr = F.getFnAttribute("target-cpu");
330   Attribute FSAttr = F.getFnAttribute("target-features");
331 
332   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
333                         ? CPUAttr.getValueAsString().str()
334                         : TargetCPU;
335   std::string FS = !FSAttr.hasAttribute(Attribute::None)
336                        ? FSAttr.getValueAsString().str()
337                        : TargetFS;
338 
339   auto &I = SubtargetMap[CPU + FS];
340   if (!I) {
341     // This needs to be done before we create a new subtarget since any
342     // creation will depend on the TM and the code generation flags on the
343     // function that reside in TargetOptions.
344     resetTargetOptions(F);
345     I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
346                                             isLittle);
347   }
348   return I.get();
349 }
350 
351 void AArch64leTargetMachine::anchor() { }
352 
353 AArch64leTargetMachine::AArch64leTargetMachine(
354     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
355     const TargetOptions &Options, Optional<Reloc::Model> RM,
356     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
357     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
358 
359 void AArch64beTargetMachine::anchor() { }
360 
361 AArch64beTargetMachine::AArch64beTargetMachine(
362     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
363     const TargetOptions &Options, Optional<Reloc::Model> RM,
364     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
365     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
366 
367 namespace {
368 
369 /// AArch64 Code Generator Pass Configuration Options.
370 class AArch64PassConfig : public TargetPassConfig {
371 public:
372   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
373       : TargetPassConfig(TM, PM) {
374     if (TM.getOptLevel() != CodeGenOpt::None)
375       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
376   }
377 
378   AArch64TargetMachine &getAArch64TargetMachine() const {
379     return getTM<AArch64TargetMachine>();
380   }
381 
382   ScheduleDAGInstrs *
383   createMachineScheduler(MachineSchedContext *C) const override {
384     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
385     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
386     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
387     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
388     if (ST.hasFusion())
389       DAG->addMutation(createAArch64MacroFusionDAGMutation());
390     return DAG;
391   }
392 
393   ScheduleDAGInstrs *
394   createPostMachineScheduler(MachineSchedContext *C) const override {
395     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
396     if (ST.hasFusion()) {
397       // Run the Macro Fusion after RA again since literals are expanded from
398       // pseudos then (v. addPreSched2()).
399       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
400       DAG->addMutation(createAArch64MacroFusionDAGMutation());
401       return DAG;
402     }
403 
404     return nullptr;
405   }
406 
407   void addIRPasses()  override;
408   bool addPreISel() override;
409   bool addInstSelector() override;
410   bool addIRTranslator() override;
411   void addPreLegalizeMachineIR() override;
412   bool addLegalizeMachineIR() override;
413   bool addRegBankSelect() override;
414   void addPreGlobalInstructionSelect() override;
415   bool addGlobalInstructionSelect() override;
416   bool addILPOpts() override;
417   void addPreRegAlloc() override;
418   void addPostRegAlloc() override;
419   void addPreSched2() override;
420   void addPreEmitPass() override;
421 
422   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
423 };
424 
425 } // end anonymous namespace
426 
427 TargetTransformInfo
428 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
429   return TargetTransformInfo(AArch64TTIImpl(this, F));
430 }
431 
432 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
433   return new AArch64PassConfig(*this, PM);
434 }
435 
436 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
437   return getStandardCSEConfigForOpt(TM->getOptLevel());
438 }
439 
440 void AArch64PassConfig::addIRPasses() {
441   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
442   // ourselves.
443   addPass(createAtomicExpandPass());
444 
445   // Expand any SVE vector library calls that we can't code generate directly.
446   if (EnableSVEIntrinsicOpts && TM->getOptLevel() == CodeGenOpt::Aggressive)
447     addPass(createSVEIntrinsicOptsPass());
448 
449   // Cmpxchg instructions are often used with a subsequent comparison to
450   // determine whether it succeeded. We can exploit existing control-flow in
451   // ldrex/strex loops to simplify this, but it needs tidying up.
452   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
453     addPass(createCFGSimplificationPass(1, true, true, false, true));
454 
455   // Run LoopDataPrefetch
456   //
457   // Run this before LSR to remove the multiplies involved in computing the
458   // pointer values N iterations ahead.
459   if (TM->getOptLevel() != CodeGenOpt::None) {
460     if (EnableLoopDataPrefetch)
461       addPass(createLoopDataPrefetchPass());
462     if (EnableFalkorHWPFFix)
463       addPass(createFalkorMarkStridedAccessesPass());
464   }
465 
466   TargetPassConfig::addIRPasses();
467 
468   // Match interleaved memory accesses to ldN/stN intrinsics.
469   if (TM->getOptLevel() != CodeGenOpt::None) {
470     addPass(createInterleavedLoadCombinePass());
471     addPass(createInterleavedAccessPass());
472   }
473 
474   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
475     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
476     // and lower a GEP with multiple indices to either arithmetic operations or
477     // multiple GEPs with single index.
478     addPass(createSeparateConstOffsetFromGEPPass(true));
479     // Call EarlyCSE pass to find and remove subexpressions in the lowered
480     // result.
481     addPass(createEarlyCSEPass());
482     // Do loop invariant code motion in case part of the lowered result is
483     // invariant.
484     addPass(createLICMPass());
485   }
486 
487   addPass(createAArch64StackTaggingPass(/* MergeInit = */ TM->getOptLevel() !=
488                                         CodeGenOpt::None));
489 
490   // Add Control Flow Guard checks.
491   if (TM->getTargetTriple().isOSWindows())
492     addPass(createCFGuardCheckPass());
493 }
494 
495 // Pass Pipeline Configuration
496 bool AArch64PassConfig::addPreISel() {
497   // Run promote constant before global merge, so that the promoted constants
498   // get a chance to be merged
499   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
500     addPass(createAArch64PromoteConstantPass());
501   // FIXME: On AArch64, this depends on the type.
502   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
503   // and the offset has to be a multiple of the related size in bytes.
504   if ((TM->getOptLevel() != CodeGenOpt::None &&
505        EnableGlobalMerge == cl::BOU_UNSET) ||
506       EnableGlobalMerge == cl::BOU_TRUE) {
507     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
508                                (EnableGlobalMerge == cl::BOU_UNSET);
509 
510     // Merging of extern globals is enabled by default on non-Mach-O as we
511     // expect it to be generally either beneficial or harmless. On Mach-O it
512     // is disabled as we emit the .subsections_via_symbols directive which
513     // means that merging extern globals is not safe.
514     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
515 
516     // FIXME: extern global merging is only enabled when we optimise for size
517     // because there are some regressions with it also enabled for performance.
518     if (!OnlyOptimizeForSize)
519       MergeExternalByDefault = false;
520 
521     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
522                                   MergeExternalByDefault));
523   }
524 
525   return false;
526 }
527 
528 bool AArch64PassConfig::addInstSelector() {
529   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
530 
531   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
532   // references to _TLS_MODULE_BASE_ as possible.
533   if (TM->getTargetTriple().isOSBinFormatELF() &&
534       getOptLevel() != CodeGenOpt::None)
535     addPass(createAArch64CleanupLocalDynamicTLSPass());
536 
537   return false;
538 }
539 
540 bool AArch64PassConfig::addIRTranslator() {
541   addPass(new IRTranslator());
542   return false;
543 }
544 
545 void AArch64PassConfig::addPreLegalizeMachineIR() {
546   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
547   addPass(createAArch64PreLegalizeCombiner(IsOptNone));
548 }
549 
550 bool AArch64PassConfig::addLegalizeMachineIR() {
551   addPass(new Legalizer());
552   return false;
553 }
554 
555 bool AArch64PassConfig::addRegBankSelect() {
556   addPass(new RegBankSelect());
557   return false;
558 }
559 
560 void AArch64PassConfig::addPreGlobalInstructionSelect() {
561   addPass(new Localizer());
562 }
563 
564 bool AArch64PassConfig::addGlobalInstructionSelect() {
565   addPass(new InstructionSelect());
566   return false;
567 }
568 
569 bool AArch64PassConfig::addILPOpts() {
570   if (EnableCondOpt)
571     addPass(createAArch64ConditionOptimizerPass());
572   if (EnableCCMP)
573     addPass(createAArch64ConditionalCompares());
574   if (EnableMCR)
575     addPass(&MachineCombinerID);
576   if (EnableCondBrTuning)
577     addPass(createAArch64CondBrTuning());
578   if (EnableEarlyIfConversion)
579     addPass(&EarlyIfConverterID);
580   if (EnableStPairSuppress)
581     addPass(createAArch64StorePairSuppressPass());
582   addPass(createAArch64SIMDInstrOptPass());
583   if (TM->getOptLevel() != CodeGenOpt::None)
584     addPass(createAArch64StackTaggingPreRAPass());
585   return true;
586 }
587 
588 void AArch64PassConfig::addPreRegAlloc() {
589   // Change dead register definitions to refer to the zero register.
590   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
591     addPass(createAArch64DeadRegisterDefinitions());
592 
593   // Use AdvSIMD scalar instructions whenever profitable.
594   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
595     addPass(createAArch64AdvSIMDScalar());
596     // The AdvSIMD pass may produce copies that can be rewritten to
597     // be register coalescer friendly.
598     addPass(&PeepholeOptimizerID);
599   }
600 }
601 
602 void AArch64PassConfig::addPostRegAlloc() {
603   // Remove redundant copy instructions.
604   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
605     addPass(createAArch64RedundantCopyEliminationPass());
606 
607   if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
608     // Improve performance for some FP/SIMD code for A57.
609     addPass(createAArch64A57FPLoadBalancing());
610 }
611 
612 void AArch64PassConfig::addPreSched2() {
613   // Expand some pseudo instructions to allow proper scheduling.
614   addPass(createAArch64ExpandPseudoPass());
615   // Use load/store pair instructions when possible.
616   if (TM->getOptLevel() != CodeGenOpt::None) {
617     if (EnableLoadStoreOpt)
618       addPass(createAArch64LoadStoreOptimizationPass());
619   }
620 
621   // The AArch64SpeculationHardeningPass destroys dominator tree and natural
622   // loop info, which is needed for the FalkorHWPFFixPass and also later on.
623   // Therefore, run the AArch64SpeculationHardeningPass before the
624   // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
625   // info.
626   addPass(createAArch64SpeculationHardeningPass());
627 
628   if (TM->getOptLevel() != CodeGenOpt::None) {
629     if (EnableFalkorHWPFFix)
630       addPass(createFalkorHWPFFixPass());
631   }
632 }
633 
634 void AArch64PassConfig::addPreEmitPass() {
635   // Machine Block Placement might have created new opportunities when run
636   // at O3, where the Tail Duplication Threshold is set to 4 instructions.
637   // Run the load/store optimizer once more.
638   if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
639     addPass(createAArch64LoadStoreOptimizationPass());
640 
641   if (EnableA53Fix835769)
642     addPass(createAArch64A53Fix835769());
643 
644   if (EnableBranchTargets)
645     addPass(createAArch64BranchTargetsPass());
646 
647   // Relax conditional branch instructions if they're otherwise out of
648   // range of their destination.
649   if (BranchRelaxation)
650     addPass(&BranchRelaxationPassID);
651 
652   // Identify valid longjmp targets for Windows Control Flow Guard.
653   if (TM->getTargetTriple().isOSWindows())
654     addPass(createCFGuardLongjmpPass());
655 
656   if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
657     addPass(createAArch64CompressJumpTablesPass());
658 
659   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
660       TM->getTargetTriple().isOSBinFormatMachO())
661     addPass(createAArch64CollectLOHPass());
662 
663   // SVE bundles move prefixes with destructive operations.
664   addPass(createUnpackMachineBundles(nullptr));
665 }
666 
667 yaml::MachineFunctionInfo *
668 AArch64TargetMachine::createDefaultFuncInfoYAML() const {
669   return new yaml::AArch64FunctionInfo();
670 }
671 
672 yaml::MachineFunctionInfo *
673 AArch64TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
674   const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
675   return new yaml::AArch64FunctionInfo(*MFI);
676 }
677 
678 bool AArch64TargetMachine::parseMachineFunctionInfo(
679     const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
680     SMDiagnostic &Error, SMRange &SourceRange) const {
681   const auto &YamlMFI =
682       reinterpret_cast<const yaml::AArch64FunctionInfo &>(MFI);
683   MachineFunction &MF = PFS.MF;
684   MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
685   return false;
686 }
687