1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64.h"
14 #include "AArch64TargetMachine.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/TargetRegistry.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Transforms/Scalar.h"
21 using namespace llvm;
22 
23 static cl::opt<bool>
24 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
25            cl::init(true), cl::Hidden);
26 
27 static cl::opt<bool> EnableMCR("aarch64-mcr",
28                                cl::desc("Enable the machine combiner pass"),
29                                cl::init(true), cl::Hidden);
30 
31 static cl::opt<bool>
32 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
33                      cl::init(true), cl::Hidden);
34 
35 static cl::opt<bool>
36 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
37                     " integer instructions"), cl::init(false), cl::Hidden);
38 
39 static cl::opt<bool>
40 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
41                       "constant pass"), cl::init(true), cl::Hidden);
42 
43 static cl::opt<bool>
44 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
45                  " linker optimization hints (LOH)"), cl::init(true),
46                  cl::Hidden);
47 
48 static cl::opt<bool>
49 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
50                               cl::desc("Enable the pass that removes dead"
51                                        " definitons and replaces stores to"
52                                        " them with stores to the zero"
53                                        " register"),
54                               cl::init(true));
55 
56 static cl::opt<bool>
57 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
58                    " optimization pass"), cl::init(true), cl::Hidden);
59 
60 static cl::opt<bool>
61 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
62                  cl::desc("Run SimplifyCFG after expanding atomic operations"
63                           " to make use of cmpxchg flow-based information"),
64                  cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(true));
70 
71 
72 extern "C" void LLVMInitializeAArch64Target() {
73   // Register the target.
74   RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
75   RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
76   RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
77 }
78 
79 /// TargetMachine ctor - Create an AArch64 architecture model.
80 ///
81 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
82                                            StringRef CPU, StringRef FS,
83                                            const TargetOptions &Options,
84                                            Reloc::Model RM, CodeModel::Model CM,
85                                            CodeGenOpt::Level OL,
86                                            bool LittleEndian)
87     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
88       Subtarget(TT, CPU, FS, *this, LittleEndian) {
89   initAsmInfo();
90 }
91 
92 void AArch64leTargetMachine::anchor() { }
93 
94 AArch64leTargetMachine::
95 AArch64leTargetMachine(const Target &T, StringRef TT,
96                        StringRef CPU, StringRef FS, const TargetOptions &Options,
97                        Reloc::Model RM, CodeModel::Model CM,
98                        CodeGenOpt::Level OL)
99   : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
100 
101 void AArch64beTargetMachine::anchor() { }
102 
103 AArch64beTargetMachine::
104 AArch64beTargetMachine(const Target &T, StringRef TT,
105                        StringRef CPU, StringRef FS, const TargetOptions &Options,
106                        Reloc::Model RM, CodeModel::Model CM,
107                        CodeGenOpt::Level OL)
108   : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
109 
110 namespace {
111 /// AArch64 Code Generator Pass Configuration Options.
112 class AArch64PassConfig : public TargetPassConfig {
113 public:
114   AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
115       : TargetPassConfig(TM, PM) {}
116 
117   AArch64TargetMachine &getAArch64TargetMachine() const {
118     return getTM<AArch64TargetMachine>();
119   }
120 
121   void addIRPasses()  override;
122   bool addPreISel() override;
123   bool addInstSelector() override;
124   bool addILPOpts() override;
125   bool addPreRegAlloc() override;
126   bool addPostRegAlloc() override;
127   bool addPreSched2() override;
128   bool addPreEmitPass() override;
129 };
130 } // namespace
131 
132 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
133   // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
134   // allows the AArch64 pass to delegate to the target independent layer when
135   // appropriate.
136   PM.add(createBasicTargetTransformInfoPass(this));
137   PM.add(createAArch64TargetTransformInfoPass(this));
138 }
139 
140 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
141   return new AArch64PassConfig(this, PM);
142 }
143 
144 void AArch64PassConfig::addIRPasses() {
145   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
146   // ourselves.
147   addPass(createAtomicExpandLoadLinkedPass(TM));
148 
149   // Cmpxchg instructions are often used with a subsequent comparison to
150   // determine whether it succeeded. We can exploit existing control-flow in
151   // ldrex/strex loops to simplify this, but it needs tidying up.
152   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
153     addPass(createCFGSimplificationPass());
154 
155   TargetPassConfig::addIRPasses();
156 }
157 
158 // Pass Pipeline Configuration
159 bool AArch64PassConfig::addPreISel() {
160   // Run promote constant before global merge, so that the promoted constants
161   // get a chance to be merged
162   if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
163     addPass(createAArch64PromoteConstantPass());
164   if (TM->getOptLevel() != CodeGenOpt::None)
165     addPass(createGlobalMergePass(TM));
166   if (TM->getOptLevel() != CodeGenOpt::None)
167     addPass(createAArch64AddressTypePromotionPass());
168 
169   return false;
170 }
171 
172 bool AArch64PassConfig::addInstSelector() {
173   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
174 
175   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
176   // references to _TLS_MODULE_BASE_ as possible.
177   if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
178       getOptLevel() != CodeGenOpt::None)
179     addPass(createAArch64CleanupLocalDynamicTLSPass());
180 
181   return false;
182 }
183 
184 bool AArch64PassConfig::addILPOpts() {
185   if (EnableCCMP)
186     addPass(createAArch64ConditionalCompares());
187   if (EnableMCR)
188     addPass(&MachineCombinerID);
189   if (EnableEarlyIfConversion)
190     addPass(&EarlyIfConverterID);
191   if (EnableStPairSuppress)
192     addPass(createAArch64StorePairSuppressPass());
193   return true;
194 }
195 
196 bool AArch64PassConfig::addPreRegAlloc() {
197   // Use AdvSIMD scalar instructions whenever profitable.
198   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar)
199     addPass(createAArch64AdvSIMDScalar());
200   return true;
201 }
202 
203 bool AArch64PassConfig::addPostRegAlloc() {
204   // Change dead register definitions to refer to the zero register.
205   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
206     addPass(createAArch64DeadRegisterDefinitions());
207   if (TM->getOptLevel() != CodeGenOpt::None &&
208       TM->getSubtarget<AArch64Subtarget>().isCortexA57())
209     // Improve performance for some FP/SIMD code for A57.
210     addPass(createAArch64A57FPLoadBalancing());
211   return true;
212 }
213 
214 bool AArch64PassConfig::addPreSched2() {
215   // Expand some pseudo instructions to allow proper scheduling.
216   addPass(createAArch64ExpandPseudoPass());
217   // Use load/store pair instructions when possible.
218   if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
219     addPass(createAArch64LoadStoreOptimizationPass());
220   return true;
221 }
222 
223 bool AArch64PassConfig::addPreEmitPass() {
224   // Relax conditional branch instructions if they're otherwise out of
225   // range of their destination.
226   addPass(createAArch64BranchRelaxation());
227   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
228       TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
229     addPass(createAArch64CollectLOHPass());
230   return true;
231 }
232